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arm64: dts: rockchip: Enable DisplayPort for rk3588-evb2

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The rk3588 evb2 board has a full size DisplayPort connector, enable
for it.

Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Chaoyi Chen 2025-09-18 14:28:25 +08:00 committed by Heiko Stuebner
parent 7fee888827
commit 134fae98cf
1 changed files with 48 additions and 0 deletions
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48
arch/arm64/boot/dts/rockchip/rk3588-evb2-v10.dts
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@ -25,6 +25,18 @@
stdout-path = "serial2:1500000n8";
};
dp-con {
compatible = "dp-connector";
label = "DP OUT";
type = "full-size";
port {
dp_con_in: endpoint {
remote-endpoint = <&dp0_out_con>;
};
};
};
hdmi-con {
compatible = "hdmi-connector";
type = "a";
@ -106,6 +118,24 @@
};
};
&dp0 {
pinctrl-0 = <&dp0m0_pins>;
pinctrl-names = "default";
status = "okay";
};
&dp0_in {
dp0_in_vp2: endpoint {
remote-endpoint = <&vp2_out_dp0>;
};
};
&dp0_out {
dp0_out_con: endpoint {
remote-endpoint = <&dp_con_in>;
};
};
&gpu {
mali-supply = <&vdd_gpu_s0>;
sram-supply = <&vdd_gpu_mem_s0>;
@ -916,6 +946,17 @@
};
&vop {
/*
* If no dedicated PLL was specified, the GPLL would be automatically
* assigned as the PLL source for dclk_vop2. As the frequency of GPLL
* is 1188 MHz, we can only get typical clock frequencies such as
* 74.25MHz, 148.5MHz, 297MHz, 594MHz.
*
* So here we set the parent clock of VP2 to V0PLL so that we can get
* any frequency.
*/
assigned-clocks = <&cru DCLK_VOP2_SRC>;
assigned-clock-parents = <&cru PLL_V0PLL>;
status = "okay";
};
@ -929,3 +970,10 @@
remote-endpoint = <&hdmi0_in_vp0>;
};
};
&vp2 {
vp2_out_dp0: endpoint@a {
reg = <ROCKCHIP_VOP2_EP_DP0>;
remote-endpoint = <&dp0_in_vp2>;
};
};