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arm64: dts: ti: k3-j784s4-ti-ipc-firmware: Refactor IPC cfg into new dtsi

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The TI K3 J784S4 SoCs have multiple programmable remote processors like
R5F, C7x etc. The TI SDKs for J784S4 SoCs offer sample firmwares which
could be run on these cores to demonstrate an "echo" IPC test. Those
firmware require certain memory carveouts to be reserved from system
memory, timers to be reserved, and certain mailbox configurations for
interrupt based messaging. These configurations could be different for a
different firmware.

While DT is not meant for system configurations, at least refactor these
configurations from board level DTS into a dtsi for now. This dtsi for
TI IPC firmware is board-independent and can be applied to all boards
from the same SoC Family. This gets rid of code duplication and allows
more freedom for users developing custom firmware (or no firmware) to
utilize system resources better; easily by swapping out this dtsi. To
maintain backward compatibility, the dtsi is included in all boards.

This patch only refactors the C71_3 remote processor related nodes into
the new dtsi. All other nodes have been refactored in the previous
commit as part of k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi.

Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Link: https://patch.msgid.link/20250908142826.1828676-29-b-padhi@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Beleswar Padhi 2025-09-08 19:58:20 +05:30 committed by Nishanth Menon
parent 3dabfaa168
commit 2742d963e1
3 changed files with 37 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
arch/arm64/boot/dts/ti/k3-am69-sk.dts
View File

@ -60,18 +60,6 @@
reg = <0x00 0xa0100000 0x00 0xf00000>;
no-map;
};
c71_3_dma_memory_region: memory@ab000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab000000 0x00 0x100000>;
no-map;
};
c71_3_memory_region: memory@ab100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab100000 0x00 0xf00000>;
no-map;
};
};
vusb_main: regulator-vusb-main5v0 {
@ -520,13 +508,6 @@
bootph-all;
};
&mailbox0_cluster5 {
mbox_c71_3: mbox-c71-3 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&wkup_uart0 {
/* Firmware usage */
status = "reserved";
@ -795,13 +776,6 @@
bootph-all;
};
&c71_3 {
status = "okay";
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
memory-region = <&c71_3_dma_memory_region>,
<&c71_3_memory_region>;
};
&wkup_gpio_intr {
status = "okay";
};
@ -1086,3 +1060,4 @@
};
#include "k3-j784s4-j742s2-ti-ipc-firmware-common.dtsi"
#include "k3-j784s4-ti-ipc-firmware.dtsi"

26
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
View File

@ -27,31 +27,7 @@
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
c71_3_dma_memory_region: memory@ab000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab000000 0x00 0x100000>;
no-map;
};
c71_3_memory_region: memory@ab100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab100000 0x00 0xf00000>;
no-map;
};
};
};
&mailbox0_cluster5 {
mbox_c71_3: mbox-c71-3 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&c71_3 {
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
memory-region = <&c71_3_dma_memory_region>,
<&c71_3_memory_region>;
status = "okay";
};
#include "k3-j784s4-ti-ipc-firmware.dtsi"

35
arch/arm64/boot/dts/ti/k3-j784s4-ti-ipc-firmware.dtsi Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* Device Tree Source for enabling IPC using TI SDK firmware on J784S4 SoCs
*
* Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
&reserved_memory {
c71_3_dma_memory_region: memory@ab000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab000000 0x00 0x100000>;
no-map;
};
c71_3_memory_region: memory@ab100000 {
compatible = "shared-dma-pool";
reg = <0x00 0xab100000 0x00 0xf00000>;
no-map;
};
};
&mailbox0_cluster5 {
mbox_c71_3: mbox-c71-3 {
ti,mbox-rx = <2 0 0>;
ti,mbox-tx = <3 0 0>;
};
};
&c71_3 {
mboxes = <&mailbox0_cluster5 &mbox_c71_3>;
memory-region = <&c71_3_dma_memory_region>,
<&c71_3_memory_region>;
status = "okay";
};