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pci-v6.19-fixes-2

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Merge tag 'pci-v6.19-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull PCI fixes from Bjorn Helgaas:

 - Remove ASPM L0s support for MSM8996 SoC since we now enable L0s when
   advertised, and it caused random hangs on this device (Manivannan
   Sadhasivam)

 - Fix meson-pcie to report that the link is up while in ASPM L0s or L1,
   since those are active states from the software point of view, and
   treating the link as down caused config access failures (Bjorn
   Helgaas)

 - Fix up sparc DTS BAR descriptions that are above 4GB but not marked
   as prefetchable, which caused resource assignment and driver probe
   failures after we converted from the SPARC pcibios_enable_device() to
   the generic version (Ilpo Järvinen)

* tag 'pci-v6.19-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
  sparc/PCI: Correct 64-bit non-pref -> pref BAR resources
  PCI: meson: Report that link is up while in ASPM L0s and L1 states
  PCI: qcom: Remove ASPM L0s support for MSM8996 SoC
This commit is contained in:
Linus Torvalds 2026-01-09 06:41:10 -10:00
commit 4d6fe1dd12
3 changed files with 29 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/sparc/kernel/pci.c
View File

@ -181,6 +181,28 @@ static int __init ofpci_debug(char *str)
__setup("ofpci_debug=", ofpci_debug);
static void of_fixup_pci_pref(struct pci_dev *dev, int index,
struct resource *res)
{
struct pci_bus_region region;
if (!(res->flags & IORESOURCE_MEM_64))
return;
if (!resource_size(res))
return;
pcibios_resource_to_bus(dev->bus, &region, res);
if (region.end <= ~((u32)0))
return;
if (!(res->flags & IORESOURCE_PREFETCH)) {
res->flags |= IORESOURCE_PREFETCH;
pci_info(dev, "reg 0x%x: fixup: pref added to 64-bit resource\n",
index);
}
}
static unsigned long pci_parse_of_flags(u32 addr0)
{
unsigned long flags = 0;
@ -244,6 +266,7 @@ static void pci_parse_of_addrs(struct platform_device *op,
res->end = op_res->end;
res->flags = flags;
res->name = pci_name(dev);
of_fixup_pci_pref(dev, i, res);
pci_info(dev, "reg 0x%x: %pR\n", i, res);
}

37
drivers/pci/controller/dwc/pci-meson.c
View File

@ -37,7 +37,6 @@
#define PCIE_CFG_STATUS17 0x44
#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
#define WAIT_LINKUP_TIMEOUT 4000
#define PORT_CLK_RATE 100000000UL
#define MAX_PAYLOAD_SIZE 256
#define MAX_READ_REQ_SIZE 256
@ -350,40 +349,10 @@ static struct pci_ops meson_pci_ops = {
static bool meson_pcie_link_up(struct dw_pcie *pci)
{
struct meson_pcie *mp = to_meson_pcie(pci);
struct device *dev = pci->dev;
u32 speed_okay = 0;
u32 cnt = 0;
u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
u32 state12;
do {
state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
smlh_up = IS_SMLH_LINK_UP(state12);
rdlh_up = IS_RDLH_LINK_UP(state12);
ltssm_up = IS_LTSSM_UP(state12);
if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
speed_okay = 1;
if (smlh_up)
dev_dbg(dev, "smlh_link_up is on\n");
if (rdlh_up)
dev_dbg(dev, "rdlh_link_up is on\n");
if (ltssm_up)
dev_dbg(dev, "ltssm_up is on\n");
if (speed_okay)
dev_dbg(dev, "speed_okay\n");
if (smlh_up && rdlh_up && ltssm_up && speed_okay)
return true;
cnt++;
udelay(10);
} while (cnt < WAIT_LINKUP_TIMEOUT);
dev_err(dev, "error: wait linkup timeout\n");
return false;
state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
return IS_SMLH_LINK_UP(state12) && IS_RDLH_LINK_UP(state12);
}
static int meson_pcie_host_init(struct dw_pcie_rp *pp)

4
drivers/pci/controller/dwc/pcie-qcom.c
View File

@ -1047,7 +1047,6 @@ static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
pcie->parf + PARF_NO_SNOOP_OVERRIDE);
qcom_pcie_clear_aspm_l0s(pcie->pci);
qcom_pcie_clear_hpc(pcie->pci);
return 0;
@ -1316,6 +1315,8 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
goto err_disable_phy;
}
qcom_pcie_clear_aspm_l0s(pcie->pci);
qcom_ep_reset_deassert(pcie);
if (pcie->cfg->ops->config_sid) {
@ -1464,6 +1465,7 @@ static const struct qcom_pcie_cfg cfg_2_1_0 = {
static const struct qcom_pcie_cfg cfg_2_3_2 = {
.ops = &ops_2_3_2,
.no_l0s = true,
};
static const struct qcom_pcie_cfg cfg_2_3_3 = {