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mpfs pinctrl binding base

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The pinctrl binding patch for iomux0 mpfs adds a ref to itself to the
 syscon/mfd mss-top-sysreg binding, and therefore needs that file to
 exist.
 
 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaPez8QAKCRB4tDGHoIJi
 0tgYAP9KAOQ/zMPyEPViByRoyQx1xjuMR88xQ5LvfsYcV3M6jgD8C9H73smi7Q64
 j7l5ybzz/hhxLl2FrsgFK3PMSzvo5QI=
 =6Fxl
 -----END PGP SIGNATURE-----

Merge tag 'mpfs-pinctrl-binding-base' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into devel

mpfs pinctrl binding base

The pinctrl binding patch for iomux0 mpfs adds a ref to itself to the
syscon/mfd mss-top-sysreg binding, and therefore needs that file to
exist.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij 2025-10-24 11:07:47 +02:00
commit 5aed16228a
1 changed files with 47 additions and 0 deletions
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47
Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC Microprocessor Subsystem (MSS) sysreg register region
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
description:
An wide assortment of registers that control elements of the MSS on PolarFire
SoC, including pinmuxing, resets and clocks among others.
properties:
compatible:
items:
- const: microchip,mpfs-mss-top-sysreg
- const: syscon
reg:
maxItems: 1
'#reset-cells':
description:
The AHB/AXI peripherals on the PolarFire SoC have reset support, so
from CLK_ENVM to CLK_CFM. The reset consumer should specify the
desired peripheral via the clock ID in its "resets" phandle cell.
See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list
of PolarFire clock/reset IDs.
const: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@20002000 {
compatible = "microchip,mpfs-mss-top-sysreg", "syscon";
reg = <0x20002000 0x1000>;
#reset-cells = <1>;
};