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dt-bindings: Changes for v6.19-rc1

Browse Source 
Document various new IPs on older chips, as well as some existing
 developer kits that were missing compatible strings. Add power domain
 IDs on Tegra264 and wake-up support for the XUSB controller on Tegra234.
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Merge tag 'tegra-for-6.19-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

dt-bindings: Changes for v6.19-rc1

Document various new IPs on older chips, as well as some existing
developer kits that were missing compatible strings. Add power domain
IDs on Tegra264 and wake-up support for the XUSB controller on Tegra234.

* tag 'tegra-for-6.19-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: usb: Add wake-up support for Tegra234 XUSB host controller
  dt-bindings: devfreq: tegra30-actmon: Add Tegra124 fallback for Tegra210
  dt-bindings: display: tegra: Document Tegra20 and Tegra30 CSI
  dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114+
  dt-bindings: arm: tegra: Document Jetson Nano Devkits
  dt-bindings: power: Add power domain IDs for Tegra264

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-11-21 16:49:08 +01:00
commit 5d5b665e3e
9 changed files with 306 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/tegra.yaml
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@ -189,6 +189,11 @@ properties:
- nvidia,p2371-2180
- nvidia,p2571
- nvidia,p2894-0050-a08
- nvidia,p3450-0000
- const: nvidia,tegra210
- items:
- const: nvidia,p3541-0000
- const: nvidia,p3450-0000
- const: nvidia,tegra210
- description: Jetson TX2 Developer Kit
items:

13
Documentation/devicetree/bindings/devfreq/nvidia,tegra30-actmon.yaml
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@ -19,11 +19,14 @@ description: |
properties:
compatible:
enum:
- nvidia,tegra30-actmon
- nvidia,tegra114-actmon
- nvidia,tegra124-actmon
- nvidia,tegra210-actmon
oneOf:
- enum:
- nvidia,tegra30-actmon
- nvidia,tegra114-actmon
- nvidia,tegra124-actmon
- items:
- const: nvidia,tegra210-actmon
- const: nvidia,tegra124-actmon
reg:
maxItems: 1

68
Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Security co-processor
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
- Thierry Reding <thierry.reding@gmail.com>
description: Tegra Security co-processor, an embedded security processor used
mainly to manage the HDCP encryption and keys on the HDMI link.
properties:
compatible:
oneOf:
- enum:
- nvidia,tegra114-tsec
- nvidia,tegra124-tsec
- nvidia,tegra210-tsec
- items:
- const: nvidia,tegra132-tsec
- const: nvidia,tegra124-tsec
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
iommus:
maxItems: 1
operating-points-v2: true
power-domains:
maxItems: 1
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- resets
examples:
- |
#include <dt-bindings/clock/tegra114-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
tsec@54500000 {
compatible = "nvidia,tegra114-tsec";
reg = <0x54500000 0x00040000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
resets = <&tegra_car TEGRA114_CLK_TSEC>;
};

138
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml Normal file
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@ -0,0 +1,138 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra20 CSI controller
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
properties:
compatible:
enum:
- nvidia,tegra20-csi
- nvidia,tegra30-csi
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: module clock
- description: PAD A clock
- description: PAD B clock
clock-names:
items:
- const: csi
- const: csia-pad
- const: csib-pad
avdd-dsi-csi-supply:
description: DSI/CSI power supply. Must supply 1.2 V.
power-domains:
maxItems: 1
"#nvidia,mipi-calibrate-cells":
description:
The number of cells in a MIPI calibration specifier. Should be 1.
The single cell specifies an id of the pad that need to be
calibrated for a given device. Valid pad ids for receiver would be
0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B.
$ref: /schemas/types.yaml#/definitions/uint32
const: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^channel@[0-1]$":
type: object
description: channel 0 represents CSI-A and 1 represents CSI-B
additionalProperties: false
properties:
reg:
maximum: 1
nvidia,mipi-calibrate:
description: Should contain a phandle and a specifier specifying
which pad is used by this CSI channel and needs to be calibrated.
$ref: /schemas/types.yaml#/definitions/phandle-array
"#address-cells":
const: 1
"#size-cells":
const: 0
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: port receiving the video stream from the sensor
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: port sending the video stream to the VI
required:
- reg
- "#address-cells"
- "#size-cells"
- port@0
- port@1
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra20-csi
then:
properties:
clocks:
maxItems: 1
clock-names: false
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra30-csi
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
additionalProperties: false
required:
- compatible
- reg
- clocks
- power-domains
- "#address-cells"
- "#size-cells"
# see nvidia,tegra20-vi.yaml for an example

14
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
View File

@ -15,10 +15,16 @@ properties:
pattern: "^epp@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-epp
- nvidia,tegra30-epp
- nvidia,tegra114-epp
oneOf:
- enum:
- nvidia,tegra20-epp
- nvidia,tegra30-epp
- nvidia,tegra114-epp
- nvidia,tegra124-epp
- items:
- const: nvidia,tegra132-epp
- const: nvidia,tegra124-epp
reg:
maxItems: 1

15
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
View File

@ -12,10 +12,17 @@ maintainers:
properties:
compatible:
enum:
- nvidia,tegra20-isp
- nvidia,tegra30-isp
- nvidia,tegra210-isp
oneOf:
- enum:
- nvidia,tegra20-isp
- nvidia,tegra30-isp
- nvidia,tegra114-isp
- nvidia,tegra124-isp
- nvidia,tegra210-isp
- items:
- const: nvidia,tegra132-isp
- const: nvidia,tegra124-isp
reg:
maxItems: 1

18
Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
View File

@ -12,13 +12,21 @@ maintainers:
properties:
$nodename:
pattern: "^mpe@[0-9a-f]+$"
oneOf:
- pattern: "^mpe@[0-9a-f]+$"
- pattern: "^msenc@[0-9a-f]+$"
compatible:
enum:
- nvidia,tegra20-mpe
- nvidia,tegra30-mpe
- nvidia,tegra114-mpe
oneOf:
- enum:
- nvidia,tegra20-mpe
- nvidia,tegra30-mpe
- nvidia,tegra114-msenc
- nvidia,tegra124-msenc
- items:
- const: nvidia,tegra132-msenc
- const: nvidia,tegra124-msenc
reg:
maxItems: 1

31
Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml
View File

@ -32,9 +32,35 @@ properties:
- const: bar2
interrupts:
minItems: 2
items:
- description: xHCI host interrupt
- description: mailbox interrupt
- description: USB wake event 0
- description: USB wake event 1
- description: USB wake event 2
- description: USB wake event 3
- description: USB wake event 4
- description: USB wake event 5
- description: USB wake event 6
description: |
The first two interrupts are required for the USB host controller. The
remaining USB wake event interrupts are optional. Each USB wake event is
independent; it is not necessary to use all of these events on a
platform. The USB host controller can function even if no wake-up events
are defined. The USB wake event interrupts are handled by the Tegra PMC;
hence, the interrupt controller for these is the PMC and the interrupt
IDs correspond to the PMC wake event IDs. A complete list of wake event
IDs is provided below, and this information is also present in the Tegra
TRM document.
PMC wake-up 76 for USB3 port 0 wakeup
PMC wake-up 77 for USB3 port 1 wakeup
PMC wake-up 78 for USB3 port 2 and port 3 wakeup
PMC wake-up 79 for USB2 port 0 wakeup
PMC wake-up 80 for USB2 port 1 wakeup
PMC wake-up 81 for USB2 port 2 wakeup
PMC wake-up 82 for USB2 port 3 wakeup
clocks:
items:
@ -127,8 +153,9 @@ examples:
<0x03650000 0x10000>;
reg-names = "hcd", "fpci", "bar2";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
<&pmc 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
<&bpmp TEGRA234_CLK_XUSB_FALCON>,

24
include/dt-bindings/power/nvidia,tegra264-bpmp.h Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/* Copyright (c) 2022-2024, NVIDIA CORPORATION. All rights reserved. */
#ifndef DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H
#define DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H
#define TEGRA264_POWER_DOMAIN_DISP 1
#define TEGRA264_POWER_DOMAIN_AUD 2
/* reserved 3:9 */
#define TEGRA264_POWER_DOMAIN_XUSB_SS 10
#define TEGRA264_POWER_DOMAIN_XUSB_DEV 11
#define TEGRA264_POWER_DOMAIN_XUSB_HOST 12
#define TEGRA264_POWER_DOMAIN_MGBE0 13
#define TEGRA264_POWER_DOMAIN_MGBE1 14
#define TEGRA264_POWER_DOMAIN_MGBE2 15
#define TEGRA264_POWER_DOMAIN_MGBE3 16
#define TEGRA264_POWER_DOMAIN_VI 17
#define TEGRA264_POWER_DOMAIN_VIC 18
#define TEGRA264_POWER_DOMAIN_ISP0 19
#define TEGRA264_POWER_DOMAIN_ISP1 20
#define TEGRA264_POWER_DOMAIN_PVA0 21
#define TEGRA264_POWER_DOMAIN_GPU 22
#endif /* DT_BINDINGS_POWER_NVIDIA_TEGRA264_BPMP_H */