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Pin control fixes for the v6.18 series:

Browse Source 
- Fix register naming in the Mediatek mt8189 driver.
 
 - Select REGMAP_MMIO for the Realtek RTD driver.
 
 - Fix the number of items in groups in the Toshiba
   Visconti driver.
 
 - Fix a memory leak in the Cirrus CS42L43 driver.
 
 - Fix a deadlock (!) in Qualcomm pinmux configuration.
 
 - Fix use of uninitialized memory and list initialization
   in the S32CC pin controller.
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Merge tag 'pinctrl-v6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control fixes from Linus Walleij:

 - Fix register naming in the Mediatek mt8189 driver

 - Select REGMAP_MMIO for the Realtek RTD driver

 - Fix the number of items in groups in the Toshiba Visconti driver

 - Fix a memory leak in the Cirrus CS42L43 driver

 - Fix a deadlock (!) in Qualcomm pinmux configuration

 - Fix use of uninitialized memory and list initialization in the S32CC
   pin controller

* tag 'pinctrl-v6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  dt-bindings: pinctrl: xlnx,versal-pinctrl: Add missing unevaluatedProperties on '^conf' nodes
  pinctrl: s32cc: initialize gpio_pin_config::list after kmalloc()
  pinctrl: s32cc: fix uninitialized memory in s32_pinctrl_desc
  pinctrl: qcom: msm: Fix deadlock in pinmux configuration
  pinctrl: cirrus: Fix fwnode leak in cs42l43_pin_probe()
  dt-bindings: pinctrl: toshiba,visconti: Fix number of items in groups
  pinctrl: realtek: Select REGMAP_MMIO for RTD driver
  pinctrl: mediatek: mt8189: align register base names to dt-bindings ones
  pinctrl: mediatek: mt8196: align register base names to dt-bindings ones
This commit is contained in:
Linus Torvalds 2025-11-21 10:47:24 -08:00
commit 68d804c64a
8 changed files with 40 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml
View File

@ -50,18 +50,20 @@ patternProperties:
groups:
description:
Name of the pin group to use for the functions.
$ref: /schemas/types.yaml#/definitions/string
enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
uart0_grp, uart1_grp, uart2_grp, uart3_grp,
pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]
items:
enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
uart0_grp, uart1_grp, uart2_grp, uart3_grp,
pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]
minItems: 1
maxItems: 8
drive-strength:
enum: [2, 4, 6, 8, 16, 24, 32]

1
Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml
View File

@ -74,6 +74,7 @@ patternProperties:
'^conf':
type: object
unevaluatedProperties: false
description:
Pinctrl node's client devices use subnodes for pin configurations,
which in turn use the standard properties below.

21
drivers/pinctrl/cirrus/pinctrl-cs42l43.c
View File

@ -532,6 +532,11 @@ static int cs42l43_gpio_add_pin_ranges(struct gpio_chip *chip)
return ret;
}
static void cs42l43_fwnode_put(void *data)
{
fwnode_handle_put(data);
}
static int cs42l43_pin_probe(struct platform_device *pdev)
{
struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
@ -563,10 +568,20 @@ static int cs42l43_pin_probe(struct platform_device *pdev)
priv->gpio_chip.ngpio = CS42L43_NUM_GPIOS;
if (is_of_node(fwnode)) {
fwnode = fwnode_get_named_child_node(fwnode, "pinctrl");
struct fwnode_handle *child;
if (fwnode && !fwnode->dev)
fwnode->dev = priv->dev;
child = fwnode_get_named_child_node(fwnode, "pinctrl");
if (child) {
ret = devm_add_action_or_reset(&pdev->dev,
cs42l43_fwnode_put, child);
if (ret) {
fwnode_handle_put(child);
return ret;
}
if (!child->dev)
child->dev = priv->dev;
fwnode = child;
}
}
priv->gpio_chip.fwnode = fwnode;

4
drivers/pinctrl/mediatek/pinctrl-mt8189.c
View File

@ -1642,9 +1642,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {
};
static const char * const mt8189_pinctrl_register_base_names[] = {
"gpio_base", "iocfg_bm0_base", "iocfg_bm1_base", "iocfg_bm2_base", "iocfg_lm_base",
"iocfg_lt0_base", "iocfg_lt1_base", "iocfg_rb0_base", "iocfg_rb1_base",
"iocfg_rt_base"
"base", "lm", "rb0", "rb1", "bm0", "bm1", "bm2", "lt0", "lt1", "rt",
};
static const struct mtk_eint_hw mt8189_eint_hw = {

6
drivers/pinctrl/mediatek/pinctrl-mt8196.c
View File

@ -1801,10 +1801,8 @@ static const struct mtk_pin_reg_calc mt8196_reg_cals[PINCTRL_PIN_REG_MAX] = {
};
static const char * const mt8196_pinctrl_register_base_names[] = {
"iocfg0", "iocfg_rt", "iocfg_rm1", "iocfg_rm2",
"iocfg_rb", "iocfg_bm1", "iocfg_bm2", "iocfg_bm3",
"iocfg_lt", "iocfg_lm1", "iocfg_lm2", "iocfg_lb1",
"iocfg_lb2", "iocfg_tm1", "iocfg_tm2", "iocfg_tm3",
"base", "rt", "rm1", "rm2", "rb", "bm1", "bm2", "bm3",
"lt", "lm1", "lm2", "lb1", "lb2", "tm1", "tm2", "tm3",
};
static const struct mtk_eint_hw mt8196_eint_hw = {

3
drivers/pinctrl/nxp/pinctrl-s32cc.c
View File

@ -392,6 +392,7 @@ static int s32_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
gpio_pin->pin_id = offset;
gpio_pin->config = config;
INIT_LIST_HEAD(&gpio_pin->list);
spin_lock_irqsave(&ipctl->gpio_configs_lock, flags);
list_add(&gpio_pin->list, &ipctl->gpio_configs);
@ -951,7 +952,7 @@ int s32_pinctrl_probe(struct platform_device *pdev,
spin_lock_init(&ipctl->gpio_configs_lock);
s32_pinctrl_desc =
devm_kmalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL);
devm_kzalloc(&pdev->dev, sizeof(*s32_pinctrl_desc), GFP_KERNEL);
if (!s32_pinctrl_desc)
return -ENOMEM;

2
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -189,7 +189,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
*/
if (d && i != gpio_func &&
!test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
disable_irq(irq);
disable_irq_nosync(irq);
raw_spin_lock_irqsave(&pctrl->lock, flags);

1
drivers/pinctrl/realtek/Kconfig
View File

@ -6,6 +6,7 @@ config PINCTRL_RTD
default y
select PINMUX
select GENERIC_PINCONF
select REGMAP_MMIO
config PINCTRL_RTD1619B
tristate "Realtek DHC 1619B pin controller driver"