jsauer/torvalds-linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-01-12 01:20:14 +00:00
Code

i.MX arm64 device tree changes for 6.18:

Browse Source 
- New device trees: TQMa91xx/MBa91xxCA, Ultratronik Ultra-MACH SBC,
   SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK,
   EDM-G-IMX8M-PLUS SOM
 - A bunch of Kontron boards update from Annette Kobou and Frieder Schrempf,
   adding overlay for LTE extension board, fixing GPIO for panel regulator,
   removing unused regulators, fixing USB hub reset and USB port etc.
 - A number of s32g updates from Dan Carpenter and Daniel Lezcano, adding
   OCOTP, timers and watchdog support
 - An i.MX95 update from Frank Li to add msi-map for pci-ep device
 - A series from Joy Zou to add i.MX91 support
 - A series from Krzysztof Kozlowski to add default GIC address cells for
   LS and i.MX8 SoCs
 - A set of changes from Peng Fan to improve i.MX95 support with more devices
   enabled
 - A series from Shengjiu Wang to support more sample rates for wm8524 card
   on i.MX8M EVK boards
 - Other random updates and cleanups on various boards
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCgAdFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAmjIEKYACgkQUFdYWoew
 fM73nwf5AeVYl6EyXcPn4z0GxIru8Kp48aSEj0qbyj/CaEmfW01fAz7SE2aiytEW
 gBYUnGwpV6FRY8vKBXKawT4jLX3IOiu9ZGHi24tyd0QveTXcC/yryIhOaGF5Gooe
 t04puDBogkSq9io/cTe/aLujkyh59Zoe2x8OlN2o2Yl/SX1ozVX6LJLqyc+KaklB
 rHipWiH6EsoxrZnpHlv7vqoZgl6SuBd+qchWgDIESDalUdun5fvEOhCElrGoZcYQ
 Bdf1JGOugXFdBa+z/31bC2yjbYEBev2iGKwOrnZo5V3rX6sTWApw+31VgirYH/jE
 tLWRs2VqCbIFzDHJozYHxYgsq1+s+g==
 =HmPc
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIJIIACgkQmmx57+YA
 GNlzaA/9GOpQI/HicC6LeWCzzIF+cU4XCWUsdQsnezZszpoXk5tqEn4nSNVLRI/+
 D41bgg2CH0854yuGv56EnBjeFRcqJhs6tkFhI4DUlR1J4ApncyWlUboCSfftVW8l
 ZvDk2J/X1SNqxnMJvw3VFOfX4fI3+LxrM22zaRJ2Fta/w7S/LemEEM4+ho0+dY4J
 XBaY9o+pyAtLInkx5xasI3m55JKfnNFSJwoVWEuIoEie05QWBdJasxQafRsm06MQ
 xICJGpp2atZknCcOD3BG0db5+ZhiQL6pRg0OOiBmqHoViRAzDMia4WfbKNHmyhfa
 Tl+xR985oo3bL/SkHr5ctJ15FvO6+IEJ1N7Wp3MD/IsjeSctx/SS7+Tlnca3JxWC
 THCNjtmQaMhBh0RYD2ViIkiNqmEXLrdDSE4aP/WfL0ifIGes8Sb5n9LIB3c0mfbp
 JBbkxge82Mf+6bC5Rjx6XAZRToXaoPecCirPGY5IPcuI+FA/YveWWl4UodZ78uhj
 7xKw2pDGJiARed1UbBJK8pvg7cnf3leWPhWIuYuDn/HYJhpwewWP25539/Ari9HM
 jkMiGCGqde7IaCQwSlWfhwAPwNoByinOmBnj/JlAcQP46NdF9KCPNEgKvFsfTRdR
 mt8nhDSn1aFmfq5VqzBd1xz7nf/3ydFFGEpJP3jj+yLibIVqb40=
 =zi/z
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

i.MX arm64 device tree changes for 6.18:

- New device trees: TQMa91xx/MBa91xxCA, Ultratronik Ultra-MACH SBC,
  SolidRun i.MX8MP SoM, i.MX8ULP EVK9, TQMLS1012AL, i.MX91 11x11 EVK,
  EDM-G-IMX8M-PLUS SOM
- A bunch of Kontron boards update from Annette Kobou and Frieder Schrempf,
  adding overlay for LTE extension board, fixing GPIO for panel regulator,
  removing unused regulators, fixing USB hub reset and USB port etc.
- A number of s32g updates from Dan Carpenter and Daniel Lezcano, adding
  OCOTP, timers and watchdog support
- An i.MX95 update from Frank Li to add msi-map for pci-ep device
- A series from Joy Zou to add i.MX91 support
- A series from Krzysztof Kozlowski to add default GIC address cells for
  LS and i.MX8 SoCs
- A set of changes from Peng Fan to improve i.MX95 support with more devices
  enabled
- A series from Shengjiu Wang to support more sample rates for wm8524 card
  on i.MX8M EVK boards
- Other random updates and cleanups on various boards

* tag 'imx-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (75 commits)
  arm64: dts: s32g: Add device tree information for the OCOTP driver
  arm64: dts: add description for solidrun imx8mp hummingboard variants
  arm64: dts: imx8mm-phycore-som: optimize drive strengh
  arm64: dts: freescale: imx93-phycore-som: Remove "fsl,magic-packet"
  arm64: dts: freescale: imx93-phyboard-nash: Current sense via iio-hwmon
  arm64: dts: imx95: add standard PCI device compatible string to NETC Timer
  arm64: dts: freescale: add initial device tree for TQMa91xx/MBa91xxCA
  arm64: dts: imx93-11x11-evk: remove fec property eee-broken-1000t
  arm64: dts: freescale: add i.MX91 11x11 EVK basic support
  arm64: dts: imx91: add i.MX91 dtsi support
  arm64: dts: freescale: rename imx93.dtsi to imx91_93_common.dtsi and modify them
  arm64: dts: freescale: move aliases from imx93.dtsi to board dts
  arm64: dts: lx2160a-clearfog-itx: enable pcie nodes for x4 and x8 slots
  arm64: dts: lx2160a-cex7: add interrupts for rtc and ethernet phy
  arm64: dts: add description for solidrun imx8mp som and cubox-m
  arm64: dts: imx8: Use GIC_SPI for interrupt-map for readability
  arm64: dts: imx8qxp: Add default GIC address cells
  arm64: dts: imx8qm: Add default GIC address cells
  arm64: dts: imx8mq: Add default GIC address cells
  arm64: dts: imx8mp: Add default GIC address cells
  ...

Link: https://lore.kernel.org/r/20250915132535.253859-3-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-09-15 16:36:33 +02:00
commit 6c1c107bf5
84 changed files with 9439 additions and 1492 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -25864,6 +25864,7 @@ M: Goran Rađenović <goran.radni@gmail.com>
M: Börge Strümpfel <boerge.struempfel@gmail.com>
S: Maintained
F: arch/arm/boot/dts/st/stm32mp157c-ultra-fly-sbc.dts
F: arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
UNICODE SUBSYSTEM
M: Gabriel Krisman Bertazi <krisman@kernel.org>

14
arch/arm64/boot/dts/freescale/Makefile
View File

@ -5,6 +5,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb
@ -194,6 +196,7 @@ imx8mp-aristainetos3-helios-lvds-dtbs += imx8mp-aristainetos3-helios.dtb imx8mp-
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-helios-lvds.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-aristainetos3-proton2s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-cubox-m.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
@ -201,7 +204,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-edm-g-wb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-mate.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pro.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-hummingboard-ripple.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb
@ -237,6 +245,7 @@ imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17-dtbs += imx8mp-tx8p-ml81-modu
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-tx8p-ml81-moduline-display-106-av123z7m-n17.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-ultra-mach-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb
@ -332,7 +341,10 @@ dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
@ -371,8 +383,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-pcie0-ep.dtb imx95-19x19-evk-pcie1-ep.
dtb-$(CONFIG_ARCH_MXC) += imx95-libra-rdk-fpsc.dtb
imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo
imx8mm-kontron-bl-lte-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-bl-lte.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-lte.dtb
imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo

23
arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al-emmc.dts Normal file
View File

@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Matthias Schiffer
* Author: Max Merchel
*/
#include "fsl-ls1012a-tqmls1012al-mbls1012al.dts"
&esdhc0 {
vqmmc-supply = <&reg_1v8>;
/delete-property/ no-mmc;
/delete-property/ sd-uhs-sdr12;
/delete-property/ sd-uhs-sdr25;
/delete-property/ sd-uhs-sdr50;
/delete-property/ sd-uhs-sdr104;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
no-sd;
voltage-ranges = <1800 1800>;
non-removable;
};

366
arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al-mbls1012al.dts Normal file
View File

@ -0,0 +1,366 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Matthias Schiffer
* Author: Max Merchel
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "fsl-ls1012a-tqmls1012al.dtsi"
/ {
model = "TQ-Systems TQMLS1012AL on MBLS1012AL";
compatible = "tq,ls1012a-tqmls1012al-mbls1012al", "tq,ls1012a-tqmls1012al", "fsl,ls1012a";
chassis-type = "embedded";
aliases {
/* use MAC from U-Boot environment */
/* TODO: PFE */
ethernet2 = &swport0;
ethernet3 = &swport1;
ethernet4 = &swport2;
ethernet5 = &swport3;
serial0 = &duart0;
spi0 = &qspi;
};
chosen {
stdout-path = &duart0;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
switch-1 {
label = "S2";
linux,code = <BTN_0>;
gpios = <&gpio_exp_3p3v 13 GPIO_ACTIVE_LOW>;
};
switch-2 {
label = "X15";
linux,code = <BTN_1>;
gpios = <&gpio_exp_1p8v 5 GPIO_ACTIVE_LOW>;
};
switch-3 {
label = "X16";
linux,code = <BTN_2>;
gpios = <&gpio_exp_1p8v 4 GPIO_ACTIVE_LOW>;
};
};
gpio-leds {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&gpio_exp_3p3v 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio_exp_3p3v 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "default-on";
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
/* 64 MiB */
size = <0 0x04000000>;
/* 512 - 128 MiB, our minimum RAM config will be 512 MiB */
alloc-ranges = <0 0x80000000 0 0x98000000>;
linux,cma-default;
};
};
reg_1v5: regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "V_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
reg_1p5v_pcie: regulator-1p5v-pcie {
compatible = "regulator-fixed";
regulator-name = "V_1V5_PCIE";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio_exp_1p8v 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_1v5>;
};
reg_1p5v_wlan: regulator-1p5v-wlan {
compatible = "regulator-fixed";
regulator-name = "V_1V5_WLAN";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio_exp_1p8v 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_1v5>;
};
reg_1v8: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "V_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_3v3: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_3v3_pcie: regulator-3v3-pcie {
compatible = "regulator-fixed";
regulator-name = "V_3V3_PCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio_exp_3p3v 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_3v3>;
};
reg_3v3_wlan: regulator-3v3-wlan {
compatible = "regulator-fixed";
regulator-name = "V_3V3_WLAN";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&gpio_exp_3p3v 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_3v3>;
};
};
&duart0 {
status = "okay";
};
&esdhc0 {
vmmc-supply = <&reg_3v3>;
no-mmc;
no-sdio;
disable-wp;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&i2c0 {
gpio_exp_3p3v: gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
interrupt-parent = <&gpio0>;
interrupts = <24 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-line-names = "", "", "GPIO_3V3_3", "",
"", "", "", "",
"", "GPIO_3V3_1", "GPIO_3V3_2", "",
"", "", "", "";
wlan-disable-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "WLAN_DISABLE#";
};
pcie-rst-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE_RST#";
};
wlan-rst-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "WLAN_RST#";
};
pcie-dis-hog {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE_DIS#";
};
pcie-wake-hog {
gpio-hog;
gpios = <12 GPIO_ACTIVE_HIGH>;
input;
line-name = "PCIE_WAKE#";
};
};
lm75_48: temperature-sensor@48 {
compatible = "national,lm75a";
reg = <0x48>;
vs-supply = <&reg_3v3>;
};
switch@5f {
compatible = "microchip,ksz9897";
reg = <0x5f>;
reset-gpios = <&gpio_exp_3p3v 7 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
swport0: port@0 {
reg = <0>;
label = "swp0";
phy-mode = "internal";
};
swport1: port@1 {
reg = <1>;
label = "swp1";
phy-mode = "internal";
};
swport2: port@2 {
reg = <2>;
label = "swp2";
phy-mode = "internal";
};
swport3: port@3 {
reg = <3>;
label = "swp3";
phy-mode = "internal";
};
port@6 {
reg = <6>;
label = "cpu";
/* TODO: PFE */
phy-mode = "rgmii-id";
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
gpio_exp_1p8v: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_1v8>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-line-names = "PCIE_CLK_PD#", "PMIC_INT#", "ETH_SW_INT#", "",
"", "", "", "",
"", "GPIO_3V3_1", "GPIO_3V3_2", "",
"", "", "", "";
/* do not change PCIE_CLK_PD */
pcie-clk-pd-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE_CLK_PD#";
};
pmic-int-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
input;
line-name = "PMIC_INT#";
};
eth-sw-int-hog {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
input;
line-name = "ETH_SW_INT#";
};
eth-link-pwrdwn-hog {
gpio-hog;
gpios = <3 GPIO_ACTIVE_HIGH>;
input;
line-name = "ETH_LINK_PWRDWN#";
};
};
};
&pcie1 {
status = "okay";
};
/* TODO: PFE */
&sata {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
hub_2_0: hub@1 {
compatible = "usb451,8142";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_vcc_3v3>;
};
hub_3_0: hub@2 {
compatible = "usb451,8140";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio_exp_3p3v 6 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_vcc_3v3>;
};
};

81
arch/arm64/boot/dts/freescale/fsl-ls1012a-tqmls1012al.dtsi Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2018-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Matthias Schiffer
* Author: Max Merchel
*/
#include "fsl-ls1012a.dtsi"
/ {
compatible = "tq,ls1012a-tqmls1012al", "fsl,ls1012a";
memory@80000000 {
device_type = "memory";
/* our minimum RAM config will be 512 MiB */
reg = <0x00000000 0x80000000 0 0x20000000>;
};
reg_vcc_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vcc_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&i2c0 {
status = "okay";
jc42_19: temperature-sensor@19 {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x19>;
};
m24c64_50: eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&reg_vcc_3v3>;
};
m24c02_51: eeprom@51 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
read-only;
vcc-supply = <&reg_vcc_3v3>;
};
rtc1: rtc@68 {
compatible = "dallas,ds1339";
reg = <0x68>;
};
};
&qspi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <39000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
vcc-supply = <&reg_vcc_1v8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};

1
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
View File

@ -87,6 +87,7 @@
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1401000 0 0x1000>, /* GICD */

1
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View File

@ -289,6 +289,7 @@
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1401000 0 0x1000>, /* GICD */

1
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
View File

@ -260,6 +260,7 @@
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1410000 0 0x10000>, /* GICD */

2
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
View File

@ -41,6 +41,7 @@
rgmii_phy1: ethernet-phy@1 {
reg = <1>;
qca,smarteee-tw-us-1g = <24>;
interrupts-extended = <&gpio2 4 IRQ_TYPE_EDGE_FALLING>;
};
};
@ -156,6 +157,7 @@
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
interrupts-extended = <&gpio2 8 IRQ_TYPE_LEVEL_LOW>;
};
};

8
arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
View File

@ -96,6 +96,14 @@
status = "okay";
};
&pcie3 {
status = "okay";
};
&pcie5 {
status = "okay";
};
&pcs_mdio7 {
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@ -256,7 +256,7 @@
};
&asrc0 {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
};
&adc0 {

8
arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
View File

@ -68,10 +68,10 @@ hsio_subsys: bus@5f000000 {
clock-names = "dbi", "mstr", "slv";
bus-range = <0x00 0xff>;
device_type = "pci";
interrupt-map = <0 0 0 1 &gic 0 105 4>,
<0 0 0 2 &gic 0 106 4>,
<0 0 0 3 &gic 0 107 4>,
<0 0 0 4 &gic 0 108 4>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0x7>;
num-lanes = <1>;
num-viewport = <4>;

2
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@ -652,7 +652,7 @@
status = "okay";
};
&pcie0_ep{
&pcie0_ep {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;

2
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
View File

@ -5,6 +5,8 @@
/delete-node/ &enet1_lpcg;
/delete-node/ &fec2;
/delete-node/ &usbotg3;
/delete-node/ &usb3_phy;
/ {
conn_enet0_root_clk: clock-conn-enet0-root {

8
arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi
View File

@ -42,10 +42,10 @@
#interrupt-cells = <1>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map = <0 0 0 1 &gic 0 47 4>,
<0 0 0 2 &gic 0 48 4>,
<0 0 0 3 &gic 0 49 4>,
<0 0 0 4 &gic 0 50 4>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0x7>;
};

1
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@ -92,6 +92,7 @@
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
View File

@ -333,7 +333,7 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4

17
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@ -147,6 +147,7 @@
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Line", "Left Line Out Jack",
"Line", "Right Line Out Jack";
@ -158,11 +159,11 @@
sound-dai = <&sai3>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
system-clock-direction-out;
};
simple-audio-card,codec {
sound-dai = <&wm8524>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
};
};
@ -570,9 +571,17 @@
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>,
<&clk IMX8MM_AUDIO_PLL2>,
<&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <393216000>, <361267200>, <24576000>;
fsl,sai-mclk-direction-output;
clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};

186
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-lte.dtso Normal file
View File

@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2025 Kontron Electronics GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
#include "imx8mm-pinfunc.h"
&{/} {
compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
key-user {
label = "user";
linux,code = <BTN_0>;
gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led_lte>;
lte-led1-b {
label = "lte-led1-blue";
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
};
lte-led1-g {
label = "lte-led1-green";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
};
lte-led1-r {
label = "lte-led1-red";
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
};
lte-led2-b {
label = "lte-led2-blue";
color = <LED_COLOR_ID_BLUE>;
gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
};
lte-led2-g {
label = "lte-led2-green";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
};
lte-led2-r {
label = "lte-led2-red";
color = <LED_COLOR_ID_RED>;
gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
};
};
};
&ecspi3 {
status = "disabled";
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
tpm@2e {
compatible = "infineon,slb9673", "tcg,tpm-tis-i2c";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm>;
reg = <0x2e>;
interrupt-parent = <&gpio3>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio3>;
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "VDD_IO_REF", "TPM_PIRQ#",
"TPM_RESET# ", "", "", "",
"", "LTE_LED1_B", "LTE_LED1_G", "",
"";
vdd-io-ref-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
line-name = "VDD_IO_REF";
output-high;
};
tpm-reset-hog {
gpio-hog;
gpios = <12 GPIO_ACTIVE_LOW>;
line-name = "TPM_RESET#";
output-low;
};
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>;
gpio-line-names = "", "", "LTE_RESET", "",
"", "", "", "",
"", "", "", "LTE_PWRKEY",
"", "", "", "",
"", "", "", "",
"LTE_PWR_EN";
};
&gpio5 {
gpio-line-names = "", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "LTE_LED2_G", "LTE_LED1_R",
"LTE_LED2_R", "LTE_LED2_B";
};
&iomuxc {
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* VDD_IO_REF */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x19 /* LTE_RESET */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x19 /* LTE_PWRKEY */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x19 /* LTE_PWR_EN */
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x19 /* Pushbutton */
>;
};
pinctrl_gpio_led_lte: gpioledltegrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* LTE_LED1_B */
MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* LTE_LED1_G */
MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23 0x19 /* LTE_LED1_R */
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* LTE_LED2_B */
MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22 0x19 /* LTE_LED2_G */
MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24 0x19 /* LTE_LED2_R */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */
>;
};
pinctrl_tpm: tpmgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* TPM_PIRQ# */
MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12 0x39 /* TPM_RESET# */
>;
};
};

8
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts
View File

@ -48,14 +48,6 @@
pwms = <&pwm2 0 5000 0>;
};
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-name = "rst-usb-eth2";
};
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-always-on;

12
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
View File

@ -268,8 +268,16 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
/*
* During bootup the CTS needs to stay LOW, which is only possible if this
* pin is controlled by a GPIO. The UART IP always sets CTS to HIGH if not
* running. So using 'uart-has-rtscts' is not a good choice here! There are
* workarounds for this, but they introduce unnecessary complexity and are
* therefore avoided here. For more information about this see:
* https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=79d0224f6bf296d04cd843cfc49921b19c97bb09
*/
rts-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
};
@ -439,7 +447,7 @@
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
>;
};

13
arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso
View File

@ -107,7 +107,7 @@
#size-cells = <0>;
status = "okay";
touchscreen@5d {
gt911: touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
@ -117,6 +117,17 @@
reset-gpios = <&gpio3 23 0>;
irq-gpios = <&gpio3 22 0>;
};
st1633: touchscreen@55 {
compatible = "sitronix,st1633";
reg = <0x55>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupts = <22 8>;
interrupt-parent = <&gpio3>;
gpios = <&gpio3 22 0>;
status = "disabled";
};
};
&lvds {

50
arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi
View File

@ -30,29 +30,6 @@
stdout-path = &uart3;
};
reg_vdd_carrier: regulator-vdd-carrier {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
regulator-name = "VDD_CARRIER";
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
regulator-state-disk {
regulator-off-in-suspend;
};
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -61,7 +38,7 @@
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "VBUS_USB1";
regulator-name = "VBUS_USB_A";
};
reg_usb2_vbus: regulator-usb2-vbus {
@ -72,7 +49,7 @@
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "VBUS_USB2";
regulator-name = "VBUS_USB_B";
};
reg_usdhc2_vcc: regulator-usdhc2-vcc {
@ -96,6 +73,29 @@
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SDIO_B";
};
reg_vdd_carrier: regulator-vdd-carrier {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
regulator-name = "VDD_CARRIER";
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
regulator-state-disk {
regulator-off-in-suspend;
};
};
};
&A53_0 {

2
arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-peb-av-10.dtso
View File

@ -20,7 +20,7 @@
pwms = <&pwm4 0 50000 0>;
power-supply = <&reg_vdd_3v3_s>;
enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
brightness-levels= <0 4 8 16 32 64 128 255>;
brightness-levels = <0 4 8 16 32 64 128 255>;
};
panel {

8
arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi
View File

@ -340,10 +340,10 @@
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x12
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x12
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x12
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x12
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10
>;
};

1
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -1467,6 +1467,7 @@
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
<0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

5
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@ -387,6 +387,11 @@
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
<&clk IMX8MN_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3-proton2s.dts
View File

@ -36,7 +36,7 @@
max-speed = <100>;
};
&ecspi1{
&ecspi1 {
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
};

6
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
View File

@ -167,7 +167,7 @@
<&clk IMX8MP_VIDEO_PLL1>;
};
&ecspi1{
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs2>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW &gpio1 6 GPIO_ACTIVE_LOW>;
@ -565,7 +565,7 @@
status = "disabled";
};
&pcie{
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 20 GPIO_ACTIVE_LOW>;
@ -574,7 +574,7 @@
status = "okay";
};
&pcie_phy{
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
clocks = <&pcie0_refclk>;
clock-names = "ref";

223
arch/arm64/boot/dts/freescale/imx8mp-cubox-m.dts Normal file
View File

@ -0,0 +1,223 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mp-sr-som.dtsi"
/ {
model = "SolidRun i.MX8MP CuBox-M";
compatible = "solidrun,imx8mp-cubox-m",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
/delete-property/ ethernet1;
rtc0 = &carrier_rtc;
rtc1 = &snvs_rtc;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&ir_pins>;
linux,autosuspend-period = <125>;
wakeup-source;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
status {
label = "status";
color = <LED_COLOR_ID_RED>;
gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
function = LED_FUNCTION_HEARTBEAT;
};
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
vbus: regulator-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&vbus_pins>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vmmc: regulator-mmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&vmmc_pins>;
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
startup-delay-us = <250>;
};
};
&aud2htx {
status = "okay";
};
&fec {
/* this board does not use second phy / ethernet on SoM */
status = "disabled";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
status = "okay";
};
&hdmi_tx_phy {
status = "okay";
};
&i2c3 {
carrier_rtc: rtc@32 {
compatible = "epson,rx8130";
reg = <0x32>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
hdmi_pins: pinctrl-hdmi-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
>;
};
ir_pins: pinctrl-ir-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x4f
>;
};
led_pins: pinctrl-led-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x0
>;
};
usdhc2_pins: pinctrl-usdhc2-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
vbus_pins: pinctrl-vbus-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x100
>;
};
vmmc_pins: pinctrl-vmmc-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0
>;
};
};
&lcdif3 {
status = "okay";
};
&usb3_phy0 {
fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
vbus-supply = <&vbus>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_phy1 {
fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
vbus-supply = <&vbus>;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
};
&usb_dwc3_1 {
dr_mode = "host";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&usdhc2_pins>;
pinctrl-1 = <&usdhc2_100mhz_pins>;
pinctrl-2 = <&usdhc2_200mhz_pins>;
vmmc-supply = <&vmmc>;
bus-width = <4>;
cap-power-off-card;
full-pwr-cycle;
status = "okay";
};

359
arch/arm64/boot/dts/freescale/imx8mp-edm-g-wb.dts Normal file
View File

@ -0,0 +1,359 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 TechNexion Ltd.
*
* Author: Ray Chang <ray.chang@technexion.com>
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-edm-g.dtsi"
/ {
compatible = "technexion,edm-g-imx8mp-wb", "technexion,edm-g-imx8mp", "fsl,imx8mp";
model = "TechNexion EDM-G-IMX8MP SOM on WB-EDM-G";
connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
hdmi-connector {
compatible = "hdmi-connector";
label = "HDMI OUT";
type = "a";
port {
hdmi_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
leds {
compatible = "gpio-leds";
led {
default-state = "on";
gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
label = "gpio-led";
};
};
pcie0_refclk: clock-pcie-ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_pwr_3v3: regulator-pwr-3v3 {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "pwr-3v3";
};
reg_pwr_5v: regulator-pwr-5v {
compatible = "regulator-fixed";
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "pwr-5v";
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
model = "audio-hdmi";
};
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
audio-asrc = <&easrc>;
audio-codec = <&wm8960>;
audio-cpu = <&sai3>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
model = "wm8960-audio";
};
};
&aud2htx {
status = "okay";
};
&easrc {
fsl,asrc-rate = <48000>;
status = "okay";
};
&flexcan1 {
status = "okay";
};
&gpio1 {
gpio-line-names =
"", "", "", "", "", "", "DSI_RST", "",
"", "", "", "", "", "PCIE_CLKREQ_N", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
pinctrl-0 = <&pinctrl_gpio1>;
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "", "GPIO_P249", "GPIO_P251",
"", "GPIO_P255", "", "", "", "", "", "",
"DSI_BL_EN", "DSI_VDDEN", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
pinctrl-0 = <&pinctrl_gpio4>;
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-0 = <&pinctrl_hdmi>;
pinctrl-names = "default";
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
status = "okay";
wm8960: audio-codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
clock-names = "mclk";
#sound-dai-cells = <0>;
AVDD-supply = <&reg_pwr_3v3>;
DBVDD-supply = <&reg_pwr_3v3>;
DCVDD-supply = <&reg_pwr_3v3>;
SPKVDD1-supply = <&reg_pwr_5v>;
SPKVDD2-supply = <&reg_pwr_5v>;
wlf,gpio-cfg = <1 2>;
wlf,hp-cfg = <2 2 3>;
wlf,shared-lrclk;
};
expander1: gpio@21 {
compatible = "nxp,pca9555";
reg = <0x21>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "EXPOSURE_TRIG_IN1", "FLASH_OUT1",
"INFO_TRIG_IN1", "CAM_SHUTTER1", "XVS1",
"PWR1_TIME0", "PWR1_TIME1", "PWR1_TIME2",
"EXPOSURE_TRIG_IN2", "FLASH_OUT2",
"INFO_TRIG_IN2", "CAM_SHUTTER2", "XVS2",
"PWR2_TIME0", "PWR2_TIME1", "PWR2_TIME2";
};
expander2: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio4>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
gpio-line-names = "M2_DISABLE_N", "LED_EN", "", "",
"", "", "", "USB_OTG_OC",
"EXT_GPIO8", "EXT_GPIO9", "", "",
"", "CSI1_PDB", "CSI2_PDB", "PD_FAULT";
pinctrl-0 = <&pinctrl_expander2_irq>;
pinctrl-names = "default";
};
usb_typec: usb-typec@67 {
compatible = "ti,hd3ss3220";
reg = <0x67>;
interrupt-parent = <&gpio4>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_hd3ss3220_irq>;
pinctrl-names = "default";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hd3ss3220_in_ep: endpoint {
remote-endpoint = <&ss_ep>;
};
};
port@1 {
reg = <1>;
hd3ss3220_out_ep: endpoint {
remote-endpoint = <&usb3_role_switch>;
};
};
};
};
};
&i2c_0 {
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
};
&lcdif3 {
status = "okay";
};
&pcie {
status = "okay";
};
&pcie_phy {
clocks = <&pcie0_refclk>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usb_dwc3_0 {
/* dual role is implemented but not a full featured OTG */
adp-disable;
dr_mode = "otg";
hnp-disable;
role-switch-default-mode = "peripheral";
srp-disable;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
usb3_hs_ep: endpoint {
remote-endpoint = <&hs_ep>;
};
};
port@1 {
reg = <1>;
usb3_role_switch: endpoint {
remote-endpoint = <&hd3ss3220_out_ep>;
};
};
};
};
&usb_dwc3_1 {
dr_mode = "host";
};
&iomuxc {
pinctrl_expander2_irq: expander2-irqgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x140 /* GPIO_P247 */
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x16 /* DSI_RST */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x16 /* GPIO_P249 */
MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x16 /* GPIO_P251 */
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16 /* GPIO_P255 */
MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x16 /* DSI_BL_EN */
MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x16 /* DSI_VDDEN */
>;
};
pinctrl_hd3ss3220_irq: hd3ss3220-irqgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x41 /* GPIO_P253 */
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
>;
};
};

786
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi Normal file
View File

@ -0,0 +1,786 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 TechNexion Ltd.
*
* Author: Ray Chang <ray.chang@technexion.com>
*/
#include "imx8mp.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
i2c_0: i2c {
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c_brd_conf>;
pinctrl-names = "default";
scl-gpios = <&gpio4 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio4 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
};
memory@40000000 {
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
device_type = "memory";
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
startup-delay-us = <100>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
rfkill {
compatible = "rfkill-gpio";
name = "rfkill";
pinctrl-0 = <&pinctrl_bt_ctrl>;
pinctrl-names = "default";
radio-type = "bluetooth";
shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
wl_reg_on: regulator-wl-reg-on {
compatible = "regulator-fixed";
off-on-delay-us = <20000>;
pinctrl-0 = <&pinctrl_wifi_ctrl>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "WL_REG_ON";
startup-delay-us = <100>;
gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&reg_arm>;
};
&A53_1 {
cpu-supply = <&reg_arm>;
};
&A53_2 {
cpu-supply = <&reg_arm>;
};
&A53_3 {
cpu-supply = <&reg_arm>;
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
num-cs = <1>;
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
pinctrl-names = "default";
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-names = "default";
snps,force_thresh_dma_mode;
snps,mtl-rx-config = <&mtl_rx_setup>;
snps,mtl-tx-config = <&mtl_tx_setup>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
reset-assert-us = <35000>;
reset-deassert-us = <75000>;
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
realtek,clkout-disable;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
queue0 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <0>;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <1>;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <2>;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <3>;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,map-to-dma-channel = <4>;
snps,priority = <0xf0>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
};
&flexcan1 {
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default";
};
&flexcan2 {
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-names = "default";
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
regulators {
BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <720000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
reg_arm: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1025000>;
regulator-min-microvolt = <720000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3600000>;
regulator-min-microvolt = <3000000>;
regulator-name = "BUCK4";
};
reg_buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "BUCK5";
};
BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1155000>;
regulator-min-microvolt = <1045000>;
regulator-name = "BUCK6";
};
LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "LDO1";
};
LDO3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1890000>;
regulator-min-microvolt = <1710000>;
regulator-name = "LDO3";
};
LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
};
&i2c2 {
/* I2C_B on EDMG */
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-names = "default";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-names = "default";
};
&i2c4 {
/* I2C_A on EDMG */
clock-frequency = <100000>;
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-names = "default";
};
&i2c5 {
/* I2C_C on EDMG */
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-names = "default";
};
&pcie {
pinctrl-0 = <&pinctrl_pcie>;
pinctrl-names = "default";
reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
&pwm1 {
pinctrl-0 = <&pinctrl_pwm1>;
pinctrl-names = "default";
status = "okay";
};
&pwm2 {
pinctrl-0 = <&pinctrl_pwm2>;
pinctrl-names = "default";
status = "okay";
};
&pwm3 {
pinctrl-0 = <&pinctrl_pwm3>;
pinctrl-names = "default";
status = "okay";
};
&pwm4 {
pinctrl-0 = <&pinctrl_pwm4>;
pinctrl-names = "default";
status = "okay";
};
&sai2 {
/* AUD_B on EDMG */
assigned-clocks = <&clk IMX8MP_CLK_SAI2>;
assigned-clock-rates = <12288000>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
pinctrl-0 = <&pinctrl_sai2>;
pinctrl-names = "default";
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai3 {
/* AUD_A on EDMG */
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-rates = <12288000>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
pinctrl-0 = <&pinctrl_sai3>;
pinctrl-names = "default";
fsl,sai-mclk-direction-output;
status = "okay";
};
&uart1 {
/* BT */
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&uart2 {
/* UART_A on EDMG, console */
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
status = "okay";
};
&uart3 {
/* UART_C on EDMG */
assigned-clocks = <&clk IMX8MP_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-0 = <&pinctrl_uart3>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&uart4 {
/* UART_B on EDMG */
assigned-clocks = <&clk IMX8MP_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
pinctrl-0 = <&pinctrl_uart4>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&usdhc1 {
/* WIFI SDIO */
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
assigned-clock-rates = <200000000>;
bus-width = <4>;
keep-power-in-suspend;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&wl_reg_on>;
status = "okay";
};
&usdhc2 {
/* SD card on baseboard */
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
bus-width = <4>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
/* eMMC on SOM */
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&wdog1 {
pinctrl-0 = <&pinctrl_wdog>;
pinctrl-names = "default";
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_hog>;
pinctrl-names = "default";
pinctrl_bt_ctrl: bt-ctrlgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x41 /* BT_REG_ON */
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x41 /* BT_WAKE_HOST */
>;
};
pinctrl_ecspi1_cs: ecspi1csgrp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40000
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x23
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001a3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001a3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001a3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001a3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001a3
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001a3
>;
};
pinctrl_i2c_brd_conf: i2cbrdconfgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c3 /* BRD_CONF_SCL, bitbang */
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c3 /* BRD_CONF_SDA, bitbang */
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x41 /* PCIE CLKREQ */
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x41 /* PCIE WAKE */
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x140
MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x140
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140
MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140
MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140
MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x140
MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x140
MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
pinctrl_wifi_ctrl: wifi-ctrlgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x41 /* WL_REG_ON */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x41 /* WL_WAKE_HOST */
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -309,7 +309,7 @@
};
&easrc {
fsl,asrc-rate = <48000>;
fsl,asrc-rate = <48000>;
status = "okay";
};

31
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-mate.dts Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include "imx8mp-sr-som.dtsi"
#include "imx8mp-hummingboard-pulse-common.dtsi"
#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
/ {
model = "SolidRun i.MX8MP HummingBoard Mate";
compatible = "solidrun,imx8mp-hummingboard-mate",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
/delete-property/ ethernet1;
};
};
&fec {
/* this board does not use second phy / ethernet on SoM */
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>;
};

76
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pro.dts Normal file
View File

@ -0,0 +1,76 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-sr-som.dtsi"
#include "imx8mp-hummingboard-pulse-codec.dtsi"
#include "imx8mp-hummingboard-pulse-common.dtsi"
#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
#include "imx8mp-hummingboard-pulse-m2con.dtsi"
#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
/ {
model = "SolidRun i.MX8MP HummingBoard Pro";
compatible = "solidrun,imx8mp-hummingboard-pro",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
<&m2_wwan_wake_pins>;
};
&pcie {
pinctrl-0 = <&m2_reset_pins>;
pinctrl-names = "default";
reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};
&phy0 {
leds {
/* ADIN1300 LED_0 pin */
led@0 {
reg = <0>;
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
/delete-node/ led@1;
};
};
&phy1 {
leds {
#address-cells = <1>;
#size-cells = <0>;
/* ADIN1300 LED_0 pin */
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};

59
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-codec.dtsi Normal file
View File

@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/ {
sound-wm8904 {
compatible = "fsl,imx-audio-wm8904";
model = "audio-wm8904";
audio-cpu = <&sai3>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"AMIC", "MICBIAS",
"IN2R", "AMIC";
};
};
&i2c2 {
codec: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
clock-names = "mclk";
AVDD-supply = <&v_1_8>;
CPVDD-supply = <&v_1_8>;
DBVDD-supply = <&v_3_3>;
DCVDD-supply = <&v_1_8>;
MICVDD-supply = <&v_3_3>;
};
};
&iomuxc {
sai3_pins: pinctrl-sai3-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
>;
};
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&sai3_pins>;
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
<&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
<&clk IMX8MP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
fsl,sai-mclk-direction-output;
status = "okay";
};

384
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-common.dtsi Normal file
View File

@ -0,0 +1,384 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
#include <dt-bindings/leds/common.h>
/ {
aliases {
rtc0 = &carrier_rtc;
rtc1 = &snvs_rtc;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
led-0 {
label = "D30";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-1 {
label = "D31";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-2 {
label = "D32";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-3 {
label = "D33";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led-4 {
label = "D34";
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
default-state = "on";
};
};
rfkill-mpcie-wifi {
/*
* The mpcie connector only has USB,
* therefore this rfkill is for cellular radios only.
*/
compatible = "rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&mpcie_rfkill_pins>;
label = "mpcie radio";
radio-type = "wwan";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
};
vmmc: regulator-mmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&vmmc_pins>;
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
startup-delay-us = <250>;
};
vbus1: regulator-vbus-1 {
compatible = "regulator-fixed";
regulator-name = "vbus1";
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&vbus1_pins>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vbus2: regulator-vbus-2 {
compatible = "regulator-fixed";
regulator-name = "vbus2";
gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&vbus2_pins>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
v_1_2: regulator-1-2 {
compatible = "regulator-fixed";
regulator-name = "1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vmpcie {
/* supplies mpcie and m2 connectors */
compatible = "regulator-fixed";
regulator-name = "vmpcie";
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&vmpcie_pins>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
/* mikrobus spi */
&ecspi2 {
num-cs = <1>;
pinctrl-names = "default";
pinctrl-0 = <&mikro_spi_pins>;
status = "okay";
};
&gpio1 {
pinctrl-0 = <&mpcie_reset_pins>;
pinctrl-names = "default";
mpcie-reset-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
output-low;
line-name = "mpcie-reset";
};
};
&i2c3 {
carrier_eeprom: eeprom@57{
compatible = "st,24c02", "atmel,24c02";
reg = <0x57>;
pagesize = <16>;
};
carrier_rtc: rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;
abracon,tc-diode = "schottky";
abracon,tc-resistor = <3>;
};
};
&iomuxc {
csi_pins: pinctrl-csi-grp {
fsl,pins = <
/* Pin 24: STROBE */
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0
>;
};
led_pins: pinctrl-led-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x0
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x0
MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x0
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0
MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x0
>;
};
mikro_int_pins: pinctrl-mikro-int-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x0
>;
};
mikro_pwm_pins: pinctrl-mikro-pwm-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x0
>;
};
mikro_rst_pins: pinctrl-mikro-rst-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x0
>;
};
mikro_spi_pins: pinctrl-mikro-spi-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x40000
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
>;
};
mikro_uart_pins: pinctrl-mikro-uart-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
>;
};
mpcie_reset_pins: pinctrl-mpcie-reset-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x0
>;
};
mpcie_rfkill_pins: pinctrl-pcie-rfkill-grp {
fsl,pins = <
/* weak i/o, open drain */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x20
>;
};
usb_hub_pins: pinctrl-usb-hub-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x0
>;
};
usdhc2_pins: pinctrl-usdhc2-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
usdhc2_100mhz_pins: pinctrl-usdhc2-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
usdhc2_200mhz_pins: pinctrl-usdhc2-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x140
MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x140
>;
};
vbus1_pins: pinctrl-vbus-1-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x20
>;
};
vbus2_pins: pinctrl-vbus-2-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x20
>;
};
vmmc_pins: pinctrl-vmmc-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
vmpcie_pins: pinctrl-vmpcie-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x0
>;
};
};
&phy0 {
leds {
#address-cells = <1>;
#size-cells = <0>;
/* ADIN1300 LED_0 pin */
led@0 {
reg = <0>;
color = <LED_COLOR_ID_ORANGE>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
/* ADIN1300 LINK_ST pin */
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
default-state = "keep";
};
};
};
&snvs_pwrkey {
status = "okay";
};
/* mikrobus uart */
&uart3 {
status = "okay";
};
&usb3_phy0 {
fsl,phy-tx-preemp-amp-tune-microamp = <1200>;
vbus-supply = <&vbus2>;
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&vbus1>;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
};
&usb_dwc3_1 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&usb_hub_pins>;
hub_2_0: hub@1 {
compatible = "usb4b4,6502", "usb4b4,6506";
reg = <1>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
vdd-supply = <&v_1_2>;
vdd2-supply = <&v_3_3>;
};
hub_3_0: hub@2 {
compatible = "usb4b4,6500", "usb4b4,6504";
reg = <2>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
vdd-supply = <&v_1_2>;
vdd2-supply = <&v_3_3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&usdhc2_pins>;
pinctrl-1 = <&usdhc2_100mhz_pins>;
pinctrl-2 = <&usdhc2_200mhz_pins>;
vmmc-supply = <&vmmc>;
bus-width = <4>;
cap-power-off-card;
full-pwr-cycle;
status = "okay";
};

44
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-hdmi.dtsi Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/ {
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
};
&aud2htx {
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
status = "okay";
};
&hdmi_tx_phy {
status = "okay";
};
&iomuxc {
hdmi_pins: pinctrl-hdmi-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
>;
};
};
&lcdif3 {
status = "okay";
};

60
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-m2con.dtsi Normal file
View File

@ -0,0 +1,60 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/ {
rfkill-m2-gnss {
compatible = "rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&m2_gnss_rfkill_pins>;
label = "m.2 GNSS";
radio-type = "gps";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
/* M.2 is B-keyed, so w-disable is for WWAN */
rfkill-m2-wwan {
compatible = "rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&m2_wwan_rfkill_pins>;
label = "m.2 WWAN";
radio-type = "wwan";
/* rfkill-gpio inverts internally */
shutdown-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
};
};
&iomuxc {
m2_gnss_rfkill_pins: pinctrl-m2-gnss-rfkill-grp {
fsl,pins = <
/* weak i/o, open drain */
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x20
>;
};
m2_reset_pins: pinctrl-m2-reset-grp {
fsl,pins = <
/*
* 3.3V domain on SoC, set open-drain to ensure
* 1.8V logic on connector
*/
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x20
>;
};
m2_wwan_rfkill_pins: pinctrl-m2-wwan-rfkill-grp {
fsl,pins = <
/* weak i/o, open drain */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x20
>;
};
m2_wwan_wake_pins: pinctrl-m2-wwan-wake-grp {
fsl,pins = <
/* weak i/o, open drain */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x20
>;
};
};

81
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse-mini-hdmi.dtsi Normal file
View File

@ -0,0 +1,81 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/ {
hdmi-connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "c";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7535_out>;
};
};
};
};
&i2c3 {
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3f>, <0x3c>, <0x38>;
reg-names = "main", "edid", "cec", "packet";
adi,dsi-lanes = <4>;
avdd-supply = <&v_1_8>;
dvdd-supply = <&v_1_8>;
pvdd-supply = <&v_1_8>;
a2vdd-supply = <&v_1_8>;
v3p3-supply = <&v_3_3>;
pinctrl-names = "default";
pinctrl-0 = <&mini_hdmi_pins>;
interrupt-parent = <&gpio4>;
interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7535_from_dsim: endpoint {
remote-endpoint = <&dsim_to_adv7535>;
};
};
port@1 {
reg = <1>;
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
};
&iomuxc {
mini_hdmi_pins: pinctrl-mini-hdmi-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x0
>;
};
};
&lcdif1 {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
port@1 {
dsim_to_adv7535: endpoint {
remote-endpoint = <&adv7535_from_dsim>;
attach-bridge;
};
};
};

83
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-pulse.dts Normal file
View File

@ -0,0 +1,83 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-sr-som.dtsi"
#include "imx8mp-hummingboard-pulse-codec.dtsi"
#include "imx8mp-hummingboard-pulse-common.dtsi"
#include "imx8mp-hummingboard-pulse-hdmi.dtsi"
#include "imx8mp-hummingboard-pulse-m2con.dtsi"
#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
/ {
model = "SolidRun i.MX8MP HummingBoard Pulse";
compatible = "solidrun,imx8mp-hummingboard-pulse",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
ethernet1 = &pcie_eth;
};
};
&fec {
/* this board does not use second phy / ethernet on SoM */
status = "disabled";
};
&gpio1 {
pinctrl-0 = <&mpcie_reset_pins>, <&m2_reset_pins>;
pinctrl-names = "default";
m2-reset-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "m2-reset";
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&hdmi_pins>,
<&m2_wwan_wake_pins>;
pcie_eth_pins: pinctrl-pcie-eth-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0
>;
};
};
&pcie {
pinctrl-0 = <&pcie_eth_pins>;
pinctrl-names = "default";
reset-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
root@0,0 {
compatible = "pci16c3,abcd";
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
/* Intel i210 */
pcie_eth: ethernet@1,0 {
compatible = "pci8086,157b";
reg = <0x00010000 0 0 0 0>;
};
};
};
&pcie_phy {
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
fsl,clkreq-unsupported;
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
status = "okay";
};

31
arch/arm64/boot/dts/freescale/imx8mp-hummingboard-ripple.dts Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
/dts-v1/;
#include "imx8mp-sr-som.dtsi"
#include "imx8mp-hummingboard-pulse-common.dtsi"
#include "imx8mp-hummingboard-pulse-mini-hdmi.dtsi"
/ {
model = "SolidRun i.MX8MP HummingBoard Ripple";
compatible = "solidrun,imx8mp-hummingboard-ripple",
"solidrun,imx8mp-sr-som", "fsl,imx8mp";
aliases {
ethernet0 = &eqos;
/delete-property/ ethernet1;
};
};
&fec {
/* this board does not use second phy / ethernet on SoM */
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&mikro_pwm_pins>, <&mikro_int_pins>, <&mikro_rst_pins>;
};

59
arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts
View File

@ -123,40 +123,54 @@
/*
* Rename SoM signals according to board usage:
* SPI_A_WP -> CAN_ADDR0
* SPI_A_HOLD -> CAN_ADDR1
* GPIO_B_0 -> DIO1_OUT
* GPIO_B_1 -> DIO2_OUT
* GPIO_B_0 -> IO_EXP_INT
* GPIO_B_1 -> IO_EXP_RST
*/
&gpio3 {
gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
"SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1",
"SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
"UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
"SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
"PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT",
"DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1",
"PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "IO_EXP_INT",
"IO_EXP_RST", "", "BOOT_SEL0", "BOOT_SEL1",
"", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
"HDMI_CEC", "HDMI_HPD";
};
/*
* Rename SoM signals according to board usage:
* GPIO_B_5 -> DIO2_IN
* GPIO_B_6 -> DIO3_IN
* GPIO_B_7 -> DIO4_IN
* GPIO_B_3 -> DIO4_OUT
* GPIO_B_4 -> DIO1_IN
* GPIO_B_2 -> DIO3_OUT
* Rename SoM signals according to board usage and remove labels for unsed pins:
* GPIO_A_6 -> TFT_RESET
* GPIO_A_7 -> TFT_STBY
* GPIO_B_3 -> CSI_ENABLE
* GPIO_B_2 -> USB_HUB_RST
*/
&gpio4 {
gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0",
gpio-line-names = "", "", "", "",
"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
"ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN",
"DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS",
"ETH_A_TX_EN", "ETH_A_TX_CLK", "CSI_ENABLE", "",
"USB_HUB_RST", "TFT_RESET", "CAN_A_TX", "UART_A_CTS",
"UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
"GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
"TFT_STBY", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
};
/*
* Rename SoM signals according to board usage:
* SPI_A_SDI -> CAN_ADDR0
* SPI_A_SDO -> CAN_ADDR1
*/
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
"PWM_1", "PWM_0", "SPI_A_SCK", "CAN_ADDR1",
"CAN_ADDR0", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
"SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
"I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
"I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
"UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
"UART_B_RX", "UART_B_TX";
};
&hdmi_pvi {
@ -236,8 +250,6 @@
};
&usb_dwc3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_hub>;
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
@ -246,7 +258,7 @@
usb-hub@1 {
compatible = "usb424,2514";
reg = <1>;
reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
};
};
@ -297,9 +309,10 @@
>;
};
pinctrl_usb_hub: usbhubgrp {
pinctrl_gpio5: gpio5grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46
MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x46 /* CAN_ADR0 */
MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x46 /* CAN_ADR1 */
>;
};
};

2
arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts
View File

@ -83,7 +83,7 @@
compatible = "ti,tsc2046e-adc";
reg = <0>;
pinctrl-0 = <&pinctrl_touch>;
pinctrl-names ="default";
pinctrl-names = "default";
spi-max-frequency = <1000000>;
interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
#io-channel-cells = <1>;

591
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi Normal file
View File

@ -0,0 +1,591 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 Josua Mayer <josua@solid-run.com>
*/
#include "imx8mp.dtsi"
/ {
model = "SolidRun i.MX8MP SoM";
compatible = "solidrun,imx8mp-sr-som", "fsl,imx8mp";
chosen {
bootargs = "earlycon=ec_imx6q,0x30890000,115200";
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0xc0000000>,
<0x1 0x00000000 0 0xc0000000>;
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
v_1_8: regulator-1-8 {
compatible = "regulator-fixed";
regulator-name = "1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
v_3_3: regulator-3-3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
/*
* Reserve all physical memory from within the first 1GB of DDR address
* space to avoid panic on low memory systems.
*/
&dsp_reserved {
reg = <0 0x6f000000 0 0x1000000>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&eqos_pins>, <&phy0_pins>;
phy-mode = "rgmii-id";
phy = <&phy0>;
snps,force_thresh_dma_mode;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
};
};
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
};
};
mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <5>;
snps,rx-sched-sp;
queue0 {
snps,dcb-algorithm;
snps,priority = <0x1>;
snps,map-to-dma-channel = <0>;
};
queue1 {
snps,dcb-algorithm;
snps,priority = <0x2>;
snps,map-to-dma-channel = <1>;
};
queue2 {
snps,dcb-algorithm;
snps,priority = <0x4>;
snps,map-to-dma-channel = <2>;
};
queue3 {
snps,dcb-algorithm;
snps,priority = <0x8>;
snps,map-to-dma-channel = <3>;
};
queue4 {
snps,dcb-algorithm;
snps,priority = <0xf0>;
snps,map-to-dma-channel = <4>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&fec_pins>, <&phy1_pins>;
phy-mode = "rgmii-id";
phy = <&phy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&i2c1_gpio_pins>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-0 = <&pmic_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
nxp,i2c-lt-enable;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
som_eeprom: eeprom@50{
compatible = "st,24c01", "atmel,24c01";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_gpio_pins>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c3_pins>;
pinctrl-1 = <&i2c3_gpio_pins>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 {
/* routed to basler camera connector */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c4_pins>;
pinctrl-1 = <&i2c4_gpio_pins>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&iomuxc {
eqos_pins: pinctrl-eqos-grp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
>;
};
fec_pins: pinctrl-fec-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
>;
};
i2c1_pins: pinctrl-i2c1-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
i2c1_gpio_pins: pinctrl-i2c1-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c3
>;
};
i2c2_pins: pinctrl-i2c2-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
>;
};
i2c3_pins: pinctrl-i2c3-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
>;
};
i2c4_pins: pinctrl-i2c4-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
i2c4_gpio_pins: pinctrl-i2c4-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
>;
};
phy0_pins: pinctrl-phy0-grp {
fsl,pins = <
/* RESET_N: weak i/o, open drain, external 1k pull-up */
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x20
/* INT_N: weak i/o, open drain, internal pull-up */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x160
>;
};
phy1_pins: pinctrl-phy-1-grp {
fsl,pins = <
/* RESET_N: weak i/o, open drain, external 1k pull-up */
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x20
/* INT_N: weak i/o, open drain, internal pull-up */
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160
>;
};
pmic_pins: pinctrl-pmic-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
uart1_pins: pinctrl-uart1-grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
/* BT_REG_ON */
MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0
/* BT_WAKE_DEV */
MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0
/* BT_WAKE_HOST */
MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x100
>;
};
uart2_pins: pinctrl-uart2-grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
>;
};
usdhc1_pins: pinctrl-usdhc1-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
/* WL_REG_ON */
MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0
/* WL_WAKE_HOST */
MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x100
>;
};
usdhc1_100mhz_pins: pinctrl-usdhc1g-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
usdhc1_200mhz_pins: pinctrl-usdhc1-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
usdhc3_pins: pinctrl-usdhc3-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
usdhc3_100mhz_pins: pinctrl-usdhc3-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
usdhc3_200mhz_pins: pinctrl-usdhc3-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
wdog1_pins: pinctrl-wdog1-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140
>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
uart-has-rtscts;
/* select 80MHz parent clock to support maximum baudrate 4Mbps */
assigned-clocks = <&clk IMX8MP_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
status = "okay";
bluetooth {
compatible = "brcm,bcm4345c5";
device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
/* Murata 1MW module supports max. 3M baud */
max-speed = <3000000>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&usdhc1_pins>;
pinctrl-1 = <&usdhc1_100mhz_pins>;
pinctrl-2 = <&usdhc1_200mhz_pins>;
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
bus-width = <4>;
mmc-pwrseq = <&usdhc1_pwrseq>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&usdhc3_pins>;
pinctrl-1 = <&usdhc3_100mhz_pins>;
pinctrl-2 = <&usdhc3_200mhz_pins>;
vmmc-supply = <&v_3_3>;
vqmmc-supply = <&v_1_8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&wdog1_pins>;
status = "okay";
};

46
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts
View File

@ -36,6 +36,24 @@
vout-supply = <&reg_5v0_sensor>;
};
flexcan1_phy: can-phy0 {
compatible = "ti,tcan1051", "ti,tcan1042";
#phy-cells = <0>;
pinctrl-0 = <&pinctrl_flexcan1_stby>;
pinctrl-names = "default";
max-bitrate = <5000000>;
standby-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
};
flexcan2_phy: can-phy1 {
compatible = "ti,tcan1051", "ti,tcan1042";
#phy-cells = <0>;
pinctrl-0 = <&pinctrl_flexcan2_stby>;
pinctrl-names = "default";
max-bitrate = <5000000>;
standby-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
};
reg_1v8_per: regulator-1v8-per {
compatible = "regulator-fixed";
pinctrl-0 = <&pinctrl_reg_1v8>;
@ -85,26 +103,6 @@
regulator-name = "6v4";
};
reg_can1_stby: regulator-can1-stby {
compatible = "regulator-fixed";
pinctrl-0 = <&pinctrl_flexcan1_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can1-stby";
gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
pinctrl-0 = <&pinctrl_flexcan2_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can2-stby";
gpio = <&gpio5 9 GPIO_ACTIVE_LOW>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&cpudai>;
@ -180,16 +178,16 @@
};
&flexcan1 {
phys = <&flexcan1_phy>;
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default";
xceiver-supply = <&reg_can1_stby>;
status = "okay";
};
&flexcan2 {
phys = <&flexcan2_phy>;
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
@ -278,7 +276,7 @@
>;
};
pinctrl_flexcan1_reg: flexcan1reggrp {
pinctrl_flexcan1_stby: flexcan1stbygrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)
@ -294,7 +292,7 @@
>;
};
pinctrl_flexcan2_reg: flexcan2reggrp {
pinctrl_flexcan2_stby: flexcan2stbygrp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09
(MX8MP_DSE_X2 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | MX8MP_PULL_ENABLE)

907
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts Normal file
View File

@ -0,0 +1,907 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2025 Ultratronik
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx8mp.dtsi"
/ {
model = "NXP i.MX8MPlus Ultratronik MMI_A53 board";
compatible = "ultratronik,imx8mp-ultra-mach-sbc", "fsl,imx8mp";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
rtc0 = &hwrtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart2;
};
gpio-sbu-mux {
compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sbu_mux>;
select-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
enable-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
orientation-switch;
port {
usb3_data_ss: endpoint {
remote-endpoint = <&typec_con_ss>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
button-0 {
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; /* Wakeup */
label = "Wakeup";
linux,code = <KEY_WAKEUP>;
pinctrl-0 = <&pinctrl_gpio_key_wakeup>;
pinctrl-names = "default";
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "red";
gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led2 {
label = "green";
gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led3 {
label = "yellow";
gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
reg_usba_vbus: regulator-usba-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
regulator-name = "usb-A-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
slb9670: tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <32000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_slb9670>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
&ecspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio1 8 GPIO_ACTIVE_LOW>,
<&gpio1 9 GPIO_ACTIVE_LOW>;
status = "okay";
nfc-transceiver@1 {
compatible = "st,st95hf";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nfc>;
spi-max-frequency = <100000>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
enable-gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
};
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x2>;
interrupt-parent = <&gpio4>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&gpio1 {
gpio-line-names =
"#TPM_IRQ", "GPIO1", "", "#PMIC_INT",
"SD2_VSEL", "#TOUCH_IRQ", "#NFC_INT_I", "#NFC_INT",
"#SPI2_CS2", "#SPI2_CS3", "#RTS4", "",
"USB_PWR", "GPIO2", "GPIO3", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "#SD2_CD", "", "", "",
"", "", "", "", "#USB-C_EN", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "DISP_POW", "GPIO4",
"#", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"BKL_POW", "#ETH1_INT", "#TPM_RES", "#PCAP_RES",
"", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "#ETH0_INT", "#USB-C_ALERT",
"#USB-C_SEL", "", "", "",
"LED_RED", "LED_GREEN", "LED_YELLOW", "#WAKEUP",
"", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "#SPI1_CS", "", "", "", "#SPI2_CS1", "", "",
"", "", "", "", "ENA_KAM", "ENA_LED", "", "",
"", "", "", "", "", "", "", "";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
ddc-i2c-bus = <&i2c5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 GPIO_ACTIVE_LOW>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products
* 3.1.4 Operating ranges
* MIMX8ML8DVNLZAB
*/
regulators {
buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 { /* VDD_ARM */
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 { /* +3V3 */
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
buck5: BUCK5 { /* +1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
buck6: BUCK6 { /* DRAM_1V1 */
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
};
ldo1: LDO1 { /* NVCC_SNVS_1V8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo3: LDO3 { /* VDDA_1P8 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4: LDO4 { /* ENET_2V5 */
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
regulator-boot-on;
};
ldo5: LDO5 { /* NVCC_SD2 */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
};
crypto@35 {
compatible = "atmel,atecc508a";
reg = <0x35>;
};
eeprom@50 {
compatible = "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
hwrtc: rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
epson,vdet-disable;
trickle-diode-disable;
};
tcpc@52 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5110>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 5000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec_dr_sw: endpoint {
remote-endpoint = <&usb3_drd_sw>;
};
};
port@1 {
reg = <1>;
typec_con_ss: endpoint {
remote-endpoint = <&usb3_data_ss>;
};
};
};
};
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c5 { /* HDMI EDID bus */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-1 = <&pinctrl_i2c5_gpio>;
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&uart2 {
/* system console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
/* expansion port serial connection */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
status = "okay";
port {
usb3_drd_sw: endpoint {
remote-endpoint = <&typec_dr_sw>;
};
};
};
&usb3_phy1 {
vbus-supply = <&reg_usba_vbus>;
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
snps,hsphy_interface = "utmi";
status = "okay";
};
&usdhc2 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
vqmmc-supply = <&ldo5>;
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
vmmc-supply = <&buck4>;
vqmmc-supply = <&buck5>;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* #SPI1_CS */
>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82
>;
};
pinctrl_ecspi2_cs: ecspi2-cs-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* #SPI2_CS */
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40 /* #SPI2_CS2 */
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40 /* #SPI2_CS3 */
>;
};
pinctrl_ecspi2: ecspi2-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
>;
};
pinctrl_eqos: eqos-grp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x0
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x0
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x10 /* #ETH0_INT */
>;
};
pinctrl_fec: fec-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x0
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x10 /* #ETH1_INT */
>;
};
pinctrl_flexcan1: flexcan1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
>;
};
pinctrl_gpio_key_wakeup: gpio-key-wakeup-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40 /* #WAKEUP */
>;
};
pinctrl_gpio_leds: gpio-leds-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40 /* LED_RED */
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40 /* LED_GREEN */
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40 /* LED_YELLOW */
>;
};
pinctrl_hdmi: hdmi-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x154
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x154
>;
};
pinctrl_hog: hog-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x40 /* GPIO1 */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x40 /* GPIO2 */
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40 /* GPIO3 */
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x40 /* GPIO4 */
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x40 /* ENA_KAM */
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x40 /* ENA_LED */
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x40 /* #PCAP_RES */
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x40 /* #RTS4 */
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c0
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c0
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0xc0
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0xc0
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c0
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c0
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0xc0
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0xc0
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>;
};
pinctrl_i2c3_gpio: i2c3-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0xc2
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0xc2
>;
};
pinctrl_i2c5: i2c5-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400000c4
MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400000c4
>;
};
pinctrl_i2c5_gpio: i2c5-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0xc4
MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0xc4
>;
};
pinctrl_nfc: nfc-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x40 /* NFC_INT_I */
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */
>;
};
pinctrl_pmic: pmic-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */
>;
};
pinctrl_ptn5110: ptn5110-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* #USB-C_ALERT */
>;
};
pinctrl_pwm1: pwm1-grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116
>;
};
pinctrl_pwm2: pwm2-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x116 /* EXT_PWM */
>;
};
pinctrl_reg_usdhc2_vmmc: reg-usdhc2-vmmc-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>;
};
pinctrl_sbu_mux: sbu-mux-grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* #USB-C_SEL */
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x16 /* #USB-C_EN */
>;
};
pinctrl_slb9670: slb9670-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x40 /* #TPM_IRQ */
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40 /* #TPM_RES */
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>;
};
pinctrl_uart3: uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x40
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x40
>;
};
pinctrl_uart4: uart4-grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x40
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x40
>;
};
pinctrl_usb1: usb1-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x40 /* USB_PWR */
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 /* SD2_VSEL */
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x40 /* #SD3_RESET */
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x192
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d2
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x192
>;
};
pinctrl_wdog: wdog-grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 /* #WDOG */
>;
};
};

23
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -1701,9 +1701,12 @@
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "isp", "aclk", "hclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>;
clock-names = "isp", "aclk", "hclk", "pclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
<&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
power-domain-names = "isp", "csi2";
fsl,blk-ctrl = <&media_blk_ctrl 0>;
status = "disabled";
@ -1723,9 +1726,12 @@
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
clock-names = "isp", "aclk", "hclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>;
clock-names = "isp", "aclk", "hclk", "pclk";
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
<&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
power-domain-names = "isp", "csi2";
fsl,blk-ctrl = <&media_blk_ctrl 1>;
status = "disabled";
@ -2045,6 +2051,10 @@
"pai", "pvi", "trng",
"hdmi-tx", "hdmi-tx-phy",
"hdcp", "hrv";
interconnects = <&noc IMX8MP_ICM_HRV &noc IMX8MP_ICN_HDMI>,
<&noc IMX8MP_ICM_LCDIF_HDMI &noc IMX8MP_ICN_HDMI>,
<&noc IMX8MP_ICM_HDCP &noc IMX8MP_ICN_HDMI>;
interconnect-names = "hrv", "lcdif-hdmi", "hdcp";
#power-domain-cells = <1>;
};
@ -2317,6 +2327,7 @@
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
<0x38880000 0xc0000>;
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

8
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -108,6 +108,7 @@
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&cpudai>;
simple-audio-card,bitclock-master = <&cpudai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Line", "Left Line Out Jack",
"Line", "Right Line Out Jack";
@ -117,11 +118,11 @@
cpudai: simple-audio-card,cpu {
sound-dai = <&sai2>;
system-clock-direction-out;
};
link_codec: simple-audio-card,codec {
sound-dai = <&wm8524>;
clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
};
};
@ -440,6 +441,11 @@
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24576000>;
clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI2_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};

1
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1890,6 +1890,7 @@
<0x31000000 0x2000>, /* GICC */
<0x31010000 0x2000>, /* GICV */
<0x31020000 0x2000>; /* GICH */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -406,8 +406,8 @@
model = "wm8960-audio";
audio-cpu = <&sai1>;
audio-codec = <&wm8960>;
hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HP_L",
hp-det-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",

16
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
View File

@ -30,10 +30,10 @@
clock-names = "dbi", "mstr", "slv";
bus-range = <0x00 0xff>;
device_type = "pci";
interrupt-map = <0 0 0 1 &gic 0 73 4>,
<0 0 0 2 &gic 0 74 4>,
<0 0 0 3 &gic 0 75 4>,
<0 0 0 4 &gic 0 76 4>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0x7>;
num-lanes = <1>;
num-viewport = <4>;
@ -80,10 +80,10 @@
clock-names = "dbi", "mstr", "slv";
bus-range = <0x00 0xff>;
device_type = "pci";
interrupt-map = <0 0 0 1 &gic 0 105 4>,
<0 0 0 2 &gic 0 106 4>,
<0 0 0 3 &gic 0 107 4>,
<0 0 0 4 &gic 0 108 4>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0x7>;
num-lanes = <1>;
num-viewport = <4>;

1
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@ -245,6 +245,7 @@
<0x0 0x52000000 0 0x2000>, /* GICC */
<0x0 0x52010000 0 0x1000>, /* GICH */
<0x0 0x52020000 0 0x20000>; /* GICV */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -333,7 +333,7 @@
model = "wm8960-audio";
audio-cpu = <&sai1>;
audio-codec = <&wm8960>;
hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
hp-det-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",

1
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@ -159,6 +159,7 @@
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

69
arch/arm64/boot/dts/freescale/imx8ulp-9x9-evk.dts Normal file
View File

@ -0,0 +1,69 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
#include "imx8ulp-evk.dts"
/ {
model = "NXP i.MX8ULP EVK9";
compatible = "fsl,imx8ulp-9x9-evk", "fsl,imx8ulp";
};
&btcpu {
sound-dai = <&sai6>;
};
&iomuxc1 {
pinctrl_sai6: sai6grp {
fsl,pins = <
MX8ULP_PAD_PTE10__I2S6_TX_BCLK 0x43
MX8ULP_PAD_PTE11__I2S6_TX_FS 0x43
MX8ULP_PAD_PTE14__I2S6_TXD2 0x43
MX8ULP_PAD_PTE6__I2S6_RXD0 0x43
>;
};
};
&pinctrl_enet {
fsl,pins = <
MX8ULP_PAD_PTF9__ENET0_MDC 0x43
MX8ULP_PAD_PTF8__ENET0_MDIO 0x43
MX8ULP_PAD_PTF5__ENET0_RXER 0x43
MX8ULP_PAD_PTF6__ENET0_CRS_DV 0x43
MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
MX8ULP_PAD_PTF0__ENET0_RXD1 0x43
MX8ULP_PAD_PTF4__ENET0_TXEN 0x43
MX8ULP_PAD_PTF3__ENET0_TXD0 0x43
MX8ULP_PAD_PTF2__ENET0_TXD1 0x43
MX8ULP_PAD_PTF7__ENET0_REFCLK 0x43
MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
>;
};
&pinctrl_usb1 {
fsl,pins = <
MX8ULP_PAD_PTE16__USB0_ID 0x10003
MX8ULP_PAD_PTE18__USB0_OC 0x10003
>;
};
&pinctrl_usb2 {
fsl,pins = <
MX8ULP_PAD_PTD23__USB1_ID 0x10003
MX8ULP_PAD_PTE20__USB1_OC 0x10003
>;
};
&sai6 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai6>;
pinctrl-1 = <&pinctrl_sai6>;
assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>, <&cgc2 IMX8ULP_CLK_SAI6_SEL>;
assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
assigned-clock-rates = <12288000>;
fsl,dataline = <1 0x01 0x04>;
status = "okay";
};

4
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
View File

@ -462,11 +462,11 @@
/* VPU Mailboxes */
&mu_m0 {
status="okay";
status = "okay";
};
&mu1_m0 {
status="okay";
status = "okay";
};
/* TODO MIPI CSI */

674
arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts Normal file
View File

@ -0,0 +1,674 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx91.dtsi"
/ {
compatible = "fsl,imx91-11x11-evk", "fsl,imx91";
model = "NXP i.MX91 11X11 EVK board";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "vref_1v8";
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-always-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "audio-pwr";
gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
off-on-delay-us = <12000>;
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VSD_3V3";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x40000000>;
reusable;
size = <0 0x10000000>;
linux,cma-default;
};
};
};
&adc1 {
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&eqos {
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
pinctrl-names = "default", "sleep";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
realtek,clkout-disable;
};
};
};
&fec {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
pinctrl-names = "default", "sleep";
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 {
reg = <2>;
realtek,clkout-disable;
};
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-names = "default";
status = "okay";
audio_codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
DCVDD-supply = <&reg_audio_pwr>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
inertial-meter@6a {
compatible = "st,lsm6dso";
reg = <0x6a>;
};
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-names = "default";
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
#interrupt-cells = <2>;
interrupt-controller;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
interrupt-parent = <&gpio3>;
pinctrl-0 = <&pinctrl_pcal6524>;
pinctrl-names = "default";
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pcal6524>;
regulators {
buck1: BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2237500>;
regulator-min-microvolt = <650000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK4";
};
buck5: BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK5";
};
buck6: BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
regulator-name = "BUCK6";
};
ldo1: LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
regulator-name = "LDO1";
};
ldo4: LDO4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
regulator-name = "LDO4";
};
ldo5: LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
adp5585: io-expander@34 {
compatible = "adi,adp5585-00", "adi,adp5585";
reg = <0x34>;
#gpio-cells = <2>;
gpio-controller;
#pwm-cells = <3>;
gpio-reserved-ranges = <5 1>;
exp-sel-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-low;
};
};
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-names = "default";
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
typec1_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
ptn5110_2: tcpc@51 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x51>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
status = "okay";
typec2_con: connector {
compatible = "usb-c-connector";
data-role = "dual";
label = "USB-C";
op-sink-microwatt = <15000000>;
power-role = "dual";
self-powered;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
try-power-role = "sink";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec2_dr_sw: endpoint {
remote-endpoint = <&usb2_drd_sw>;
};
};
};
};
};
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&pcal6524>;
status = "okay";
};
};
&lpuart1 {
pinctrl-0 = <&pinctrl_uart1>;
pinctrl-names = "default";
status = "okay";
};
&lpuart5 {
pinctrl-0 = <&pinctrl_uart5>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&usbotg1 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
adp-disable;
disable-over-current;
dr_mode = "otg";
hnp-disable;
srp-disable;
usb-role-switch;
samsung,picophy-dc-vol-level-adjust = <7>;
samsung,picophy-pre-emp-curr-control = <3>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 {
bus-width = <8>;
non-removable;
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
status = "okay";
};
&usdhc2 {
bus-width = <4>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
no-mmc;
no-sdio;
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e
MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = <
MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e
MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e
MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e
MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e
MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e
MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e
MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
};

770
arch/arm64/boot/dts/freescale/imx91-pinfunc.h Normal file
View File

@ -0,0 +1,770 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright 2025 NXP
*/
#ifndef __DTS_IMX91_PINFUNC_H
#define __DTS_IMX91_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00
#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00
#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00
#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00
#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00
#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00
#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00
#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00
#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00
#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00
#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00
#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00
#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00
#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00
#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01
#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00
#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00
#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00
#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00
#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01
#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00
#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00
#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00
#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00
#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01
#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00
#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00
#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00
#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00
#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00
#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00
#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01
#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00
#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00
#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01
#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00
#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00
#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00
#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00
#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00
#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00
#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00
#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00
#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01
#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00
#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00
#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01
#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00
#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00
#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00
#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00
#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00
#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00
#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00
#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00
#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01
#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00
#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00
#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01
#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00
#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00
#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00
#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00
#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00
#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00
#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00
#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00
#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00
#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01
#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00
#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00
#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00
#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00
#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00
#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00
#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00
#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00
#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01
#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01
#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00
#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01
#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00
#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00
#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01
#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00
#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00
#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01
#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00
#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00
#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01
#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00
#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00
#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00
#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00
#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00
#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01
#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00
#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00
#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01
#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01
#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00
#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00
#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01
#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00
#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00
#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01
#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00
#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00
#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01
#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00
#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00
#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00
#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01
#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00
#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00
#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00
#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00
#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00
#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01
#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00
#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00
#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00
#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00
#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00
#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00
#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00
#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00
#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00
#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00
#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00
#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00
#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00
#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00
#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00
#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00
#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00
#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00
#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00
#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00
#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02
#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00
#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00
#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00
#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00
#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00
#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01
#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00
#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00
#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00
#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00
#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00
#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00
#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00
#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00
#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00
#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00
#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00
#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01
#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01
#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00
#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00
#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00
#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00
#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00
#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00
#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00
#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00
#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00
#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00
#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00
#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00
#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00
#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01
#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00
#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00
#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00
#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00
#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00
#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01
#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00
#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01
#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01
#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01
#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01
#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01
#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00
#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01
#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00
#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00
#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00
#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00
#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00
#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01
#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00
#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00
#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01
#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00
#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01
#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01
#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01
#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01
#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01
#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01
#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00
#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00
#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00
#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01
#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00
#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00
#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02
#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00
#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00
#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00
#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01
#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00
#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00
#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01
#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00
#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01
#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00
#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01
#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01
#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01
#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01
#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00
#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01
#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00
#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00
#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00
#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01
#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00
#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01
#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00
#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00
#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01
#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00
#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00
#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01
#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00
#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00
#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00
#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00
#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01
#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00
#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00
#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00
#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00
#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01
#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00
#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00
#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00
#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01
#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00
#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00
#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00
#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01
#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00
#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00
#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01
#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00
#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01
#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00
#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00
#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00
#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01
#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00
#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01
#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01
#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00
#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01
#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01
#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01
#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01
#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00
#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01
#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00
#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01
#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01
#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00
#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00
#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00
#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01
#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01
#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00
#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01
#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00
#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00
#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00
#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01
#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01
#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00
#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00
#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01
#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00
#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00
#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00
#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00
#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01
#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00
#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00
#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00
#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01
#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00
#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00
#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03
#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01
#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00
#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00
#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00
#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01
#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00
#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00
#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00
#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01
#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00
#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01
#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00
#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00
#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00
#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00
#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01
#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01
#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00
#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00
#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02
#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00
#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00
#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00
#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00
#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02
#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00
#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00
#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00
#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00
#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01
#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00
#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00
#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00
#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00
#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00
#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00
#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01
#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00
#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00
#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00
#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00
#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01
#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00
#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02
#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00
#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00
#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01
#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00
#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02
#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00
#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00
#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01
#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01
#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02
#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00
#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00
#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00
#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01
#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00
#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02
#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00
#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00
#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02
#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00
#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00
#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00
#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00
#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00
#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02
#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00
#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01
#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00
#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00
#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00
#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01
#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02
#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01
#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00
#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00
#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00
#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01
#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00
#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00
#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01
#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00
#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00
#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00
#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00
#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01
#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01
#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00
#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02
#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00
#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00
#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00
#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01
#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00
#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00
#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00
#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01
#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00
#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02
#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01
#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00
#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00
#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00
#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00
#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00
#endif /* __DTS_IMX91_PINFUNC_H */

739
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba91xxca.dts Normal file
View File

@ -0,0 +1,739 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel
* Author: Alexander Stein
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/usb/pd.h>
#include "imx91-tqma9131.dtsi"
/{
model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa91xxCA starter kit";
compatible = "tq,imx91-tqma9131-mba91xxca", "tq,imx91-tqma9131", "fsl,imx91";
chassis-type = "embedded";
chosen {
stdout-path = &lpuart1;
};
aliases {
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial1 = &lpuart2;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&tpm2 2 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_12v0>;
enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
* DT overlay
*/
power-supply = <&reg_3v3>;
enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
status = "disabled";
port {
panel_in: endpoint {
};
};
};
fan0: gpio-fan {
compatible = "gpio-fan";
gpios = <&expander2 4 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0>, <10000 1>;
fan-supply = <&reg_12v0>;
#cooling-cells = <2>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
switch-a {
label = "switcha";
linux,code = <BTN_0>;
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
wakeup-source;
};
switch-b {
label = "switchb";
linux,code = <BTN_1>;
gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
wakeup-source;
};
};
gpio-leds {
compatible = "gpio-leds";
led-1 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
};
led-2 {
color = <LED_COLOR_ID_AMBER>;
function = LED_FUNCTION_HEARTBEAT;
gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
};
lvds_encoder: lvds-encoder {
compatible = "ti,sn75lvds83", "lvds-encoder";
powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>;
power-supply = <&reg_3v3>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_encoder_input: endpoint {
};
};
port@1 {
reg = <1>;
lvds_encoder_output: endpoint {
};
};
};
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "V_5V0_MB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_12v0: regulator-12v0 {
compatible = "regulator-fixed";
regulator-name = "V_12V";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_mpcie_1v5: regulator-mpcie-1v5 {
compatible = "regulator-fixed";
regulator-name = "V_1V5_MPCIE";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_mpcie_3v3: regulator-mpcie-3v3 {
compatible = "regulator-fixed";
regulator-name = "V_3V3_MPCIE";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
};
&adc1 {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_eqos>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy_eqos: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_phy>;
reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy_fec>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <5000000>;
ethphy_fec: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_phy>;
reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <500000>;
reset-deassert-us = <50000>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
enet-phy-lane-no-swap;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3v3>;
status = "okay";
};
&gpio1 {
gpio-line-names =
/* 00 */ "", "", "", "PMIC_IRQ#",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#",
/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&gpio2 {
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_jtag>;
gpio-line-names =
/* 00 */ "SD2_CD#", "", "", "",
/* 04 */ "", "", "", "SD2_RST#",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
/* 28 */ "", "", "", "";
};
&gpio4 {
gpio-line-names =
/* 00 */ "", "", "", "",
/* 04 */ "", "", "", "",
/* 08 */ "", "", "", "",
/* 12 */ "", "", "", "",
/* 16 */ "", "", "", "",
/* 20 */ "", "", "", "",
/* 24 */ "", "", "", "",
/* 28 */ "", "", "", "";
};
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3>;
status = "okay";
temperature-sensor@1c {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1c>;
};
ptn5110: usb-typec@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
connector {
compatible = "usb-c-connector";
label = "X17";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
typec-power-opmode = "default";
pd-disable;
self-powered;
port {
typec_con_hs: endpoint {
remote-endpoint = <&typec_hs>;
};
};
};
};
eeprom2: eeprom@54 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
vcc-supply = <&reg_3v3>;
};
expander0: gpio@70 {
compatible = "nxp,pca9538";
reg = <0x70>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pexp_irq>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#",
"MPCIE_1V5_EN", "MPCIE_3V3_EN",
"MPCIE_PERST#", "MPCIE_WDISABLE#",
"BUTTON_A#", "BUTTON_B#";
temp-event-mod-hog {
gpio-hog;
gpios = <0 GPIO_ACTIVE_LOW>;
input;
line-name = "TEMP_EVENT_MOD#";
};
mpcie-wake-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_LOW>;
input;
line-name = "MPCIE_WAKE#";
};
/*
* Controls the mPCIE slot reset which is low active as
* reset signal. The output-low states, the signal is
* inactive, e.g. not in reset
*/
mpcie_rst_hog: mpcie-rst-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "MPCIE_PERST#";
};
/*
* Controls the mPCIE slot WDISABLE pin which is low active
* as disable signal. The output-low states, the signal is
* inactive, e.g. not disabled
*/
mpcie_wdisable_hog: mpcie-wdisable-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "MPCIE_WDISABLE#";
};
};
expander1: gpio@71 {
compatible = "nxp,pca9538";
reg = <0x71>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
"USB_RESET#", "",
"WLAN_PD#", "WLAN_W_DISABLE#",
"WLAN_PERST#", "12V_EN";
/*
* Controls the WiFi card PD pin which is low active
* as power down signal. The output-low states, the signal
* is inactive, e.g. not power down
*/
wlan-pd-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_PD#";
};
/*
* Controls the WiFi card disable pin which is low active
* as disable signal. The output-low states, the signal
* is inactive, e.g. not disabled
*/
wlan-wdisable-hog {
gpio-hog;
gpios = <5 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_W_DISABLE#";
};
/*
* Controls the WiFi card reset pin which is low active
* as reset signal. The output-low states, the signal
* is inactive, e.g. not in reset
*/
wlan-perst-hog {
gpio-hog;
gpios = <6 GPIO_ACTIVE_LOW>;
output-low;
line-name = "WLAN_PERST#";
};
};
expander2: gpio@72 {
compatible = "nxp,pca9538";
reg = <0x72>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3v3>;
gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
"LCD_BLT_EN", "LVDS_SHDN#",
"FAN_PWR_EN", "",
"USER_LED1", "USER_LED2";
};
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
status = "okay";
};
&pcf85063 {
/* RTC_EVENT# from SoM is connected on mainboard */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcf85063>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
};
&se97_som {
/* TEMP_EVENT# from SoM is connected on mainboard */
interrupt-parent = <&expander0>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&tpm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tpm2>;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
status = "okay";
port {
typec_hs: endpoint {
remote-endpoint = <&typec_con_hs>;
};
};
};
&usbotg2 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb424,2517";
reg = <1>;
reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
vdd-supply = <&reg_3v3>;
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
no-sdio;
no-mmc;
disable-wp;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e>,
/* SION | HYS | FSEL_2 | DSE X4 */
<MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>,
/* HYS | FSEL_0 | DSE no drive */
<MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>,
<MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>,
<MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>,
<MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>,
<MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>,
/* HYS | PD | FSEL_0 | DSE no drive */
<MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400>,
/* PD | FSEL_2 | DSE X4 */
<MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e>,
<MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e>,
<MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e>,
<MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e>,
<MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e>,
/* PD | FSEL_3 | DSE X3 */
<MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e>;
};
pinctrl_eqos_phy: eqosphygrp {
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
<MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>;
};
pinctrl_fec: fecgrp {
fsl,pins = /* PD | FSEL_2 | DSE X4 */
<MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e>,
/* SION | HYS | FSEL_2 | DSE X4 */
<MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e>,
/* HYS | FSEL_0 | DSE no drive */
<MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000>,
<MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000>,
<MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000>,
<MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000>,
<MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000>,
/* HYS | PD | FSEL_0 | DSE no drive */
<MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400>,
/* PD | FSEL_2 | DSE X4 */
<MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e>,
<MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e>,
<MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e>,
<MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e>,
<MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e>,
/* PD | FSEL_3 | DSE X3 */
<MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e>;
};
pinctrl_fec_phy: fecphygrp {
fsl,pins = /* HYS | FSEL_0 | DSE no drive */
<MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */
<MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>,
/* PU | FSEL_3 | DSE X4 */
<MX91_PAD_PDM_CLK__CAN1_TX 0x039e>;
};
pinctrl_jtag: jtaggrp {
fsl,pins = <MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>,
<MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>,
<MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>,
<MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */
<MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>,
<MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>;
};
pinctrl_pcf85063: pcf85063grp {
fsl,pins = <MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>;
};
pinctrl_pexp_irq: pexpirqgrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000>;
};
pinctrl_rgbdisp: rgbdispgrp {
fsl,pins = <MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e>,
<MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e>,
<MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e>,
<MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e>,
<MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x31e>,
<MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x31e>,
<MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x31e>,
<MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x31e>,
<MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x31e>,
<MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x31e>,
<MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x31e>,
<MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x31e>,
<MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x31e>,
<MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x31e>,
<MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e>,
<MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e>,
<MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e>,
<MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e>,
<MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e>,
<MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e>,
<MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e>,
<MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e>,
<MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x31e>,
<MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x31e>,
<MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x31e>,
<MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x31e>,
<MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x31e>,
<MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x31e>;
};
pinctrl_touch: touchgrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000>;
};
pinctrl_tpm2: tpm2grp {
fsl,pins = <MX91_PAD_I2C2_SCL__TPM2_CH2 0x57e>;
};
pinctrl_typec: typecgrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x1000>;
};
pinctrl_uart1: uart1grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX91_PAD_UART1_RXD__LPUART1_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX91_PAD_UART1_TXD__LPUART1_TX 0x011e>;
};
pinctrl_uart2: uart2grp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX91_PAD_UART2_RXD__LPUART2_RX 0x1000>,
/* FSEL_2 | DSE X4 */
<MX91_PAD_UART2_TXD__LPUART2_TX 0x011e>,
/* FSEL_2 | DSE X4 */
<MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = /* HYS | FSEL_0 | No DSE */
<MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_hs: usdhc2hsgrp {
fsl,pins = /* PD | FSEL_3 | DSE X5 */
<MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
/* HYS | PU | FSEL_3 | DSE X3 */
<MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>,
<MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>,
<MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>,
<MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>,
/* FSEL_2 | DSE X3 */
<MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
fsl,pins = /* PD | FSEL_3 | DSE X6 */
<MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe>,
/* HYS | PU | FSEL_3 | DSE X4 */
<MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>,
<MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>,
<MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>,
<MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>,
<MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>,
/* FSEL_2 | DSE X3 */
<MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>;
};
};

295
arch/arm64/boot/dts/freescale/imx91-tqma9131.dtsi Normal file
View File

@ -0,0 +1,295 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
* D-82229 Seefeld, Germany.
* Author: Markus Niebel
* Author: Alexander Stein
*/
#include "imx91.dtsi"
/{
model = "TQ-Systems i.MX91 TQMa91xxCA / TQMa91xxLA SOM";
compatible = "tq,imx91-tqma9131", "fsl,imx91";
memory@80000000 {
device_type = "memory";
/* our minimum RAM config will be 1024 MiB */
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* default CMA, must not exceed assembled memory */
linux,cma {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0 0x80000000 0 0x40000000>;
size = <0 0x10000000>;
linux,cma-default;
};
/* EdgeLock secure enclave */
ele_reserved: ele-reserved@a4120000 {
compatible = "shared-dma-pool";
reg = <0 0xa4120000 0 0x100000>;
no-map;
};
};
/* SD2 RST# via PMIC SW_EN */
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&buck4>;
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&buck5>;
};
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
/*
* no DQS, RXCLKSRC internal loop back, max 66 MHz
* clk framework uses CLK_DIVIDER_ROUND_CLOSEST
* selected value together with root from
* IMX91_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to
* respect the maximum value.
*/
spi-max-frequency = <62000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
vcc-supply = <&buck5>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
};
};
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c1>;
pinctrl-1 = <&pinctrl_lpi2c1>;
status = "okay";
se97_som: temperature-sensor@1b {
compatible = "nxp,se97b", "jedec,jc-42.4-temp";
reg = <0x1b>;
};
pca9451a: pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pca9451>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
/* V_0V8_SOC - hw developer guide: 0.75 .. 0.9 */
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* V_DDRQ - 1.1 V for LPDDR4 */
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
/* V_3V3 - EEPROM, RTC, ... */
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8 - SPI NOR, eMMC, RAM VDD1... */
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V1 - RAM VDD2*/
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
/* V_1V8_BBSM, fix 1.8 */
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_0V8_ANA */
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* V_SD2 - 3.3/1.8V USDHC2 io Voltage */
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
pcf85063: rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
quartz-load-femtofarads = <7000>;
};
eeprom0: eeprom@53 {
compatible = "nxp,se97b", "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
read-only;
vcc-supply = <&buck4>;
};
eeprom1: eeprom@57 {
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
vcc-supply = <&buck4>;
};
/* protectable identification memory (part of M24C64-D @57) */
eeprom@5f {
compatible = "atmel,24c64d-wl";
reg = <0x5f>;
vcc-supply = <&buck4>;
};
accelerometer@6a {
compatible = "st,ism330dhcx";
reg = <0x6a>;
vdd-supply = <&buck4>;
vddio-supply = <&buck4>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
vmmc-supply = <&buck4>;
vqmmc-supply = <&buck5>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
&wdog3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_flexspi1: flexspi1grp {
fsl,pins = /* FSEL 3 | DSE X6 */
<MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x01fe>,
<MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x01fe>,
/* HYS | PU | FSEL 3 | DSE X6 */
<MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x13fe>,
<MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x13fe>,
/* HYS | FSEL 3 | DSE X6 (external PU) */
<MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x11fe>,
<MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x11fe>;
};
pinctrl_lpi2c1: lpi2c1grp {
fsl,pins = /* SION | OD | FSEL 3 | DSE X4 */
<MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x4000199e>,
<MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x4000199e>;
};
pinctrl_pca9451: pca9451grp {
fsl,pins = /* HYS | PU */
<MX91_PAD_I2C2_SDA__GPIO1_IO3 0x1200>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = /* FSEL 2 | DSE X2 */
<MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x106>;
};
/* enable SION for data and cmd pad due to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = /* PD | FSEL 3 | DSE X5 */
<MX91_PAD_SD1_CLK__USDHC1_CLK 0x5be>,
/* HYS | FSEL 0 | no drive */
<MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1000>,
/* HYS | FSEL 3 | X5 */
<MX91_PAD_SD1_CMD__USDHC1_CMD 0x400011be>,
/* HYS | FSEL 3 | X4 */
<MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x4000119e>,
<MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x4000119e>,
<MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x4000119e>,
<MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x4000119e>,
<MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x4000119e>,
<MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x4000119e>,
<MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x4000119e>,
<MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x4000119e>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = /* PU | FSEL 1 | DSE X4 */
<MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e>;
};
};

71
arch/arm64/boot/dts/freescale/imx91.dtsi Normal file
View File

@ -0,0 +1,71 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2025 NXP
*/
#include "imx91-pinfunc.h"
#include "imx91_93_common.dtsi"
&clk {
compatible = "fsl,imx91-ccm";
};
&ddr_pmu {
compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu";
};
&eqos {
clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>,
<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET1_QOS_TSN>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
};
&fec {
clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET2_REGULAR_GATE>,
<&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>,
<&clk IMX93_CLK_DUMMY>;
assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
<&clk IMX91_CLK_ENET2_REGULAR>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
assigned-clock-rates = <100000000>, <250000000>;
};
&i3c1 {
clocks = <&clk IMX93_CLK_BUS_AON>,
<&clk IMX93_CLK_I3C1_GATE>,
<&clk IMX93_CLK_DUMMY>;
};
&i3c2 {
clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
<&clk IMX93_CLK_I3C2_GATE>,
<&clk IMX93_CLK_DUMMY>;
};
&iomuxc {
compatible = "fsl,imx91-iomuxc";
};
&media_blk_ctrl {
compatible = "fsl,imx91-media-blk-ctrl", "syscon";
clocks = <&clk IMX93_CLK_MEDIA_APB>,
<&clk IMX93_CLK_MEDIA_AXI>,
<&clk IMX93_CLK_NIC_MEDIA_GATE>,
<&clk IMX93_CLK_MEDIA_DISP_PIX>,
<&clk IMX93_CLK_CAM_PIX>,
<&clk IMX93_CLK_LCDIF_GATE>,
<&clk IMX93_CLK_ISI_GATE>,
<&clk IMX93_CLK_MIPI_CSI_GATE>;
clock-names = "apb", "axi", "nic", "disp", "cam",
"lcdif", "isi", "csi";
};

1187
arch/arm64/boot/dts/freescale/imx91_93_common.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

20
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@ -12,6 +12,25 @@
model = "NXP i.MX93 11X11 EVK board";
compatible = "fsl,imx93-11x11-evk", "fsl,imx93";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};
@ -272,7 +291,6 @@
ethphy2: ethernet-phy@2 {
reg = <2>;
eee-broken-1000t;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;

19
arch/arm64/boot/dts/freescale/imx93-14x14-evk.dts
View File

@ -12,6 +12,21 @@
model = "NXP i.MX93 14X14 EVK board";
compatible = "fsl,imx93-14x14-evk", "fsl,imx93";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
};
chosen {
stdout-path = &lpuart1;
};
@ -276,7 +291,7 @@
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
@ -284,7 +299,7 @@
regulator-always-on;
};
buck5: BUCK5{
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;

18
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@ -17,6 +17,24 @@
compatible = "linux,bt-sco";
};
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
};
chosen {
stdout-path = &lpuart1;
};

53
arch/arm64/boot/dts/freescale/imx93-kontron-bl-osm-s.dts
View File

@ -14,6 +14,27 @@
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
spi0 = &lpspi1;
spi1 = &lpspi2;
spi2 = &lpspi3;
spi3 = &lpspi4;
spi4 = &lpspi5;
spi5 = &lpspi6;
spi6 = &lpspi7;
spi7 = &lpspi8;
};
leds {
@ -33,7 +54,9 @@
reg_vcc_panel: regulator-vcc-panel {
compatible = "regulator-fixed";
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vcc_panel>;
gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
@ -135,6 +158,16 @@
};
&usbotg1 {
adp-disable;
hnp-disable;
srp-disable;
disable-over-current;
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usbotg2 {
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
@ -147,17 +180,15 @@
};
};
&usbotg2 {
adp-disable;
hnp-disable;
srp-disable;
disable-over-current;
dr_mode = "otg";
usb-role-switch;
status = "okay";
};
&usdhc2 {
vmmc-supply = <&reg_vdd_3v3>;
status = "okay";
};
&iomuxc {
pinctrl_reg_vcc_panel: regvccpanelgrp {
fsl,pins = <
MX93_PAD_GPIO_IO21__GPIO2_IO21 0x31e /* PWM_2 */
>;
};
};

9
arch/arm64/boot/dts/freescale/imx93-kontron-osm-s.dtsi
View File

@ -205,6 +205,9 @@
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio3 19 IRQ_TYPE_LEVEL_LOW>;
};
};
@ -468,6 +471,12 @@
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e /* I2S_A_DATA_IN */

35
arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
View File

@ -19,14 +19,44 @@
aliases {
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &i2c_rtc;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
spi0 = &lpspi1;
spi1 = &lpspi2;
spi2 = &lpspi3;
spi3 = &lpspi4;
spi4 = &lpspi5;
spi5 = &lpspi6;
};
chosen {
stdout-path = &lpuart1;
};
curr_sens: current-sense {
compatible = "current-sense-amplifier";
#io-channel-cells = <0>;
io-channels = <&adc1 1>;
sense-gain-div = <2>;
sense-gain-mult = <50>;
sense-resistor-micro-ohms = <35000>;
};
flexcan1_tc: can-phy0 {
compatible = "ti,tcan1042";
#phy-cells = <0>;
@ -36,6 +66,11 @@
standby-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&curr_sens 0>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;

9
arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
View File

@ -19,8 +19,17 @@
aliases {
ethernet1 = &eqos;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &i2c_rtc;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
};
chosen {

12
arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
View File

@ -67,7 +67,6 @@
pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
fsl,magic-packet;
assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
<&clk IMX93_CLK_ENET_REF>,
<&clk IMX93_CLK_ENET_REF_PHY>;
@ -85,6 +84,8 @@
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
reset-assert-us = <30>;
};
};
};
@ -206,14 +207,17 @@
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x50e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x502
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x5fe
/* the three pins below are connected to PHYs straps,
* that is what the pull-up/down setting is for.
*/
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x37e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x37e
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x50e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x50e
MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x50e
MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x4000050e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
>;
};

11
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba91xxca.dts
View File

@ -27,8 +27,19 @@
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
};
backlight: backlight {

25
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
View File

@ -28,8 +28,33 @@
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
spi0 = &lpspi1;
spi1 = &lpspi2;
spi2 = &lpspi3;
spi3 = &lpspi4;
spi4 = &lpspi5;
spi5 = &lpspi6;
};
backlight_lvds: backlight {

25
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts
View File

@ -28,8 +28,33 @@
eeprom0 = &eeprom0;
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
rtc0 = &pcf85063;
rtc1 = &bbnsm_rtc;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
spi0 = &lpspi1;
spi1 = &lpspi2;
spi2 = &lpspi3;
spi3 = &lpspi4;
spi4 = &lpspi5;
spi5 = &lpspi6;
};
backlight_lvds: backlight {

17
arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts
View File

@ -17,8 +17,25 @@
aliases {
ethernet0 = &eqos;
ethernet1 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial1 = &lpuart2;
serial2 = &lpuart3;
serial3 = &lpuart4;
serial4 = &lpuart5;
serial5 = &lpuart6;
};
chosen {
stdout-path = &lpuart1;
};

1430
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

File diff suppressed because it is too large Load Diff

6
arch/arm64/boot/dts/freescale/imx94.dtsi
View File

@ -212,7 +212,8 @@
<&a55_irqsteer 88>, <&a55_irqsteer 89>,
<&a55_irqsteer 90>, <&a55_irqsteer 91>,
<&a55_irqsteer 92>, <&a55_irqsteer 93>,
<&a55_irqsteer 94>, <&a55_irqsteer 95>;
<&a55_irqsteer 94>, <&a55_irqsteer 95>,
<&gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
mu10: mailbox@42430000 {
@ -619,7 +620,8 @@
<&a55_irqsteer 216>, <&a55_irqsteer 217>,
<&a55_irqsteer 218>, <&a55_irqsteer 219>,
<&a55_irqsteer 220>, <&a55_irqsteer 221>,
<&a55_irqsteer 222>, <&a55_irqsteer 223>;
<&a55_irqsteer 222>, <&a55_irqsteer 223>,
<&gic GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
};
};

30
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
View File

@ -28,7 +28,24 @@
aliases {
ethernet0 = &enetc_port0;
ethernet1 = &enetc_port1;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &lpuart1;
serial4 = &lpuart5;
};
bt_sco_codec: bt-sco-codec {
@ -864,12 +881,12 @@
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e
IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e
IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
@ -1082,6 +1099,7 @@
fsl,phy-pcs-tx-swing-full-percent = <100>;
fsl,phy-tx-preemp-amp-tune-microamp = <600>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
fsl,phy-tx-vref-tune-percent = <100>;
status = "okay";
port {

99
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@ -40,6 +40,7 @@
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
serial4 = &lpuart5;
};
bt_sco_codec: audio-codec-bt-sco {
@ -135,6 +136,13 @@
regulator-max-microvolt = <3300000>;
gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* M.2 device only can be enabled(W_DISABLE1#) after all Power
* Rails reach their minimum operating voltage (PCI Express M.2
* Specification r5.1 3.1.4 Power-up Timing).
* Set a delay equal to the max value of Tsettle here.
*/
startup-delay-us = <5000>;
};
reg_pcie0: regulator-pcie {
@ -216,7 +224,7 @@
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
hp-det-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
@ -302,6 +310,19 @@
reg = <0x20>;
vcc-supply = <&reg_3p3v>;
};
pca9632: pca9632@62 {
compatible = "nxp,pca9632";
reg = <0x62>;
#address-cells = <1>;
#size-cells = <0>;
led_baclklight: led@0 {
reg = <0>;
label = "backlight";
linux,default-trigger = "none";
};
};
};
&lpi2c4 {
@ -622,6 +643,7 @@
fsl,phy-pcs-tx-swing-full-percent = <100>;
fsl,phy-tx-preemp-amp-tune-microamp = <600>;
fsl,phy-tx-vboost-level-microvolt = <1156>;
fsl,phy-tx-vref-tune-percent = <100>;
orientation-switch;
status = "okay";
@ -671,7 +693,7 @@
};
&scmi_iomuxc {
pinctrl_emdio: emdiogrp{
pinctrl_emdio: emdiogrp {
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e
@ -1037,6 +1059,79 @@
};
};
};
pf09-thermal {
polling-delay = <2000>;
polling-delay-passive = <250>;
thermal-sensors = <&scmi_sensor 2>;
trips {
pf09_alert: trip0 {
hysteresis = <2000>;
temperature = <140000>;
type = "passive";
};
pf09_crit: trip1 {
hysteresis = <2000>;
temperature = <155000>;
type = "critical";
};
};
};
pf53arm-thermal {
polling-delay = <2000>;
polling-delay-passive = <250>;
thermal-sensors = <&scmi_sensor 4>;
cooling-maps {
map0 {
trip = <&pf5301_alert>;
cooling-device =
<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
trips {
pf5301_alert: trip0 {
hysteresis = <2000>;
temperature = <140000>;
type = "passive";
};
pf5301_crit: trip1 {
hysteresis = <2000>;
temperature = <155000>;
type = "critical";
};
};
};
pf53soc-thermal {
polling-delay = <2000>;
polling-delay-passive = <250>;
thermal-sensors = <&scmi_sensor 3>;
trips {
pf5302_alert: trip0 {
hysteresis = <2000>;
temperature = <140000>;
type = "passive";
};
pf5302_crit: trip1 {
hysteresis = <2000>;
temperature = <155000>;
type = "critical";
};
};
};
};
&tpm6 {

207
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -260,35 +260,35 @@
sai1_mclk: clock-sai-mclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai1_mclk";
};
sai2_mclk: clock-sai-mclk2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai2_mclk";
};
sai3_mclk: clock-sai-mclk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai3_mclk";
};
sai4_mclk: clock-sai-mclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai4_mclk";
};
sai5_mclk: clock-sai-mclk5 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <0>;
clock-frequency = <0>;
clock-output-names = "sai5_mclk";
};
@ -351,10 +351,18 @@
reg = <0x19>;
};
scmi_lmm: protocol@80 {
reg = <0x80>;
};
scmi_bbm: protocol@81 {
reg = <0x81>;
};
scmi_cpu: protocol@82 {
reg = <0x82>;
};
scmi_misc: protocol@84 {
reg = <0x84>;
};
@ -484,6 +492,110 @@
#size-cells = <2>;
ranges;
etm0: etm@40840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x0 0x40840000 0x0 0x10000>;
arm,primecell-periphid = <0xbb95d>;
cpu = <&A55_0>;
clocks = <&scmi_clk IMX95_CLK_A55PERIPH>;
clock-names = "apb_pclk";
status = "disabled";
out-ports {
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
};
};
};
};
funnel0: funnel {
/*
* non-configurable funnel don't show up on the AMBA
* bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-static-funnel";
status = "disabled";
in-ports {
port {
ca_funnel_in_port0: endpoint {
remote-endpoint = <&etm0_out_port>;
};
};
};
out-ports {
port {
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
};
};
};
funnel1: funnel-sys {
compatible = "arm,coresight-static-funnel";
status = "disabled";
in-ports {
port {
hugo_funnel_in_port0: endpoint {
remote-endpoint = <&ca_funnel_out_port0>;
};
};
};
out-ports {
port {
hugo_funnel_out_port0: endpoint {
remote-endpoint = <&etf_in_port>;
};
};
};
};
etf: etf@41030000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x41030000 0x0 0x1000>;
clocks = <&scmi_clk IMX95_CLK_A55PERIPH>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
etf_in_port: endpoint {
remote-endpoint = <&hugo_funnel_out_port0>;
};
};
};
out-ports {
port {
etf_out_port: endpoint {
remote-endpoint = <&etr_in_port>;
};
};
};
};
etr: etr@41040000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x0 0x41040000 0x0 0x1000>;
clocks = <&scmi_clk IMX95_CLK_A55PERIPH>;
clock-names = "apb_pclk";
status = "disabled";
in-ports {
port {
etr_in_port: endpoint {
remote-endpoint = <&etf_out_port>;
};
};
};
};
aips2: bus@42000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x0 0x42000000 0x0 0x800000>;
@ -913,7 +1025,7 @@
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX95_CLK_LPUART7>;
clock-names = "ipg";
dmas = <&edma2 26 0 FSL_EDMA_RX>, <&edma2 25 0 0>;
dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -925,7 +1037,7 @@
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk IMX95_CLK_LPUART8>;
clock-names = "ipg";
dmas = <&edma2 28 0 FSL_EDMA_RX>, <&edma2 27 0 0>;
dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -1100,7 +1212,7 @@
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
@ -1117,7 +1229,7 @@
assigned-clock-rates = <400000000>;
bus-width = <4>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
@ -1134,7 +1246,7 @@
assigned-clock-rates = <400000000>;
bus-width = <4>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step= <2>;
fsl,tuning-step = <2>;
status = "disabled";
};
};
@ -1260,6 +1372,15 @@
status = "disabled";
};
system_counter: timer@44290000 {
compatible = "nxp,imx95-sysctr-timer";
reg = <0x44290000 0x30000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc_24m>;
clock-names = "per";
nxp,no-divider;
};
tpm1: pwm@44310000 {
compatible = "fsl,imx7ulp-pwm";
reg = <0x44310000 0x1000>;
@ -1483,6 +1604,13 @@
};
};
mailbox@47300000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47300000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47320000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47320000 0x0 0x10000>;
@ -1490,6 +1618,20 @@
#mbox-cells = <2>;
};
mailbox@47330000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47330000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47340000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47340000 0x0 0x10000>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
mailbox@47350000 {
compatible = "fsl,imx95-mu-v2x";
reg = <0x0 0x47350000 0x0 0x10000>;
@ -1515,6 +1657,25 @@
status = "disabled";
};
ocotp: efuse@47510000 {
compatible = "fsl,imx95-ocotp", "syscon";
reg = <0x0 0x47510000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
eth_mac0: mac-address@0 {
reg = <0x0514 0x6>;
};
eth_mac1: mac-address@1 {
reg = <0x1514 0x6>;
};
eth_mac2: mac-address@2 {
reg = <0x2514 0x6>;
};
};
elemu0: mailbox@47520000 {
compatible = "fsl,imx95-mu-ele";
reg = <0x0 0x47520000 0x0 0x10000>;
@ -1685,9 +1846,9 @@
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
@ -1719,12 +1880,13 @@
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
msi-map = <0x0 &its 0x98 0x1>;
power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
status = "disabled";
};
@ -1759,9 +1921,9 @@
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>,
<&hsio_blk_ctl 0>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
@ -1795,9 +1957,9 @@
<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
<&scmi_clk IMX95_CLK_HSIOPLL>,
<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
assigned-clock-rates = <3600000000>, <100000000>, <10000000>;
assigned-clock-parents = <0>, <0>,
<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
@ -1948,6 +2110,7 @@
};
netc_timer: ethernet@18,0 {
compatible = "pci1131,ee02";
reg = <0x00c000 0 0 0 0>;
status = "disabled";
};

126
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@ -325,6 +325,81 @@
};
};
ocotp: nvmem@400a4000 {
compatible = "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
};
swt0: watchdog@40100000 {
compatible = "nxp,s32g2-swt";
reg = <0x40100000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt1: watchdog@40104000 {
compatible = "nxp,s32g2-swt";
reg = <0x40104000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt2: watchdog@40108000 {
compatible = "nxp,s32g2-swt";
reg = <0x40108000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt3: watchdog@4010c000 {
compatible = "nxp,s32g2-swt";
reg = <0x4010c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm0: timer@4011c000 {
compatible = "nxp,s32g2-stm";
reg = <0x4011c000 0x3000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm1: timer@40120000 {
compatible = "nxp,s32g2-stm";
reg = <0x40120000 0x3000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm2: timer@40124000 {
compatible = "nxp,s32g2-stm";
reg = <0x40124000 0x3000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm3: timer@40128000 {
compatible = "nxp,s32g2-stm";
reg = <0x40128000 0x3000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
status = "disabled";
};
edma0: dma-controller@40144000 {
compatible = "nxp,s32g2-edma";
reg = <0x40144000 0x24000>,
@ -479,6 +554,57 @@
status = "disabled";
};
swt4: watchdog@40200000 {
compatible = "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt5: watchdog@40204000 {
compatible = "nxp,s32g2-swt";
reg = <0x40204000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt6: watchdog@40208000 {
compatible = "nxp,s32g2-swt";
reg = <0x40208000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm4: timer@4021c000 {
compatible = "nxp,s32g2-stm";
reg = <0x4021c000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm5: timer@40220000 {
compatible = "nxp,s32g2-stm";
reg = <0x40220000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm6: timer@40224000 {
compatible = "nxp,s32g2-stm";
reg = <0x40224000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
edma1: dma-controller@40244000 {
compatible = "nxp,s32g2-edma";
reg = <0x40244000 0x24000>,

20
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
View File

@ -40,6 +40,26 @@
status = "okay";
};
&stm0 {
status = "okay";
};
&stm1 {
status = "okay";
};
&stm2 {
status = "okay";
};
&stm3 {
status = "okay";
};
&swt0 {
status = "okay";
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;

202
arch/arm64/boot/dts/freescale/s32g3.dtsi
View File

@ -383,6 +383,81 @@
};
};
ocotp: nvmem@400a4000 {
compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
reg = <0x400a4000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
};
swt0: watchdog@40100000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40100000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt1: watchdog@40104000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40104000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt2: watchdog@40108000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40108000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt3: watchdog@4010c000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x4010c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm0: timer@4011c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4011c000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm1: timer@40120000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40120000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm2: timer@40124000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40124000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm3: timer@40128000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40128000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
edma0: dma-controller@40144000 {
compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
reg = <0x40144000 0x24000>,
@ -542,6 +617,65 @@
status = "disabled";
};
swt4: watchdog@40200000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40200000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt5: watchdog@40204000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40204000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt6: watchdog@40208000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40208000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt7: watchdog@4020C000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x4020C000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm4: timer@4021c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4021c000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm5: timer@40220000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40220000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm6: timer@40224000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40224000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
edma1: dma-controller@40244000 {
compatible = "nxp,s32g3-edma", "nxp,s32g2-edma";
reg = <0x40244000 0x24000>,
@ -670,6 +804,74 @@
status = "disabled";
};
swt8: watchdog@40500000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <40500000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt9: watchdog@40504000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40504000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt10: watchdog@40508000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x40508000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
swt11: watchdog@4050c000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
reg = <0x4050c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
stm8: timer@40520000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40520000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm9: timer@40524000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40524000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm10: timer@40528000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x40528000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
stm11: timer@4052c000 {
compatible = "nxp,s32g3-stm", "nxp,s32g2-stm";
reg = <0x4052c000 0x3000>;
clocks = <&clks 0x3b>, <&clks 0x3c>, <&clks 0x3c>;
clock-names = "counter", "module", "register";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;

36
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
View File

@ -40,6 +40,42 @@
status = "okay";
};
&stm0 {
status = "okay";
};
&stm1 {
status = "okay";
};
&stm2 {
status = "okay";
};
&stm3 {
status = "okay";
};
&stm4 {
status = "okay";
};
&stm5 {
status = "okay";
};
&stm6 {
status = "okay";
};
&stm8 {
status = "okay";
};
&swt0 {
status = "okay";
};
&i2c4 {
current-sensor@40 {
compatible = "ti,ina231";