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phy: rockchip: inno-dsidphy: Add support for rk3506
For MIPI mode, the inno-dsidphy found on RK3506 supports up to 2 lanes and a maximum data rate of 1.5GHz. Signed-off-by: Hongming Zou <hongming.zou@rock-chips.com> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251106020632.92-7-kernel@airkyi.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Chaoyi Chen
Vinod Koul
parent
323c5c05a0
commit
785a9d5bb1
@ -99,10 +99,30 @@
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#define VOD_MID_RANGE 0x3
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#define VOD_BIG_RANGE 0x7
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#define VOD_MAX_RANGE 0xf
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/* Analog Register Part: reg18 */
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#define LANE0_PRE_EMPHASIS_ENABLE_MASK BIT(6)
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#define LANE0_PRE_EMPHASIS_ENABLE BIT(6)
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#define LANE0_PRE_EMPHASIS_DISABLE 0
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#define LANE1_PRE_EMPHASIS_ENABLE_MASK BIT(5)
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#define LANE1_PRE_EMPHASIS_ENABLE BIT(5)
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#define LANE1_PRE_EMPHASIS_DISABLE 0
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/* Analog Register Part: reg19 */
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#define PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
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#define PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
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/* Analog Register Part: reg1E */
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#define PLL_MODE_SEL_MASK GENMASK(6, 5)
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#define PLL_MODE_SEL_LVDS_MODE 0
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#define PLL_MODE_SEL_MIPI_MODE BIT(5)
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/* Analog Register Part: reg20 */
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#define LANE0_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
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#define LANE0_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
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/* Analog Register Part: reg21 */
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#define LANE1_PRE_EMPHASIS_RANGE_SET_MASK GENMASK(7, 6)
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#define LANE1_PRE_EMPHASIS_RANGE_SET(x) UPDATE(x, 7, 6)
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#define PRE_EMPHASIS_MIN_RANGE 0x0
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#define PRE_EMPHASIS_MID_RANGE 0x1
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#define PRE_EMPHASIS_MAX_RANGE 0x2
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#define PRE_EMPHASIS_RESERVED_RANGE 0x3
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/* Digital Register Part: reg00 */
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#define REG_DIG_RSTN_MASK BIT(0)
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#define REG_DIG_RSTN_NORMAL BIT(0)
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@ -193,6 +213,7 @@
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enum phy_max_rate {
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MAX_1GHZ,
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MAX_1_5GHZ,
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MAX_2_5GHZ,
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};
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@ -200,6 +221,7 @@ struct inno_video_phy_plat_data {
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const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
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const unsigned int num_timings;
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enum phy_max_rate max_rate;
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unsigned int max_lanes;
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};
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struct inno_dsidphy {
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@ -258,6 +280,24 @@ struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1ghz[] = {
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{1000000000, 0x0, 0x09, 0x20, 0x09, 0x27},
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};
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static const
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struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1_5ghz[] = {
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{ 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
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{ 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
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{ 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
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{ 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
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{ 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
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{ 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
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{ 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
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{ 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
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{ 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
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{ 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
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{1000, 0x05, 0x08, 0x20, 0x09, 0x30},
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{1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
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{1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
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{1500, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
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};
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static const
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struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5ghz[] = {
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{ 110000000, 0x02, 0x7f, 0x16, 0x02, 0x02},
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@ -372,6 +412,7 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
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u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
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u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
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unsigned int i;
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u32 val;
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timings = inno->pdata->inno_mipi_dphy_timing_table;
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@ -393,6 +434,23 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
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CLOCK_LANE_VOD_RANGE_SET_MASK,
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CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
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} else if (inno->pdata->max_rate == MAX_1_5GHZ) {
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
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LANE0_PRE_EMPHASIS_ENABLE_MASK, LANE0_PRE_EMPHASIS_ENABLE);
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x18,
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LANE1_PRE_EMPHASIS_ENABLE_MASK, LANE1_PRE_EMPHASIS_ENABLE);
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x19,
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PRE_EMPHASIS_RANGE_SET_MASK,
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PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1a,
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LANE0_PRE_EMPHASIS_RANGE_SET_MASK,
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LANE0_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1b,
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LANE1_PRE_EMPHASIS_RANGE_SET_MASK,
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LANE1_PRE_EMPHASIS_RANGE_SET(PRE_EMPHASIS_MID_RANGE));
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
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CLOCK_LANE_VOD_RANGE_SET_MASK,
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CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
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}
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/* Enable PLL and LDO */
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
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@ -518,10 +576,25 @@ static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
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T_TA_WAIT_CNT(ta_wait));
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}
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/* Enable all lanes on analog part */
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/* Enable lanes on analog part */
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switch (inno->pdata->max_lanes) {
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case 1:
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val = LANE_EN_0;
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break;
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case 2:
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val = LANE_EN_0 | LANE_EN_1;
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break;
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case 3:
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val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2;
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break;
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case 4:
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default:
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val = LANE_EN_0 | LANE_EN_1 | LANE_EN_2 | LANE_EN_3;
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break;
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}
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phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
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LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
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LANE_EN_1 | LANE_EN_0);
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LANE_EN_MASK, LANE_EN_CK | val);
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}
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static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
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@ -680,12 +753,21 @@ static const struct inno_video_phy_plat_data max_1ghz_video_phy_plat_data = {
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.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1ghz,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1ghz),
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.max_rate = MAX_1GHZ,
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.max_lanes = 4,
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};
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static const struct inno_video_phy_plat_data max_1_5ghz_video_phy_plat_data = {
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.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1_5ghz,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1_5ghz),
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.max_rate = MAX_1_5GHZ,
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.max_lanes = 2,
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};
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static const struct inno_video_phy_plat_data max_2_5ghz_video_phy_plat_data = {
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.inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5ghz,
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.num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5ghz),
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.max_rate = MAX_2_5GHZ,
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.max_lanes = 4,
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};
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static int inno_dsidphy_probe(struct platform_device *pdev)
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@ -767,6 +849,9 @@ static const struct of_device_id inno_dsidphy_of_match[] = {
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}, {
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.compatible = "rockchip,rk3368-dsi-dphy",
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.data = &max_1ghz_video_phy_plat_data,
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}, {
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.compatible = "rockchip,rk3506-dsi-dphy",
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.data = &max_1_5ghz_video_phy_plat_data,
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}, {
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.compatible = "rockchip,rk3568-dsi-dphy",
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.data = &max_2_5ghz_video_phy_plat_data,
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