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cxl: Clarify comment in spa_maps_hpa()

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Update the comment in spa_maps_hpa() to clearly convey the construction
of extended linear cache.

Suggested-by: Dan Williams <dan.j.williams@intel.com>
Link: https://lore.kernel.org/linux-cxl/68eea19c7e67e_2f899100a8@dwillia2-mobl4.notmuch/
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20251106170108.1468304-3-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
This commit is contained in:
Dave Jiang 2025-11-06 10:01:08 -07:00
parent c43521b9db
commit 8d27dd0b21
1 changed files with 3 additions and 3 deletions
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6
drivers/cxl/core/region.c
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@ -851,9 +851,9 @@ static bool spa_maps_hpa(const struct cxl_region_params *p,
return false;
/*
* If an extended linear cache region then the CXL range is assumed
* to be fronted by the DRAM range in current known implementation.
* This assumption will be made until a variant implementation exists.
* The extended linear cache region is constructed by a 1:1 ratio
* where the SPA maps equal amounts of DRAM and CXL HPA capacity with
* CXL decoders at the high end of the SPA range.
*/
return p->res->start + p->cache_size == range->start &&
p->res->end == range->end;