jsauer/torvalds-linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-01-12 01:20:14 +00:00
Code

arm64: dts: ti: k3-am69-sk: Add overlay for PCIE0 Endpoint Mode

Browse Source 
Add overlay to enable the PCIE0 instance of PCIe on AM69-SK in Endpoint
mode of operation.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20241205105041.749576-5-s-vadapalli@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Siddharth Vadapalli 2024-12-05 16:20:36 +05:30 committed by Nishanth Menon
parent 58efed5800
commit b09cc758bc
2 changed files with 57 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/ti/Makefile
View File

@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm.dtb
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-pcie0-pcie1-ep.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo
@ -198,6 +199,8 @@ k3-am68-sk-base-board-pcie1-ep-dtbs := k3-am68-sk-base-board.dtb \
k3-am68-sk-base-board-pcie1-ep.dtbo
k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \
k3-j721e-sk-csi2-dual-imx219.dtbo
k3-am69-sk-pcie0-ep-dtbs := k3-am69-sk.dtb \
k3-am69-sk-pcie0-ep.dtbo
k3-j7200-evm-pcie1-ep-dtbs := k3-j7200-common-proc-board.dtb \
k3-j7200-evm-pcie1-ep.dtbo
k3-j721e-common-proc-board-infotainment-dtbs := k3-j721e-common-proc-board.dtb \
@ -237,6 +240,7 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
k3-am68-sk-base-board-csi2-dual-imx219.dtb \
k3-am68-sk-base-board-pcie1-ep.dtb \
k3-am69-sk-csi2-dual-imx219.dtb \
k3-am69-sk-pcie0-ep.dtb \
k3-j7200-evm-pcie1-ep.dtb \
k3-j721e-common-proc-board-infotainment.dtb \
k3-j721e-evm-pcie0-ep.dtb \

53
arch/arm64/boot/dts/ti/k3-am69-sk-pcie0-ep.dtso Normal file
View File

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration
* on AM69-SK.
*
* AM69-SK Product Link: https://www.ti.com/tool/SK-AM69
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/ti,sci_pm_domain.h>
#include "k3-pinctrl.h"
/*
* Since Root Complex and Endpoint modes are mutually exclusive
* disable Root Complex mode.
*/
&pcie0_rc {
status = "disabled";
};
&cbass_main {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic500>;
pcie0_ep: pcie-ep@2900000 {
compatible = "ti,j784s4-pcie-ep";
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
<0x00 0x10000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 332 0>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
phys = <&serdes1_pcie_link>;
phy-names = "pcie-phy";
ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
};
};