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Merge branch 'icc-sdx75' into icc-next

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Drop the QPIC interconnect and BCM nodes for the SDX75 SoC. The reason
is that this QPIC BCM resource is already defined as a RPMh clock in
clk-rpmh driver as like other SDX SoCs. So it is wrong to describe the
same resource in two different providers.

Also, without this series, the NAND driver fails to probe on SDX75 as
the interconnect sync state disables the QPIC nodes as there were no
clients voting for this ICC resource. However, the NAND driver had already
voted for this BCM resource through the clk-rpmh driver. Since both votes
come from Linux, RPMh was unable to distinguish between these two and ends
up disabling the resource during sync state.

* icc-sdx75
  interconnect: qcom: sdx75: Drop QPIC interconnect and BCM nodes
  dt-bindings: interconnect: qcom: Drop QPIC_CORE IDs

Link: https://lore.kernel.org/r/20250926-sdx75-icc-v2-0-20d6820e455c@oss.qualcomm.com>
Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov 2025-10-31 03:05:45 +02:00
commit b4e8b0f2d1
3 changed files with 0 additions and 30 deletions
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26
drivers/interconnect/qcom/sdx75.c
View File

@ -16,15 +16,6 @@
#include "icc-rpmh.h"
#include "sdx75.h"
static struct qcom_icc_node qpic_core_master = {
.name = "qpic_core_master",
.id = SDX75_MASTER_QPIC_CORE,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SDX75_SLAVE_QPIC_CORE },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = SDX75_MASTER_QUP_CORE_0,
@ -375,14 +366,6 @@ static struct qcom_icc_node xm_usb3 = {
.links = { SDX75_SLAVE_A1NOC_CFG },
};
static struct qcom_icc_node qpic_core_slave = {
.name = "qpic_core_slave",
.id = SDX75_SLAVE_QPIC_CORE,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.id = SDX75_SLAVE_QUP_CORE_0,
@ -831,12 +814,6 @@ static struct qcom_icc_bcm bcm_mc0 = {
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_qp0 = {
.name = "QP0",
.num_nodes = 1,
.nodes = { &qpic_core_slave },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = true,
@ -898,14 +875,11 @@ static struct qcom_icc_bcm bcm_sn4 = {
};
static struct qcom_icc_bcm * const clk_virt_bcms[] = {
&bcm_qp0,
&bcm_qup0,
};
static struct qcom_icc_node * const clk_virt_nodes[] = {
[MASTER_QPIC_CORE] = &qpic_core_master,
[MASTER_QUP_CORE_0] = &qup0_core_master,
[SLAVE_QPIC_CORE] = &qpic_core_slave,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
};

2
drivers/interconnect/qcom/sdx75.h
View File

@ -33,7 +33,6 @@
#define SDX75_MASTER_QDSS_ETR 24
#define SDX75_MASTER_QDSS_ETR_1 25
#define SDX75_MASTER_QPIC 26
#define SDX75_MASTER_QPIC_CORE 27
#define SDX75_MASTER_QUP_0 28
#define SDX75_MASTER_QUP_CORE_0 29
#define SDX75_MASTER_SDCC_1 30
@ -76,7 +75,6 @@
#define SDX75_SLAVE_QDSS_CFG 67
#define SDX75_SLAVE_QDSS_STM 68
#define SDX75_SLAVE_QPIC 69
#define SDX75_SLAVE_QPIC_CORE 70
#define SDX75_SLAVE_QUP_0 71
#define SDX75_SLAVE_QUP_CORE_0 72
#define SDX75_SLAVE_SDCC_1 73

2
include/dt-bindings/interconnect/qcom,sdx75.h
View File

@ -6,9 +6,7 @@
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
#define MASTER_QPIC_CORE 0
#define MASTER_QUP_CORE_0 1
#define SLAVE_QPIC_CORE 2
#define SLAVE_QUP_CORE_0 3
#define MASTER_LLCC 0