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clk: renesas: cpg-mssr: Read back reset registers to assure values latched

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On R-Car V4H, the PCIEC controller DBI read would generate an SError in
case the controller reset is released by writing SRSTCLR register first,
and immediately afterward reading some PCIEC controller DBI register.
The issue triggers in rcar_gen4_pcie_additional_common_init() on
dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW), which on V4H is the first
read after reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc).

The reset controller which contains the SRSTCLR register and the PCIEC
controller which contains the DBI register share the same root access
bus, but the bus then splits into separate segments before reaching each
IP.  Even if the SRSTCLR write access was posted on the bus before the
DBI read access, it seems the DBI read access may reach the PCIEC
controller before the SRSTCLR write completed, and trigger the SError.

Mitigate the issue by adding a dummy SRSTCLR read, which assures the
SRSTCLR write completes fully and is latched into the reset controller,
before the PCIEC DBI read access can occur.

Fixes: 0ab55cf18341 ("clk: renesas: cpg-mssr: Add support for R-Car V4H")
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250922162113.113223-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Marek Vasut 2025-09-22 18:20:38 +02:00 committed by Geert Uytterhoeven
parent 62abfd7bed
commit b91401af6c
1 changed files with 21 additions and 25 deletions
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46
drivers/clk/renesas/renesas-cpg-mssr.c
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@ -676,18 +676,32 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
#define rcdev_to_priv(x) container_of(x, struct cpg_mssr_priv, rcdev)
static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
unsigned long id)
static int cpg_mssr_reset_operate(struct reset_controller_dev *rcdev,
const char *func, bool set, unsigned long id)
{
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
unsigned int reg = id / 32;
unsigned int bit = id % 32;
const u16 off = set ? priv->reset_regs[reg] : priv->reset_clear_regs[reg];
u32 bitmask = BIT(bit);
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
if (func)
dev_dbg(priv->dev, "%s %u%02u\n", func, reg, bit);
writel(bitmask, priv->pub.base0 + off);
readl(priv->pub.base0 + off);
barrier_data(priv->pub.base0 + off);
return 0;
}
static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
/* Reset module */
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
cpg_mssr_reset_operate(rcdev, "reset", true, id);
/*
* On R-Car Gen4, delay after SRCR has been written is 1ms.
@ -700,36 +714,18 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
usleep_range(35, 1000);
/* Release module from reset state */
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
return 0;
return cpg_mssr_reset_operate(rcdev, NULL, false, id);
}
static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
unsigned int reg = id / 32;
unsigned int bit = id % 32;
u32 bitmask = BIT(bit);
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
writel(bitmask, priv->pub.base0 + priv->reset_regs[reg]);
return 0;
return cpg_mssr_reset_operate(rcdev, "assert", true, id);
}
static int cpg_mssr_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct cpg_mssr_priv *priv = rcdev_to_priv(rcdev);
unsigned int reg = id / 32;
unsigned int bit = id % 32;
u32 bitmask = BIT(bit);
dev_dbg(priv->dev, "deassert %u%02u\n", reg, bit);
writel(bitmask, priv->pub.base0 + priv->reset_clear_regs[reg]);
return 0;
return cpg_mssr_reset_operate(rcdev, "deassert", false, id);
}
static int cpg_mssr_status(struct reset_controller_dev *rcdev,