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dt-bindings: pinctrl: Convert Marvell Berlin pinctrl to DT schema
Convert the Marvell/Synaptics Berlin pinctrl binding to DT schema format. The "reg" property was not documented for the newer SoCs. Otherwise, it's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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* Pin-controller driver for the Marvell Berlin SoCs
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Pin control registers are part of both chip controller and system
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controller register sets. Pin controller nodes should be a sub-node of
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either the chip controller or system controller node. The pins
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controlled are organized in groups, so no actual pin information is
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needed.
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A pin-controller node should contain subnodes representing the pin group
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configurations, one per function. Each subnode has the group name and
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the muxing function used.
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Be aware the Marvell Berlin datasheets use the keyword 'mode' for what
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is called a 'function' in the pin-controller subsystem.
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Required properties:
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- compatible: should be one of:
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"marvell,berlin2-soc-pinctrl",
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"marvell,berlin2-system-pinctrl",
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"marvell,berlin2cd-soc-pinctrl",
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"marvell,berlin2cd-system-pinctrl",
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"marvell,berlin2q-soc-pinctrl",
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"marvell,berlin2q-system-pinctrl",
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"marvell,berlin4ct-avio-pinctrl",
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"marvell,berlin4ct-soc-pinctrl",
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"marvell,berlin4ct-system-pinctrl",
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"syna,as370-soc-pinctrl"
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Required subnode-properties:
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- groups: a list of strings describing the group names.
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- function: a string describing the function used to mux the groups.
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Example:
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sys_pinctrl: pin-controller {
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compatible = "marvell,berlin2q-system-pinctrl";
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uart0_pmux: uart0-pmux {
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groups = "GSM12";
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function = "uart0";
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};
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};
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&uart0 {
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pinctrl-0 = <&uart0_pmux>;
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pinctrl-names = "default";
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};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/marvell,berlin2-soc-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Berlin pin-controller driver
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maintainers:
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- Antoine Tenart <atenart@kernel.org>
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- Jisheng Zhang <jszhang@kernel.org>
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description: >
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Pin control registers are part of both chip controller and system controller
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register sets. Pin controller nodes should be a sub-node of either the chip
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controller or system controller node. The pins controlled are organized in
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groups, so no actual pin information is needed.
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A pin-controller node should contain subnodes representing the pin group
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configurations, one per function. Each subnode has the group name and the
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muxing function used.
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Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is
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called a 'function' in the pin-controller subsystem.
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properties:
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compatible:
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items:
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- enum:
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- marvell,berlin2-soc-pinctrl
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- marvell,berlin2-system-pinctrl
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- marvell,berlin2cd-soc-pinctrl
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- marvell,berlin2cd-system-pinctrl
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- marvell,berlin2q-soc-pinctrl
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- marvell,berlin2q-system-pinctrl
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- marvell,berlin4ct-avio-pinctrl
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- marvell,berlin4ct-soc-pinctrl
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- marvell,berlin4ct-system-pinctrl
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- syna,as370-soc-pinctrl
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reg:
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maxItems: 1
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additionalProperties:
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description: Pin group configuration subnodes.
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type: object
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$ref: /schemas/pinctrl/pinmux-node.yaml#
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additionalProperties: false
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properties:
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groups:
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description: List of pin group names.
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$ref: /schemas/types.yaml#/definitions/string-array
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function:
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description: Function used to mux the group.
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$ref: /schemas/types.yaml#/definitions/string
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required:
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- groups
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- function
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- marvell,berlin4ct-avio-pinctrl
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- marvell,berlin4ct-soc-pinctrl
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- marvell,berlin4ct-system-pinctrl
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- syna,as370-soc-pinctrl
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then:
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required:
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- reg
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examples:
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- |
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pinctrl {
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compatible = "marvell,berlin2q-system-pinctrl";
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uart0-pmux {
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groups = "GSM12";
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function = "uart0";
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};
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};
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