mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-01-12 01:20:14 +00:00
Pin control bulk changes for v6.16:
Core changes:
- Add the devres devm_pinctrl_register_mappings() call that can
register some pin control machine mappings and have them go away
with the associated device.
New drivers:
- Support for the Mediatek MT6893 and MT8196 SoCs.
- Support for the Renesas RZ/V2N SoC.
- Support for the NXP Freescale i.MX943 SoC.
Improvements:
- Per-SoC suspend/resume callbacks in the Samsung drivers.
- Set all pins as input (High-Z) at probe in the MCP23S08 driver.
- Switch most GPIO chips to use the setters/getters with a return
value.
- EGPIO support in the Qualcomm QCM2290 driver.
- Fix up the number of available GPIO lines in Qualcomm QCS8300
and QCS615.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmg5xGcACgkQQRCzN7AZ
XXNuLQ/+LBL4VQXKXZxLkKlhhXpfJRmZx4W1h2VQt4PXj3Evhmk7aHFcPNiswWl2
rtXQEuEQcnReu8fO7wtA1d4a9QdA5ODniMmtwwNHJ0TTgcZsW1cj5ayZ5x1swRKN
+dTq336T1EEJ4KSQH6f3UIQaFyDGfL81zMei2qi63prEN7QCJ1zlJtJ3NWdoMzsK
INwzhHQPcSc0JskaMTYsYajkeaxXbA190hXAwI2msBuV/8YDjoGYWGvZIU7t3MbA
m+eFsCQJAmIgf9hK0qRBZHAWvN8XbOofnDtOUULxSi00Mh92GGTYrFmkHMIE3dRX
jtpD/kY4cWnlYYBzSo5/LmVvc2dAIvLHupqw+55fN4pG3i0fOHbjI1an160Oe61r
t3K/2fHSPZvKu1vLGedLePOBNG9AZQUjHEjiBQZd81KGRX4t4HcdQZvzd7l/5htK
J9HujqFcjT8xx/QarM2fxlFtOrAyHKljJgiBsmPtdL5zqJoQeUIXyofjGYUDgNfn
mqoT6+IwiJBEjEg6FVa3YXBhf8n2dmfzoxbITfhTeY/gsSvO24Po+9lK7NkpStyC
VHpoIxFtO9XsDrE9IC/8EpuVXB3rS5pWHBcYZeOcYCLkiSLqC7C4ZvJsZxPM8xMx
PTFzrjL+s1MxLCalE9XNA9wuZHXP8yRew67UymSsBm0yb9FDR/w=
=Qr9t
-----END PGP SIGNATURE-----
Merge tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"An especially linear and sparse improvement and new drivers release.
Nothing exciting. The biggest change in Bartosz changes to make
gpiochip set/get calls return error codes (something we should have
fixed ages ago but is now finally getting fixed.)
Core changes:
- Add the devres devm_pinctrl_register_mappings() call that can
register some pin control machine mappings and have them go away
with the associated device
New drivers:
- Support for the Mediatek MT6893 and MT8196 SoCs
- Support for the Renesas RZ/V2N SoC
- Support for the NXP Freescale i.MX943 SoC
Improvements:
- Per-SoC suspend/resume callbacks in the Samsung drivers
- Set all pins as input (High-Z) at probe in the MCP23S08 driver
- Switch most GPIO chips to use the setters/getters with a return
value
- EGPIO support in the Qualcomm QCM2290 driver
- Fix up the number of available GPIO lines in Qualcomm QCS8300 and
QCS615"
* tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
pinctrl: freescale: Add support for imx943 pinctrl
pinctrl: core: add devm_pinctrl_register_mappings()
pinctrl: remove extern specifier for functions in machine.h
pinctrl: mediatek: eint: Fix invalid pointer dereference for v1 platforms
pinctrl: freescale: Enable driver if platform is enabled.
pinctrl: freescale: Depend imx-scu driver on OF
pinctrl: armada-37xx: propagate error from armada_37xx_pmx_set_by_name()
pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get_direction()
pinctrl: armada-37xx: propagate error from armada_37xx_pmx_gpio_set_direction()
pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get()
pinctrl: armada-37xx: propagate error from armada_37xx_gpio_direction_output()
pinctrl: armada-37xx: set GPIO output value before setting direction
pinctrl: armada-37xx: use correct OUTPUT_VAL register for GPIOs > 31
pinctrl: meson: Drop unused aml_pctl_find_group_by_name()
pinctrl: at91: Fix possible out-of-boundary access
pinctrl: add stubs for OF-specific pinconf functions
pinctrl: qcom: correct the ngpios entry for QCS8300
pinctrl: qcom: correct the ngpios entry for QCS615
dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
...
This commit is contained in:
Linus Torvalds
commit
eafd95ea74
@ -14,7 +14,12 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: amlogic,pinctrl-a4
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oneOf:
|
||||
- const: amlogic,pinctrl-a4
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||||
- items:
|
||||
- enum:
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||||
- amlogic,pinctrl-a5
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- const: amlogic,pinctrl-a4
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"#address-cells":
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const: 2
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@ -0,0 +1,99 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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title: Freescale i.MX7ULP IOMUX Controller
|
||||
|
||||
description: |
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i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
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ports and IOMUXC DDR for DDR interface.
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||||
|
||||
Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it
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only supports generic pin config.
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Please refer to fsl,imx-pinctrl.txt in this directory for common binding
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part and usage.
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: fsl,imx7ulp-iomuxc1
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reg:
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maxItems: 1
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||||
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patternProperties:
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||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
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Client device subnodes use below standard properties.
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|
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properties:
|
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fsl,pins:
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description:
|
||||
Each entry consists of 5 integers which represents the mux
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and config setting for one pin. The first 4 integers
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<mux_conf_reg input_reg mux_mode input_val> are specified
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using a PIN_FUNC_ID macro, which can be found in
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imx7ulp-pinfunc.h in the device tree source folder.
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The last integer CONFIG is the pad setting value like
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pull-up on this pin.
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Please refer to i.MX7ULP Reference Manual for detailed
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CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
|
||||
"mux_conf_reg" indicates the offset of mux register.
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- description: |
|
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_mode" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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CONFIG bits definition:
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PAD_CTL_OBE (1 << 17)
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PAD_CTL_IBE (1 << 16)
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PAD_CTL_LK (1 << 16)
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PAD_CTL_DSE_HI (1 << 6)
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PAD_CTL_DSE_STD (0 << 6)
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PAD_CTL_ODE (1 << 5)
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PAD_CTL_PUSH_PULL (0 << 5)
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PAD_CTL_SRE_SLOW (1 << 2)
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PAD_CTL_SRE_STD (0 << 2)
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PAD_CTL_PE (1 << 0)
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required:
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- fsl,pins
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additionalProperties: false
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||||
|
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required:
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- compatible
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- reg
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allOf:
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- $ref: pinctrl.yaml#
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unevaluatedProperties: false
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examples:
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- |
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pinctrl@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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lpuart4grp {
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fsl,pins = <
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0x000c 0x0248 0x4 0x1 0x1
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0x0008 0x024c 0x4 0x1 0x1
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>;
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};
|
||||
};
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@ -1,53 +0,0 @@
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* Freescale i.MX7ULP IOMUX Controller
|
||||
|
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i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
|
||||
ports and IOMUXC DDR for DDR interface.
|
||||
|
||||
Note:
|
||||
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
|
||||
supports generic pin config.
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding
|
||||
part and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx7ulp-iomuxc1".
|
||||
- fsl,pins: Each entry consists of 5 integers which represents the mux
|
||||
and config setting for one pin. The first 4 integers
|
||||
<mux_conf_reg input_reg mux_mode input_val> are specified
|
||||
using a PIN_FUNC_ID macro, which can be found in
|
||||
imx7ulp-pinfunc.h in the device tree source folder.
|
||||
The last integer CONFIG is the pad setting value like
|
||||
pull-up on this pin.
|
||||
|
||||
Please refer to i.MX7ULP Reference Manual for detailed
|
||||
CONFIG settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_OBE (1 << 17)
|
||||
PAD_CTL_IBE (1 << 16)
|
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PAD_CTL_LK (1 << 16)
|
||||
PAD_CTL_DSE_HI (1 << 6)
|
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PAD_CTL_DSE_STD (0 << 6)
|
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PAD_CTL_ODE (1 << 5)
|
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PAD_CTL_PUSH_PULL (0 << 5)
|
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PAD_CTL_SRE_SLOW (1 << 2)
|
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PAD_CTL_SRE_STD (0 << 2)
|
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PAD_CTL_PE (1 << 0)
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Examples:
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#include "imx7ulp-pinfunc.h"
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/* Pin Controller Node */
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iomuxc1: pinctrl@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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||||
/* Pin Configuration Node */
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pinctrl_lpuart4: lpuart4grp {
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fsl,pins = <
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IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
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IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
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>;
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||||
};
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||||
};
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||||
@ -0,0 +1,83 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
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||||
title: Freescale Vybrid VF610 IOMUX Controller
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
maintainers:
|
||||
- Frank Li <Frank.Li@nxp.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,vf610-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
two integers array, represents a group of pins mux and config setting.
|
||||
The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a pin
|
||||
working on a specific function, CONFIG is the pad setting value such
|
||||
as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
|
||||
datasheet for the valid pad config settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description:
|
||||
PIN_FUN_ID refer to vf610-pinfunc.h in device tree source folder
|
||||
for all available PIN_FUNC_ID for Vybrid VF610.
|
||||
- description: |
|
||||
CONFIG bits definition is
|
||||
PAD_CTL_SPEED_LOW (1 << 12)
|
||||
PAD_CTL_SPEED_MED (2 << 12)
|
||||
PAD_CTL_SPEED_HIGH (3 << 12)
|
||||
PAD_CTL_SRE_FAST (1 << 11)
|
||||
PAD_CTL_SRE_SLOW (0 << 11)
|
||||
PAD_CTL_ODE (1 << 10)
|
||||
PAD_CTL_HYS (1 << 9)
|
||||
PAD_CTL_DSE_DISABLE (0 << 6)
|
||||
PAD_CTL_DSE_150ohm (1 << 6)
|
||||
PAD_CTL_DSE_75ohm (2 << 6)
|
||||
PAD_CTL_DSE_50ohm (3 << 6)
|
||||
PAD_CTL_DSE_37ohm (4 << 6)
|
||||
PAD_CTL_DSE_30ohm (5 << 6)
|
||||
PAD_CTL_DSE_25ohm (6 << 6)
|
||||
PAD_CTL_DSE_20ohm (7 << 6)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 4)
|
||||
PAD_CTL_PUS_47K_UP (1 << 4)
|
||||
PAD_CTL_PUS_100K_UP (2 << 4)
|
||||
PAD_CTL_PUS_22K_UP (3 << 4)
|
||||
PAD_CTL_PKE (1 << 3)
|
||||
PAD_CTL_PUE (1 << 2)
|
||||
PAD_CTL_OBE_ENABLE (1 << 1)
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PAD_CTL_IBE_ENABLE (1 << 0)
|
||||
PAD_CTL_OBE_IBE_ENABLE (3 << 0)
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
@ -1,41 +0,0 @@
|
||||
Freescale Vybrid VF610 IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,vf610-iomuxc"
|
||||
- fsl,pins: two integers array, represents a group of pins mux and config
|
||||
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
|
||||
a pin working on a specific function, CONFIG is the pad setting value
|
||||
such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
|
||||
datasheet for the valid pad config settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_SPEED_LOW (1 << 12)
|
||||
PAD_CTL_SPEED_MED (2 << 12)
|
||||
PAD_CTL_SPEED_HIGH (3 << 12)
|
||||
PAD_CTL_SRE_FAST (1 << 11)
|
||||
PAD_CTL_SRE_SLOW (0 << 11)
|
||||
PAD_CTL_ODE (1 << 10)
|
||||
PAD_CTL_HYS (1 << 9)
|
||||
PAD_CTL_DSE_DISABLE (0 << 6)
|
||||
PAD_CTL_DSE_150ohm (1 << 6)
|
||||
PAD_CTL_DSE_75ohm (2 << 6)
|
||||
PAD_CTL_DSE_50ohm (3 << 6)
|
||||
PAD_CTL_DSE_37ohm (4 << 6)
|
||||
PAD_CTL_DSE_30ohm (5 << 6)
|
||||
PAD_CTL_DSE_25ohm (6 << 6)
|
||||
PAD_CTL_DSE_20ohm (7 << 6)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 4)
|
||||
PAD_CTL_PUS_47K_UP (1 << 4)
|
||||
PAD_CTL_PUS_100K_UP (2 << 4)
|
||||
PAD_CTL_PUS_22K_UP (3 << 4)
|
||||
PAD_CTL_PKE (1 << 3)
|
||||
PAD_CTL_PUE (1 << 2)
|
||||
PAD_CTL_OBE_ENABLE (1 << 1)
|
||||
PAD_CTL_IBE_ENABLE (1 << 0)
|
||||
PAD_CTL_OBE_IBE_ENABLE (3 << 0)
|
||||
|
||||
Please refer to vf610-pinfunc.h in device tree source folder
|
||||
for all available PIN_FUNC_ID for Vybrid VF610.
|
||||
@ -136,75 +136,44 @@ examples:
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
syscfg_pctl_a: syscfg-pctl-a@10005000 {
|
||||
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
|
||||
reg = <0 0x10005000 0 0x1000>;
|
||||
};
|
||||
|
||||
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
|
||||
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
|
||||
reg = <0 0x1020C020 0 0x1000>;
|
||||
};
|
||||
|
||||
pinctrl@1c20800 {
|
||||
compatible = "mediatek,mt8135-pinctrl";
|
||||
reg = <0 0x1000B000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
compatible = "mediatek,mt8135-pinctrl";
|
||||
reg = <0 0x1000B000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
i2c0_pins_a: i2c0-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
|
||||
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
|
||||
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2_pins_a: i2c2-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
|
||||
bias-pull-down;
|
||||
i2c0_pins_a: i2c0-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
|
||||
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins_a: i2c3-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
|
||||
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
i2c1_pins_a: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
|
||||
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
|
||||
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
|
||||
output-low;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
||||
};
|
||||
i2c2_pins_a: i2c2-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pins3 {
|
||||
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
|
||||
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
|
||||
drive-strength = <32>;
|
||||
pins2 {
|
||||
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -245,9 +245,4 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mmc0 {
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,193 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek MT6893 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
|
||||
description:
|
||||
The MediaTek's MT6893 Pin controller is used to control SoC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt6893-pinctrl
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: pin controller base
|
||||
- description: rm group IO
|
||||
- description: bm group IO
|
||||
- description: lm group IO
|
||||
- description: lb group IO
|
||||
- description: rt group IO
|
||||
- description: lt group IO
|
||||
- description: tm group IO
|
||||
- description: External Interrupt (EINT) controller base
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: base
|
||||
- const: rm
|
||||
- const: bm
|
||||
- const: lm
|
||||
- const: lb
|
||||
- const: rt
|
||||
- const: lt
|
||||
- const: tm
|
||||
- const: eint
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description:
|
||||
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
|
||||
the amount of cells must be specified as 2. See the below mentioned gpio
|
||||
binding representation for description of particular cells.
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
gpio-line-names: true
|
||||
|
||||
interrupts:
|
||||
description: The interrupt outputs to sysirq
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
# PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'^pins':
|
||||
type: object
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
- $ref: /schemas/pinctrl/pinmux-node.yaml
|
||||
description:
|
||||
A pinctrl node should contain at least one subnodes representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input
|
||||
schmitt.
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description:
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux are defined as macros in
|
||||
arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
drive-strength-microamp:
|
||||
enum: [125, 250, 500, 1000]
|
||||
|
||||
bias-pull-down:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [75000, 5000]
|
||||
description: Pull down RSEL type resistance values (in ohms)
|
||||
description:
|
||||
For normal pull down type there is no need to specify a resistance
|
||||
value, hence this can be specified as a boolean property.
|
||||
For RSEL pull down type a resistance value (in ohms) can be added.
|
||||
|
||||
bias-pull-up:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [10000, 5000, 4000, 3000]
|
||||
description: Pull up RSEL type resistance values (in ohms)
|
||||
description:
|
||||
For normal pull up type there is no need to specify a resistance
|
||||
value, hence this can be specified as a boolean property.
|
||||
For RSEL pull up type a resistance value (in ohms) can be added.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
|
||||
#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
|
||||
#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt6893-pinctrl";
|
||||
reg = <0x10005000 0x1000>,
|
||||
<0x11c20000 0x0200>,
|
||||
<0x11d10000 0x0200>,
|
||||
<0x11e20000 0x0200>,
|
||||
<0x11e70000 0x0200>,
|
||||
<0x11ea0000 0x0200>,
|
||||
<0x11f20000 0x0200>,
|
||||
<0x11f30000 0x0200>,
|
||||
<0x1100b000 0x1000>;
|
||||
reg-names = "base", "rm", "bm", "lm", "lb", "rt",
|
||||
"lt", "tm", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 220>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
gpio-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
|
||||
bias-pull-up = <4000>;
|
||||
drive-strength = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0-pins {
|
||||
pins-bus {
|
||||
pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
|
||||
<PINMUX_GPIO100__FUNC_SDA0>;
|
||||
bias-pull-down = <75000>;
|
||||
drive-strength-microamp = <1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -366,34 +366,34 @@ examples:
|
||||
#size-cells = <2>;
|
||||
|
||||
pio: pinctrl@10211000 {
|
||||
compatible = "mediatek,mt7622-pinctrl";
|
||||
reg = <0 0x10211000 0 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
compatible = "mediatek,mt7622-pinctrl";
|
||||
reg = <0 0x10211000 0 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
pinctrl_eth_default: eth-pins {
|
||||
mux-mdio {
|
||||
groups = "mdc_mdio";
|
||||
function = "eth";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
pinctrl_eth_default: eth-pins {
|
||||
mux-mdio {
|
||||
groups = "mdc_mdio";
|
||||
function = "eth";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
mux-gmac2 {
|
||||
groups = "rgmii_via_gmac2";
|
||||
function = "eth";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
mux-gmac2 {
|
||||
groups = "rgmii_via_gmac2";
|
||||
function = "eth";
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
mux-esw {
|
||||
groups = "esw";
|
||||
function = "eth";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
mux-esw {
|
||||
groups = "esw";
|
||||
function = "eth";
|
||||
drive-strength = <8>;
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
pins = "MDC";
|
||||
bias-pull-up;
|
||||
conf-mdio {
|
||||
pins = "MDC";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -195,43 +195,43 @@ examples:
|
||||
#size-cells = <2>;
|
||||
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8183-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>,
|
||||
<0 0x11f20000 0 0x1000>,
|
||||
<0 0x11e80000 0 0x1000>,
|
||||
<0 0x11e70000 0 0x1000>,
|
||||
<0 0x11e90000 0 0x1000>,
|
||||
<0 0x11d30000 0 0x1000>,
|
||||
<0 0x11d20000 0 0x1000>,
|
||||
<0 0x11c50000 0 0x1000>,
|
||||
<0 0x11f30000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg1", "iocfg2",
|
||||
"iocfg3", "iocfg4", "iocfg5",
|
||||
"iocfg6", "iocfg7", "iocfg8",
|
||||
"eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 192>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "mediatek,mt8183-pinctrl";
|
||||
reg = <0 0x10005000 0 0x1000>,
|
||||
<0 0x11f20000 0 0x1000>,
|
||||
<0 0x11e80000 0 0x1000>,
|
||||
<0 0x11e70000 0 0x1000>,
|
||||
<0 0x11e90000 0 0x1000>,
|
||||
<0 0x11d30000 0 0x1000>,
|
||||
<0 0x11d20000 0 0x1000>,
|
||||
<0 0x11c50000 0 0x1000>,
|
||||
<0 0x11f30000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg1", "iocfg2",
|
||||
"iocfg3", "iocfg4", "iocfg5",
|
||||
"iocfg6", "iocfg7", "iocfg8",
|
||||
"eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 192>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
i2c0_pins_a: i2c0-pins {
|
||||
pins1 {
|
||||
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
|
||||
<PINMUX_GPIO49__FUNC_SDA5>;
|
||||
mediatek,pull-up-adv = <3>;
|
||||
drive-strength-microamp = <1000>;
|
||||
i2c0_pins_a: i2c0-pins {
|
||||
pins1 {
|
||||
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
|
||||
<PINMUX_GPIO49__FUNC_SDA5>;
|
||||
mediatek,pull-up-adv = <3>;
|
||||
drive-strength-microamp = <1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
|
||||
<PINMUX_GPIO51__FUNC_SDA3>;
|
||||
mediatek,pull-down-adv = <2>;
|
||||
i2c1_pins_a: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
|
||||
<PINMUX_GPIO51__FUNC_SDA3>;
|
||||
mediatek,pull-down-adv = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -142,43 +142,43 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8192-pinctrl";
|
||||
reg = <0x10005000 0x1000>,
|
||||
<0x11c20000 0x1000>,
|
||||
<0x11d10000 0x1000>,
|
||||
<0x11d30000 0x1000>,
|
||||
<0x11d40000 0x1000>,
|
||||
<0x11e20000 0x1000>,
|
||||
<0x11e70000 0x1000>,
|
||||
<0x11ea0000 0x1000>,
|
||||
<0x11f20000 0x1000>,
|
||||
<0x11f30000 0x1000>,
|
||||
<0x1000b000 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
|
||||
"iocfg_bl", "iocfg_br", "iocfg_lm",
|
||||
"iocfg_lb", "iocfg_rt", "iocfg_lt",
|
||||
"iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 220>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
pio: pinctrl@10005000 {
|
||||
compatible = "mediatek,mt8192-pinctrl";
|
||||
reg = <0x10005000 0x1000>,
|
||||
<0x11c20000 0x1000>,
|
||||
<0x11d10000 0x1000>,
|
||||
<0x11d30000 0x1000>,
|
||||
<0x11d40000 0x1000>,
|
||||
<0x11e20000 0x1000>,
|
||||
<0x11e70000 0x1000>,
|
||||
<0x11ea0000 0x1000>,
|
||||
<0x11f20000 0x1000>,
|
||||
<0x11f30000 0x1000>,
|
||||
<0x1000b000 0x1000>;
|
||||
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
|
||||
"iocfg_bl", "iocfg_br", "iocfg_lm",
|
||||
"iocfg_lb", "iocfg_rt", "iocfg_lt",
|
||||
"iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 220>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
spi1-default-pins {
|
||||
pins-cs-mosi-clk {
|
||||
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
|
||||
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
|
||||
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pins-miso {
|
||||
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
spi1-default-pins {
|
||||
pins-cs-mosi-clk {
|
||||
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
|
||||
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
|
||||
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pins-miso {
|
||||
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,236 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek MT8196 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Lei Xue <lei.xue@mediatek.com>
|
||||
- Cathy Xu <ot_cathy.xu@mediatek.com>
|
||||
|
||||
description:
|
||||
The MediaTek's MT8196 Pin controller is used to control SoC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8196-pinctrl
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: gpio base
|
||||
- description: rt group IO
|
||||
- description: rm1 group IO
|
||||
- description: rm2 group IO
|
||||
- description: rb group IO
|
||||
- description: bm1 group IO
|
||||
- description: bm2 group IO
|
||||
- description: bm3 group IO
|
||||
- description: lt group IO
|
||||
- description: lm1 group IO
|
||||
- description: lm2 group IO
|
||||
- description: lb1 group IO
|
||||
- description: lb2 group IO
|
||||
- description: tm1 group IO
|
||||
- description: tm2 group IO
|
||||
- description: tm3 group IO
|
||||
- description: eint0 group IO
|
||||
- description: eint1 group IO
|
||||
- description: eint2 group IO
|
||||
- description: eint3 group IO
|
||||
- description: eint4 group IO
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: base
|
||||
- const: rt
|
||||
- const: rm1
|
||||
- const: rm2
|
||||
- const: rb
|
||||
- const: bm1
|
||||
- const: bm2
|
||||
- const: bm3
|
||||
- const: lt
|
||||
- const: lm1
|
||||
- const: lm2
|
||||
- const: lb1
|
||||
- const: lb2
|
||||
- const: tm1
|
||||
- const: tm2
|
||||
- const: tm3
|
||||
- const: eint0
|
||||
- const: eint1
|
||||
- const: eint2
|
||||
- const: eint3
|
||||
- const: eint4
|
||||
|
||||
interrupts:
|
||||
description: The interrupt outputs to sysirq.
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
description:
|
||||
Number of cells in GPIO specifier, should be two. The first cell is the
|
||||
pin number, the second cell is used to specify optional parameters which
|
||||
are defined in <dt-bindings/gpio/gpio.h>.
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
gpio-line-names: true
|
||||
|
||||
# PIN CONFIGURATION NODES
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'^pins':
|
||||
type: object
|
||||
$ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
additionalProperties: false
|
||||
description:
|
||||
A pinctrl node should contain at least one subnode representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input
|
||||
schmitt.
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description:
|
||||
Integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are
|
||||
defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
|
||||
directly, for this SoC.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
bias-pull-down:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt8196 pull down PUPD/R0/R1 type define value.
|
||||
- enum: [75000, 5000]
|
||||
description: mt8196 pull down RSEL type si unit value(ohm).
|
||||
description: |
|
||||
For pull down type is normal, it doesn't need add R1R0 define
|
||||
and resistance value.
|
||||
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
|
||||
"MTK_PUPD_SET_R1R0_11" define in mt8196.
|
||||
For pull down type is PD/RSEL, it can add resistance value(ohm)
|
||||
to set different resistance by identifying property
|
||||
"mediatek,rsel-resistance-in-si-unit". It can support resistance
|
||||
value(ohm) "75000" & "5000" in mt8196.
|
||||
|
||||
bias-pull-up:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: mt8196 pull up PUPD/R0/R1 type define value.
|
||||
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
|
||||
description: mt8196 pull up RSEL type si unit value(ohm).
|
||||
description: |
|
||||
For pull up type is normal, it don't need add R1R0 define
|
||||
and resistance value.
|
||||
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
|
||||
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
|
||||
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
|
||||
"MTK_PUPD_SET_R1R0_11" define in mt8196.
|
||||
For pull up type is PU/RSEL, it can add resistance value(ohm)
|
||||
to set different resistance by identifying property
|
||||
"mediatek,rsel-resistance-in-si-unit". It can support resistance
|
||||
value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" &
|
||||
"75000" in mt8196.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
|
||||
#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
|
||||
|
||||
pio: pinctrl@1002d000 {
|
||||
compatible = "mediatek,mt8196-pinctrl";
|
||||
reg = <0x1002d000 0x1000>,
|
||||
<0x12000000 0x1000>,
|
||||
<0x12020000 0x1000>,
|
||||
<0x12040000 0x1000>,
|
||||
<0x12060000 0x1000>,
|
||||
<0x12820000 0x1000>,
|
||||
<0x12840000 0x1000>,
|
||||
<0x12860000 0x1000>,
|
||||
<0x13000000 0x1000>,
|
||||
<0x13020000 0x1000>,
|
||||
<0x13040000 0x1000>,
|
||||
<0x130f0000 0x1000>,
|
||||
<0x13110000 0x1000>,
|
||||
<0x13800000 0x1000>,
|
||||
<0x13820000 0x1000>,
|
||||
<0x13860000 0x1000>,
|
||||
<0x12080000 0x1000>,
|
||||
<0x12880000 0x1000>,
|
||||
<0x13080000 0x1000>,
|
||||
<0x13880000 0x1000>,
|
||||
<0x1c54a000 0x1000>;
|
||||
reg-names = "base", "rt", "rm1", "rm2", "rb" , "bm1",
|
||||
"bm2", "bm3", "lt", "lm1", "lm2", "lb1",
|
||||
"lb2", "tm1", "tm2", "tm3", "eint0", "eint1",
|
||||
"eint2", "eint3", "eint4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 271>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
i2c0-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
|
||||
<PINMUX_GPIO100__FUNC_SDA0>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -110,7 +110,7 @@ examples:
|
||||
<0x03c00000 0x300000>;
|
||||
reg-names = "east", "west", "south";
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-ranges = <&tlmm 0 0 123>;
|
||||
gpio-ranges = <&tlmm 0 0 124>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
@ -106,7 +106,7 @@ examples:
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 133>;
|
||||
gpio-ranges = <&tlmm 0 0 134>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
|
||||
@ -17,6 +17,19 @@ properties:
|
||||
items:
|
||||
- description: pinctrl io memory base
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Functional Clock
|
||||
- description: Bus Clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: func
|
||||
- const: bus
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
'-cfg$':
|
||||
type: object
|
||||
@ -94,6 +107,8 @@ patternProperties:
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@ -108,6 +123,9 @@ examples:
|
||||
pinctrl@d401e000 {
|
||||
compatible = "spacemit,k1-pinctrl";
|
||||
reg = <0x0 0xd401e000 0x0 0x400>;
|
||||
clocks = <&syscon_apbc 42>,
|
||||
<&syscon_apbc 94>;
|
||||
clock-names = "func", "bus";
|
||||
|
||||
uart0_2_cfg: uart0-2-cfg {
|
||||
uart0-2-pins {
|
||||
|
||||
@ -103,12 +103,10 @@ config PINCTRL_AS3722
|
||||
|
||||
config PINCTRL_AT91
|
||||
bool "AT91 pinctrl driver"
|
||||
depends on OF
|
||||
depends on ARCH_AT91
|
||||
depends on (OF && ARCH_AT91) || COMPILE_TEST
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GPIOLIB
|
||||
select OF_GPIO
|
||||
select GPIOLIB_IRQCHIP
|
||||
help
|
||||
Say Y here to enable the at91 pinctrl driver
|
||||
|
||||
@ -598,7 +598,7 @@ static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
return !!(val & BIT(offset));
|
||||
}
|
||||
|
||||
static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
static int owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
const struct owl_gpio_port *port;
|
||||
@ -607,13 +607,15 @@ static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
|
||||
port = owl_gpio_get_port(pctrl, &offset);
|
||||
if (WARN_ON(port == NULL))
|
||||
return;
|
||||
return -ENODEV;
|
||||
|
||||
gpio_base = pctrl->base + port->offset;
|
||||
|
||||
raw_spin_lock_irqsave(&pctrl->lock, flags);
|
||||
owl_gpio_update_reg(gpio_base + port->dat, offset, value);
|
||||
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
|
||||
@ -960,7 +962,7 @@ int owl_pinctrl_probe(struct platform_device *pdev,
|
||||
pctrl->chip.direction_input = owl_gpio_direction_input;
|
||||
pctrl->chip.direction_output = owl_gpio_direction_output;
|
||||
pctrl->chip.get = owl_gpio_get;
|
||||
pctrl->chip.set = owl_gpio_set;
|
||||
pctrl->chip.set_rv = owl_gpio_set;
|
||||
pctrl->chip.request = owl_gpio_request;
|
||||
pctrl->chip.free = owl_gpio_free;
|
||||
|
||||
|
||||
@ -356,11 +356,14 @@ static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offse
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int bcm2835_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
|
||||
|
||||
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
|
||||
@ -394,7 +397,7 @@ static const struct gpio_chip bcm2835_gpio_chip = {
|
||||
.direction_output = bcm2835_gpio_direction_output,
|
||||
.get_direction = bcm2835_gpio_get_direction,
|
||||
.get = bcm2835_gpio_get,
|
||||
.set = bcm2835_gpio_set,
|
||||
.set_rv = bcm2835_gpio_set,
|
||||
.set_config = gpiochip_generic_config,
|
||||
.base = -1,
|
||||
.ngpio = BCM2835_NUM_GPIOS,
|
||||
@ -411,7 +414,7 @@ static const struct gpio_chip bcm2711_gpio_chip = {
|
||||
.direction_output = bcm2835_gpio_direction_output,
|
||||
.get_direction = bcm2835_gpio_get_direction,
|
||||
.get = bcm2835_gpio_get,
|
||||
.set = bcm2835_gpio_set,
|
||||
.set_rv = bcm2835_gpio_set,
|
||||
.set_config = gpiochip_generic_config,
|
||||
.base = -1,
|
||||
.ngpio = BCM2711_NUM_GPIOS,
|
||||
|
||||
@ -390,7 +390,7 @@ static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
|
||||
static int iproc_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct iproc_gpio *chip = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
@ -400,6 +400,8 @@ static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
|
||||
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
|
||||
@ -863,7 +865,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
|
||||
gc->direction_input = iproc_gpio_direction_input;
|
||||
gc->direction_output = iproc_gpio_direction_output;
|
||||
gc->get_direction = iproc_gpio_get_direction;
|
||||
gc->set = iproc_gpio_set;
|
||||
gc->set_rv = iproc_gpio_set;
|
||||
gc->get = iproc_gpio_get;
|
||||
|
||||
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
|
||||
|
||||
@ -310,7 +310,7 @@ static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
|
||||
return !val;
|
||||
}
|
||||
|
||||
static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
|
||||
static int nsp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
|
||||
{
|
||||
struct nsp_gpio *chip = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
@ -320,6 +320,8 @@ static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
|
||||
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
||||
|
||||
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
|
||||
@ -654,7 +656,7 @@ static int nsp_gpio_probe(struct platform_device *pdev)
|
||||
gc->direction_input = nsp_gpio_direction_input;
|
||||
gc->direction_output = nsp_gpio_direction_output;
|
||||
gc->get_direction = nsp_gpio_get_direction;
|
||||
gc->set = nsp_gpio_set;
|
||||
gc->set_rv = nsp_gpio_set;
|
||||
gc->get = nsp_gpio_get;
|
||||
|
||||
/* optional GPIO interrupt support */
|
||||
|
||||
@ -1530,6 +1530,35 @@ void pinctrl_unregister_mappings(const struct pinctrl_map *map)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pinctrl_unregister_mappings);
|
||||
|
||||
static void devm_pinctrl_unregister_mappings(void *maps)
|
||||
{
|
||||
pinctrl_unregister_mappings(maps);
|
||||
}
|
||||
|
||||
/**
|
||||
* devm_pinctrl_register_mappings() - Resource managed pinctrl_register_mappings()
|
||||
* @dev: device for which mappings are registered
|
||||
* @maps: the pincontrol mappings table to register. Note the pinctrl-core
|
||||
* keeps a reference to the passed in maps, so they should _not_ be
|
||||
* marked with __initdata.
|
||||
* @num_maps: the number of maps in the mapping table
|
||||
*
|
||||
* Returns: 0 on success, or negative errno on failure.
|
||||
*/
|
||||
int devm_pinctrl_register_mappings(struct device *dev,
|
||||
const struct pinctrl_map *maps,
|
||||
unsigned int num_maps)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = pinctrl_register_mappings(maps, num_maps);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return devm_add_action_or_reset(dev, devm_pinctrl_unregister_mappings, (void *)maps);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(devm_pinctrl_register_mappings);
|
||||
|
||||
/**
|
||||
* pinctrl_force_sleep() - turn a given controller device into sleep state
|
||||
* @pctldev: pin controller device
|
||||
|
||||
@ -20,7 +20,9 @@ config PINCTRL_IMX_SCMI
|
||||
|
||||
config PINCTRL_IMX_SCU
|
||||
tristate
|
||||
depends on OF
|
||||
depends on IMX_SCU || COMPILE_TEST
|
||||
default IMX_SCU
|
||||
select PINCTRL_IMX
|
||||
|
||||
config PINCTRL_IMX1_CORE
|
||||
@ -159,6 +161,7 @@ config PINCTRL_IMX8MM
|
||||
tristate "IMX8MM pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX8M || COMPILE_TEST
|
||||
default SOC_IMX8M
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mm pinctrl driver
|
||||
@ -167,6 +170,7 @@ config PINCTRL_IMX8MN
|
||||
tristate "IMX8MN pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX8M || COMPILE_TEST
|
||||
default SOC_IMX8M
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mn pinctrl driver
|
||||
@ -175,6 +179,7 @@ config PINCTRL_IMX8MP
|
||||
tristate "IMX8MP pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX8M || COMPILE_TEST
|
||||
default SOC_IMX8M
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mp pinctrl driver
|
||||
@ -183,6 +188,7 @@ config PINCTRL_IMX8MQ
|
||||
tristate "IMX8MQ pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX8M || COMPILE_TEST
|
||||
default SOC_IMX8M
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8mq pinctrl driver
|
||||
@ -191,6 +197,7 @@ config PINCTRL_IMX8QM
|
||||
tristate "IMX8QM pinctrl driver"
|
||||
depends on OF
|
||||
depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST
|
||||
default ARCH_MXC
|
||||
select PINCTRL_IMX_SCU
|
||||
help
|
||||
Say Y here to enable the imx8qm pinctrl driver
|
||||
@ -199,6 +206,7 @@ config PINCTRL_IMX8QXP
|
||||
tristate "IMX8QXP pinctrl driver"
|
||||
depends on OF
|
||||
depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST
|
||||
default ARCH_MXC
|
||||
select PINCTRL_IMX_SCU
|
||||
help
|
||||
Say Y here to enable the imx8qxp pinctrl driver
|
||||
@ -207,6 +215,7 @@ config PINCTRL_IMX8DXL
|
||||
tristate "IMX8DXL pinctrl driver"
|
||||
depends on OF
|
||||
depends on (IMX_SCU && ARCH_MXC && ARM64) || COMPILE_TEST
|
||||
default ARCH_MXC
|
||||
select PINCTRL_IMX_SCU
|
||||
help
|
||||
Say Y here to enable the imx8dxl pinctrl driver
|
||||
@ -215,6 +224,7 @@ config PINCTRL_IMX8ULP
|
||||
tristate "IMX8ULP pinctrl driver"
|
||||
depends on OF
|
||||
depends on ARCH_MXC || COMPILE_TEST
|
||||
default ARCH_MXC
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx8ulp pinctrl driver
|
||||
@ -239,6 +249,7 @@ config PINCTRL_IMX93
|
||||
tristate "IMX93 pinctrl driver"
|
||||
depends on OF
|
||||
depends on ARCH_MXC || COMPILE_TEST
|
||||
default SOC_IMX9
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx93 pinctrl driver
|
||||
|
||||
@ -51,6 +51,7 @@ struct scmi_pinctrl_imx {
|
||||
#define IMX_SCMI_PIN_SIZE 24
|
||||
|
||||
#define IMX95_DAISY_OFF 0x408
|
||||
#define IMX94_DAISY_OFF 0x608
|
||||
|
||||
static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np,
|
||||
@ -70,6 +71,8 @@ static int pinctrl_scmi_imx_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
if (!daisy_off) {
|
||||
if (of_machine_is_compatible("fsl,imx95")) {
|
||||
daisy_off = IMX95_DAISY_OFF;
|
||||
} else if (of_machine_is_compatible("fsl,imx94")) {
|
||||
daisy_off = IMX94_DAISY_OFF;
|
||||
} else {
|
||||
dev_err(pctldev->dev, "platform not support scmi pinctrl\n");
|
||||
return -EINVAL;
|
||||
@ -289,6 +292,7 @@ scmi_pinctrl_imx_get_pins(struct scmi_pinctrl_imx *pmx, struct pinctrl_desc *des
|
||||
|
||||
static const char * const scmi_pinctrl_imx_allowlist[] = {
|
||||
"fsl,imx95",
|
||||
"fsl,imx94",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@ -181,6 +181,16 @@ config PINCTRL_MT6797
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT6893
|
||||
bool "MediaTek Dimensity MT6893 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
help
|
||||
Say yes here to support pin controller and gpio driver
|
||||
on the MediaTek Dimensity 1200 MT6893 Smartphone SoC.
|
||||
|
||||
config PINCTRL_MT7622
|
||||
bool "MediaTek MT7622 pin control"
|
||||
depends on OF
|
||||
@ -263,6 +273,18 @@ config PINCTRL_MT8195
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
|
||||
config PINCTRL_MT8196
|
||||
bool "MediaTek MT8196 pin control"
|
||||
depends on OF
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_PARIS
|
||||
help
|
||||
Say yes here to support pin controller and gpio driver
|
||||
on MediaTek MT8196 SoC.
|
||||
In MTK platform, we support virtual gpio and use it to
|
||||
map specific eint which doesn't have real gpio pin.
|
||||
|
||||
config PINCTRL_MT8365
|
||||
bool "MediaTek MT8365 pin control"
|
||||
depends on OF
|
||||
|
||||
@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o
|
||||
obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o
|
||||
obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o
|
||||
obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
|
||||
obj-$(CONFIG_PINCTRL_MT6893) += pinctrl-mt6893.o
|
||||
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
|
||||
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
|
||||
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
|
||||
@ -36,6 +37,7 @@ obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o
|
||||
obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o
|
||||
obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o
|
||||
obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o
|
||||
obj-$(CONFIG_PINCTRL_MT8196) += pinctrl-mt8196.o
|
||||
obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o
|
||||
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
|
||||
obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
|
||||
|
||||
@ -22,7 +22,6 @@
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "mtk-eint.h"
|
||||
#include "pinctrl-mtk-common-v2.h"
|
||||
|
||||
#define MTK_EINT_EDGE_SENSITIVE 0
|
||||
#define MTK_EINT_LEVEL_SENSITIVE 1
|
||||
@ -505,10 +504,9 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_eint_find_irq);
|
||||
|
||||
int mtk_eint_do_init(struct mtk_eint *eint)
|
||||
int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin)
|
||||
{
|
||||
unsigned int size, i, port, inst = 0;
|
||||
struct mtk_pinctrl *hw = (struct mtk_pinctrl *)eint->pctl;
|
||||
unsigned int size, i, port, virq, inst = 0;
|
||||
|
||||
/* If clients don't assign a specific regs, let's use generic one */
|
||||
if (!eint->regs)
|
||||
@ -519,7 +517,15 @@ int mtk_eint_do_init(struct mtk_eint *eint)
|
||||
if (!eint->base_pin_num)
|
||||
return -ENOMEM;
|
||||
|
||||
if (eint->nbase == 1) {
|
||||
if (eint_pin) {
|
||||
eint->pins = eint_pin;
|
||||
for (i = 0; i < eint->hw->ap_num; i++) {
|
||||
inst = eint->pins[i].instance;
|
||||
if (inst >= eint->nbase)
|
||||
continue;
|
||||
eint->base_pin_num[inst]++;
|
||||
}
|
||||
} else {
|
||||
size = eint->hw->ap_num * sizeof(struct mtk_eint_pin);
|
||||
eint->pins = devm_kmalloc(eint->dev, size, GFP_KERNEL);
|
||||
if (!eint->pins)
|
||||
@ -533,16 +539,6 @@ int mtk_eint_do_init(struct mtk_eint *eint)
|
||||
}
|
||||
}
|
||||
|
||||
if (hw && hw->soc && hw->soc->eint_pin) {
|
||||
eint->pins = hw->soc->eint_pin;
|
||||
for (i = 0; i < eint->hw->ap_num; i++) {
|
||||
inst = eint->pins[i].instance;
|
||||
if (inst >= eint->nbase)
|
||||
continue;
|
||||
eint->base_pin_num[inst]++;
|
||||
}
|
||||
}
|
||||
|
||||
eint->pin_list = devm_kmalloc(eint->dev, eint->nbase * sizeof(u16 *), GFP_KERNEL);
|
||||
if (!eint->pin_list)
|
||||
goto err_pin_list;
|
||||
@ -583,7 +579,7 @@ int mtk_eint_do_init(struct mtk_eint *eint)
|
||||
if (inst >= eint->nbase)
|
||||
continue;
|
||||
eint->pin_list[inst][eint->pins[i].index] = i;
|
||||
int virq = irq_create_mapping(eint->domain, i);
|
||||
virq = irq_create_mapping(eint->domain, i);
|
||||
irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
|
||||
handle_level_irq);
|
||||
irq_set_chip_data(virq, eint);
|
||||
@ -609,7 +605,7 @@ err_cur_mask:
|
||||
err_wake_mask:
|
||||
devm_kfree(eint->dev, eint->pin_list);
|
||||
err_pin_list:
|
||||
if (eint->nbase == 1)
|
||||
if (!eint_pin)
|
||||
devm_kfree(eint->dev, eint->pins);
|
||||
err_pins:
|
||||
devm_kfree(eint->dev, eint->base_pin_num);
|
||||
|
||||
@ -66,7 +66,7 @@ struct mtk_eint_xt {
|
||||
struct mtk_eint {
|
||||
struct device *dev;
|
||||
void __iomem **base;
|
||||
u8 nbase;
|
||||
int nbase;
|
||||
u16 *base_pin_num;
|
||||
struct irq_domain *domain;
|
||||
int irq;
|
||||
@ -88,7 +88,7 @@ struct mtk_eint {
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_EINT_MTK)
|
||||
int mtk_eint_do_init(struct mtk_eint *eint);
|
||||
int mtk_eint_do_init(struct mtk_eint *eint, struct mtk_eint_pin *eint_pin);
|
||||
int mtk_eint_do_suspend(struct mtk_eint *eint);
|
||||
int mtk_eint_do_resume(struct mtk_eint *eint);
|
||||
int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
|
||||
@ -96,7 +96,8 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_n,
|
||||
int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n);
|
||||
|
||||
#else
|
||||
static inline int mtk_eint_do_init(struct mtk_eint *eint)
|
||||
static inline int mtk_eint_do_init(struct mtk_eint *eint,
|
||||
struct mtk_eint_pin *eint_pin)
|
||||
{
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
@ -2247,15 +2247,16 @@ static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
|
||||
}
|
||||
|
||||
/* gpio callbacks */
|
||||
static void airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio,
|
||||
int value)
|
||||
static int airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio,
|
||||
int value)
|
||||
{
|
||||
struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
|
||||
u32 offset = gpio % AIROHA_PIN_BANK_SIZE;
|
||||
u8 index = gpio / AIROHA_PIN_BANK_SIZE;
|
||||
|
||||
regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.data[index],
|
||||
BIT(offset), value ? BIT(offset) : 0);
|
||||
return regmap_update_bits(pinctrl->regmap,
|
||||
pinctrl->gpiochip.data[index],
|
||||
BIT(offset), value ? BIT(offset) : 0);
|
||||
}
|
||||
|
||||
static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
||||
@ -2280,9 +2281,7 @@ static int airoha_gpio_direction_output(struct gpio_chip *chip,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
airoha_gpio_set(chip, gpio, value);
|
||||
|
||||
return 0;
|
||||
return airoha_gpio_set(chip, gpio, value);
|
||||
}
|
||||
|
||||
/* irq callbacks */
|
||||
@ -2419,7 +2418,7 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
|
||||
gc->free = gpiochip_generic_free;
|
||||
gc->direction_input = pinctrl_gpio_direction_input;
|
||||
gc->direction_output = airoha_gpio_direction_output;
|
||||
gc->set = airoha_gpio_set;
|
||||
gc->set_rv = airoha_gpio_set;
|
||||
gc->get = airoha_gpio_get;
|
||||
gc->base = -1;
|
||||
gc->ngpio = AIROHA_NUM_PINS;
|
||||
@ -2715,9 +2714,7 @@ static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev,
|
||||
if (pin < 0)
|
||||
return pin;
|
||||
|
||||
airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value);
|
||||
|
||||
return 0;
|
||||
return airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value);
|
||||
}
|
||||
|
||||
static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
|
||||
|
||||
@ -496,24 +496,26 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
||||
return !!value;
|
||||
}
|
||||
|
||||
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
static int mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
{
|
||||
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
||||
const struct mtk_pin_desc *desc;
|
||||
|
||||
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
||||
if (!desc->name) {
|
||||
dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
|
||||
return;
|
||||
}
|
||||
if (!desc->name)
|
||||
return -ENOTSUPP;
|
||||
|
||||
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
|
||||
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
|
||||
}
|
||||
|
||||
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
|
||||
int value)
|
||||
{
|
||||
mtk_gpio_set(chip, gpio, value);
|
||||
int ret;
|
||||
|
||||
ret = mtk_gpio_set(chip, gpio, value);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return pinctrl_gpio_direction_output(chip, gpio);
|
||||
}
|
||||
@ -567,7 +569,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
||||
chip->direction_input = pinctrl_gpio_direction_input;
|
||||
chip->direction_output = mtk_gpio_direction_output;
|
||||
chip->get = mtk_gpio_get;
|
||||
chip->set = mtk_gpio_set;
|
||||
chip->set_rv = mtk_gpio_set;
|
||||
chip->to_irq = mtk_gpio_to_irq;
|
||||
chip->set_config = mtk_gpio_set_config;
|
||||
chip->base = -1;
|
||||
|
||||
879
drivers/pinctrl/mediatek/pinctrl-mt6893.c
Normal file
879
drivers/pinctrl/mediatek/pinctrl-mt6893.c
Normal file
@ -0,0 +1,879 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019 MediaTek Inc.
|
||||
* Copyright (C) 2024 Collabora Ltd.
|
||||
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include "pinctrl-mtk-mt6893.h"
|
||||
#include "pinctrl-paris.h"
|
||||
|
||||
#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
|
||||
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
|
||||
32, 0)
|
||||
|
||||
#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
|
||||
PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \
|
||||
32, 1)
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_mode_range[] = {
|
||||
PIN_FIELD(0, 219, 0x0300, 0x10, 0, 4),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_dir_range[] = {
|
||||
PIN_FIELD(0, 219, 0x0000, 0x10, 0, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_di_range[] = {
|
||||
PIN_FIELD(0, 219, 0x0200, 0x10, 0, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_do_range[] = {
|
||||
PIN_FIELD(0, 219, 0x0100, 0x10, 0, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_smt_range[] = {
|
||||
PINS_FIELD_BASE(0, 9, 2, 0x00f0, 0x10, 7, 1),
|
||||
PINS_FIELD_BASE(10, 15, 1, 0x0090, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(16, 17, 5, 0x00c0, 0x10, 8, 1),
|
||||
PINS_FIELD_BASE(18, 25, 7, 0x00f0, 0x10, 1, 1),
|
||||
PINS_FIELD_BASE(26, 30, 6, 0x00e0, 0x10, 6, 1),
|
||||
PINS_FIELD_BASE(31, 35, 6, 0x00e0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(36, 36, 6, 0x00e0, 0x10, 16, 1),
|
||||
PINS_FIELD_BASE(37, 39, 6, 0x00e0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(40, 41, 6, 0x00e0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(42, 42, 6, 0x00e0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(43, 44, 6, 0x00e0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(45, 45, 6, 0x00e0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(46, 46, 6, 0x00e0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(47, 47, 6, 0x00e0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(48, 49, 6, 0x00e0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(50, 50, 6, 0x00e0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(51, 52, 3, 0x0090, 0x10, 6, 1),
|
||||
PINS_FIELD_BASE(53, 56, 3, 0x0090, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(57, 60, 3, 0x0090, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(61, 61, 3, 0x0090, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(62, 62, 4, 0x0050, 0x10, 1, 1),
|
||||
PINS_FIELD_BASE(63, 73, 3, 0x0090, 0x10, 0, 1),
|
||||
PINS_FIELD_BASE(74, 84, 4, 0x0050, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(85, 86, 4, 0x0050, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(87, 88, 4, 0x0050, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(89, 90, 2, 0x00f0, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(91, 91, 2, 0x00f0, 0x10, 0, 1),
|
||||
PINS_FIELD_BASE(92, 95, 2, 0x0100, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(96, 96, 2, 0x00f0, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(97, 97, 2, 0x00f0, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(98, 98, 2, 0x00f0, 0x10, 31, 1),
|
||||
PINS_FIELD_BASE(99, 102, 2, 0x00f0, 0x10, 29, 1),
|
||||
PINS_FIELD_BASE(103, 105, 2, 0x00f0, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(106, 106, 2, 0x00f0, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(107, 108, 2, 0x00f0, 0x10, 5, 1),
|
||||
PINS_FIELD_BASE(109, 113, 2, 0x00f0, 0x10, 8, 1),
|
||||
PINS_FIELD_BASE(114, 116, 2, 0x00f0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(117, 117, 2, 0x00f0, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x00f0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x00f0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x00f0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x00f0, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x00f0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x00f0, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x00f0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x00f0, 0x10, 21, 1),
|
||||
PINS_FIELD_BASE(126, 129, 2, 0x00f0, 0x10, 9, 1),
|
||||
PINS_FIELD_BASE(130, 135, 2, 0x00f0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(136, 138, 2, 0x00f0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x00f0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x00f0, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x00f0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x00f0, 0x10, 19, 1),
|
||||
PINS_FIELD_BASE(143, 148, 1, 0x0090, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(149, 151, 1, 0x0090, 0x10, 0, 1),
|
||||
PINS_FIELD_BASE(152, 155, 5, 0x00c0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(156, 156, 5, 0x00c0, 0x10, 14, 1),
|
||||
PINS_FIELD_BASE(157, 159, 5, 0x00c0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(160, 161, 5, 0x00c0, 0x10, 11, 1),
|
||||
PINS_FIELD_BASE(162, 171, 5, 0x00c0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(172, 173, 5, 0x00c0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(174, 174, 5, 0x00c0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(175, 175, 5, 0x00c0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(176, 177, 5, 0x00c0, 0x10, 1, 1),
|
||||
PINS_FIELD_BASE(178, 182, 5, 0x00c0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(183, 183, 7, 0x00f0, 0x10, 3, 1),
|
||||
PINS_FIELD_BASE(184, 190, 7, 0x00f0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(191, 191, 7, 0x00f0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(192, 192, 7, 0x00f0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(193, 193, 7, 0x00f0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(194, 194, 7, 0x00f0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(195, 195, 7, 0x00f0, 0x10, 12, 1),
|
||||
PINS_FIELD_BASE(196, 199, 7, 0x00f0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x00f0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x00f0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x00f0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x00f0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(204, 205, 6, 0x00e0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(206, 208, 7, 0x00f0, 0x10, 15, 1),
|
||||
PINS_FIELD_BASE(209, 211, 7, 0x00f0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(212, 213, 7, 0x00f0, 0x10, 8, 1),
|
||||
PINS_FIELD_BASE(214, 219, 7, 0x00f0, 0x10, 0, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_ies_range[] = {
|
||||
PIN_FIELD_BASE(0, 9, 2, 0x0060, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(10, 15, 1, 0x0020, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(16, 17, 5, 0x0030, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(18, 25, 7, 0x0050, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(26, 30, 6, 0x0040, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(32, 32, 6, 0x0040, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(33, 33, 6, 0x0040, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(34, 34, 6, 0x0040, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(35, 35, 6, 0x0040, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(36, 39, 6, 0x0040, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(40, 41, 6, 0x0040, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(42, 42, 6, 0x0040, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 44, 6, 0x0040, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(45, 45, 6, 0x0040, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(46, 46, 6, 0x0040, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(47, 47, 6, 0x0040, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(48, 49, 6, 0x0040, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(50, 50, 6, 0x0040, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(51, 52, 3, 0x0020, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x0020, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x0020, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(55, 55, 3, 0x0020, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(56, 56, 3, 0x0020, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(57, 60, 3, 0x0020, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(62, 62, 4, 0x0010, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(63, 64, 3, 0x0020, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(65, 72, 3, 0x0020, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(73, 73, 3, 0x0020, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(74, 84, 4, 0x0010, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(85, 86, 4, 0x0010, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(87, 88, 4, 0x0010, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(89, 90, 2, 0x0070, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(91, 91, 2, 0x0060, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(92, 92, 2, 0x0070, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(93, 93, 2, 0x0070, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(94, 94, 2, 0x0070, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(95, 95, 2, 0x0070, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(96, 96, 2, 0x0070, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(97, 97, 2, 0x0070, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(98, 98, 2, 0x0070, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(99, 102, 2, 0x0070, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(103, 103, 2, 0x0070, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(104, 104, 2, 0x0070, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(107, 108, 2, 0x0060, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(109, 109, 2, 0x0060, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(110, 110, 2, 0x0060, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(111, 111, 2, 0x0060, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(112, 112, 2, 0x0060, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(113, 113, 2, 0x0060, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(114, 114, 2, 0x0070, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x0060, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x0070, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x0070, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x0070, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x0070, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x0070, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x0070, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x0070, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(126, 129, 2, 0x0060, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(130, 132, 2, 0x0060, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(133, 135, 2, 0x0060, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(136, 138, 2, 0x0060, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x0070, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x0070, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x0070, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x0070, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(143, 145, 1, 0x0020, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(146, 148, 1, 0x0020, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(149, 151, 1, 0x0020, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(152, 152, 5, 0x0030, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(153, 153, 5, 0x0030, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(154, 155, 5, 0x0030, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(156, 158, 5, 0x0030, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(159, 159, 5, 0x0040, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(160, 161, 5, 0x0030, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(162, 171, 5, 0x0030, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(172, 173, 5, 0x0030, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(174, 174, 5, 0x0030, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(175, 175, 5, 0x0030, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(176, 177, 5, 0x0030, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(178, 182, 5, 0x0030, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(183, 184, 7, 0x0050, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(185, 185, 7, 0x0050, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(186, 186, 7, 0x0050, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(187, 187, 7, 0x0050, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(188, 188, 7, 0x0050, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(189, 189, 7, 0x0050, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(190, 191, 7, 0x0050, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(192, 192, 7, 0x0050, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(193, 193, 7, 0x0050, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(194, 194, 7, 0x0050, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(195, 195, 7, 0x0060, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(196, 196, 7, 0x0050, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(197, 197, 7, 0x0050, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(198, 198, 7, 0x0050, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(199, 199, 7, 0x0050, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x0060, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x0060, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x0060, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x0060, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(204, 205, 6, 0x0040, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(206, 208, 7, 0x0060, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(209, 209, 7, 0x0060, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(210, 210, 7, 0x0050, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(211, 211, 7, 0x0060, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(212, 212, 7, 0x0050, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(213, 213, 7, 0x0060, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(214, 214, 7, 0x0050, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(215, 215, 7, 0x0050, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(216, 217, 7, 0x0050, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(218, 219, 7, 0x0050, 0x10, 1, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_pu_range[] = {
|
||||
PIN_FIELD_BASE(0, 9, 2, 0x00a0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(16, 17, 5, 0x0070, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(18, 25, 7, 0x0090, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(26, 30, 6, 0x0080, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(32, 32, 6, 0x0080, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(33, 33, 6, 0x0080, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(34, 34, 6, 0x0080, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(35, 35, 6, 0x0080, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(36, 39, 6, 0x0080, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(40, 41, 6, 0x0080, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(42, 42, 6, 0x0080, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 44, 6, 0x0080, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(57, 60, 3, 0x0050, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(62, 62, 4, 0x0030, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(63, 64, 3, 0x0050, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(65, 72, 3, 0x0050, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(74, 84, 4, 0x0030, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(85, 86, 4, 0x0030, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(87, 88, 4, 0x0030, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(89, 90, 2, 0x00b0, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(91, 91, 2, 0x00a0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(92, 92, 2, 0x00b0, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(93, 93, 2, 0x00b0, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(94, 94, 2, 0x00b0, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(95, 95, 2, 0x00b0, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(96, 96, 2, 0x00b0, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(97, 97, 2, 0x00b0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(98, 98, 2, 0x00b0, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(99, 102, 2, 0x00b0, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(103, 103, 2, 0x00b0, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(104, 104, 2, 0x00b0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(105, 105, 2, 0x00b0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(106, 106, 2, 0x00b0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(107, 108, 2, 0x00a0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(109, 109, 2, 0x00a0, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(110, 110, 2, 0x00a0, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(111, 111, 2, 0x00a0, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(112, 112, 2, 0x00a0, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(113, 113, 2, 0x00a0, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(114, 114, 2, 0x00b0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(115, 115, 2, 0x00b0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(116, 116, 2, 0x00b0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(117, 117, 2, 0x00b0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x00a0, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x00b0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x00b0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x00b0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x00b0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x00b0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x00b0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x00b0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(126, 129, 2, 0x00a0, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(130, 132, 2, 0x00a0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(133, 135, 2, 0x00a0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(136, 138, 2, 0x00a0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x00b0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x00b0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x00b0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x00b0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(143, 145, 1, 0x0050, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(146, 148, 1, 0x0050, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(149, 151, 1, 0x0050, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(156, 159, 5, 0x0070, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(160, 161, 5, 0x0070, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(162, 171, 5, 0x0070, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(172, 173, 5, 0x0070, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(174, 174, 5, 0x0070, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(175, 175, 5, 0x0070, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(176, 177, 5, 0x0070, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(178, 182, 5, 0x0070, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(195, 195, 7, 0x0090, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(196, 196, 7, 0x0090, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(197, 197, 7, 0x0090, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(198, 198, 7, 0x0090, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(199, 199, 7, 0x0090, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x0090, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x0090, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x0090, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x0090, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(204, 205, 6, 0x0080, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(206, 208, 7, 0x0090, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(209, 209, 7, 0x0090, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(210, 210, 7, 0x0090, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(211, 211, 7, 0x0090, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(212, 212, 7, 0x0090, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(213, 213, 7, 0x0090, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(214, 214, 7, 0x0090, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(215, 215, 7, 0x0090, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(216, 217, 7, 0x0090, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(218, 219, 7, 0x0090, 0x10, 1, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_pd_range[] = {
|
||||
PIN_FIELD_BASE(0, 9, 2, 0x0080, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(16, 17, 5, 0x0050, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(18, 25, 7, 0x0070, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(26, 30, 6, 0x0060, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(31, 31, 6, 0x0060, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(32, 32, 6, 0x0060, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(33, 33, 6, 0x0060, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(34, 34, 6, 0x0060, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(35, 35, 6, 0x0060, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(36, 39, 6, 0x0060, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(40, 41, 6, 0x0060, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(42, 42, 6, 0x0060, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(43, 44, 6, 0x0060, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(57, 60, 3, 0x0030, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(62, 62, 4, 0x0020, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(63, 64, 3, 0x0030, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(65, 72, 3, 0x0030, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(74, 84, 4, 0x0020, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(85, 86, 4, 0x0020, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(87, 88, 4, 0x0020, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(89, 90, 2, 0x0090, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(91, 91, 2, 0x0080, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(92, 92, 2, 0x0090, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(93, 93, 2, 0x0090, 0x10, 30, 1),
|
||||
PIN_FIELD_BASE(94, 94, 2, 0x0090, 0x10, 29, 1),
|
||||
PIN_FIELD_BASE(95, 95, 2, 0x0090, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(99, 102, 2, 0x0090, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(103, 103, 2, 0x0090, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(104, 104, 2, 0x0090, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(107, 108, 2, 0x0080, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(109, 109, 2, 0x0080, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(110, 110, 2, 0x0080, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(111, 111, 2, 0x0080, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(112, 112, 2, 0x0080, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(113, 113, 2, 0x0080, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(114, 114, 2, 0x0090, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(115, 115, 2, 0x0090, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(116, 116, 2, 0x0090, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(117, 117, 2, 0x0090, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x0080, 0x10, 31, 1),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x0090, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x0090, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x0090, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x0090, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x0090, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x0090, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x0090, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(126, 129, 2, 0x0080, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(130, 132, 2, 0x0080, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(133, 135, 2, 0x0080, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(136, 138, 2, 0x0080, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x0090, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x0090, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(143, 145, 1, 0x0030, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(146, 148, 1, 0x0030, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(149, 151, 1, 0x0030, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(156, 159, 5, 0x0050, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(160, 161, 5, 0x0050, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(162, 171, 5, 0x0050, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(172, 173, 5, 0x0050, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(174, 174, 5, 0x0050, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(175, 175, 5, 0x0050, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(176, 177, 5, 0x0050, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(178, 182, 5, 0x0050, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(195, 195, 7, 0x0070, 0x10, 25, 1),
|
||||
PIN_FIELD_BASE(196, 196, 7, 0x0070, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(197, 197, 7, 0x0070, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(198, 198, 7, 0x0070, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(199, 199, 7, 0x0070, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x0070, 0x10, 24, 1),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x0070, 0x10, 27, 1),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x0070, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x0070, 0x10, 26, 1),
|
||||
PIN_FIELD_BASE(204, 205, 6, 0x0060, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(206, 208, 7, 0x0070, 0x10, 28, 1),
|
||||
PIN_FIELD_BASE(209, 209, 7, 0x0070, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(210, 210, 7, 0x0070, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(211, 211, 7, 0x0070, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(212, 212, 7, 0x0070, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(213, 213, 7, 0x0070, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(214, 214, 7, 0x0070, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(215, 215, 7, 0x0070, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(216, 217, 7, 0x0070, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(218, 219, 7, 0x0070, 0x10, 1, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_drv_range[] = {
|
||||
PINS_FIELD_BASE(0, 9, 2, 0x0000, 0x10, 21, 3),
|
||||
PINS_FIELD_BASE(10, 15, 1, 0x0000, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(16, 17, 5, 0x0000, 0x10, 18, 3),
|
||||
PINS_FIELD_BASE(18, 25, 7, 0x0000, 0x10, 3, 3),
|
||||
PINS_FIELD_BASE(26, 30, 6, 0x0000, 0x10, 15, 3),
|
||||
PINS_FIELD_BASE(31, 35, 6, 0x0000, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(36, 36, 6, 0x0010, 0x10, 7, 3),
|
||||
PINS_FIELD_BASE(37, 39, 6, 0x0010, 0x10, 4, 3),
|
||||
PIN_FIELD_BASE(40, 41, 6, 0x0000, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(42, 42, 6, 0x0000, 0x10, 12, 3),
|
||||
PINS_FIELD_BASE(43, 44, 6, 0x0000, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(45, 45, 6, 0x0000, 0x10, 30, 2),
|
||||
PIN_FIELD_BASE(46, 46, 6, 0x0010, 0x10, 2, 2),
|
||||
PIN_FIELD_BASE(47, 47, 6, 0x0010, 0x10, 0, 2),
|
||||
PIN_FIELD_BASE(48, 49, 6, 0x0000, 0x10, 26, 2),
|
||||
PIN_FIELD_BASE(50, 50, 6, 0x0000, 0x10, 24, 2),
|
||||
PIN_FIELD_BASE(51, 52, 3, 0x0000, 0x10, 18, 3),
|
||||
PINS_FIELD_BASE(53, 56, 3, 0x0000, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(57, 60, 3, 0x0000, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(62, 62, 4, 0x0000, 0x10, 3, 3),
|
||||
PINS_FIELD_BASE(63, 73, 3, 0x0000, 0x10, 0, 3),
|
||||
PINS_FIELD_BASE(74, 84, 4, 0x0000, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(85, 86, 4, 0x0000, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(87, 88, 4, 0x0000, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(89, 90, 2, 0x0020, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(91, 91, 2, 0x0000, 0x10, 0, 3),
|
||||
PINS_FIELD_BASE(92, 95, 2, 0x0030, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(96, 96, 2, 0x0020, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(97, 97, 2, 0x0020, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(98, 98, 2, 0x0030, 0x10, 0, 3),
|
||||
PINS_FIELD_BASE(99, 102, 2, 0x0020, 0x10, 24, 3),
|
||||
PINS_FIELD_BASE(103, 105, 2, 0x0020, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(106, 106, 2, 0x0020, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(107, 108, 2, 0x0000, 0x10, 15, 3),
|
||||
PINS_FIELD_BASE(109, 113, 2, 0x0000, 0x10, 24, 3),
|
||||
PINS_FIELD_BASE(114, 117, 2, 0x0010, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x0010, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x0010, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x0010, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x0020, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x0010, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x0020, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x0010, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x0020, 0x10, 0, 3),
|
||||
PINS_FIELD_BASE(126, 129, 2, 0x0000, 0x10, 27, 3),
|
||||
PINS_FIELD_BASE(130, 135, 2, 0x0000, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(136, 138, 2, 0x0000, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x0010, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x0010, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x0010, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x0010, 0x10, 24, 3),
|
||||
PINS_FIELD_BASE(143, 148, 1, 0x0000, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(149, 151, 1, 0x0000, 0x10, 0, 3),
|
||||
PINS_FIELD_BASE(152, 155, 5, 0x0000, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(156, 156, 5, 0x0010, 0x10, 6, 3),
|
||||
PINS_FIELD_BASE(157, 159, 5, 0x0010, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(160, 160, 5, 0x0000, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(161, 161, 5, 0x0010, 0x10, 0, 3),
|
||||
PINS_FIELD_BASE(162, 171, 5, 0x0000, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(172, 172, 5, 0x0000, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(173, 173, 5, 0x0000, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(174, 174, 5, 0x0000, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(175, 177, 5, 0x0000, 0x10, 3, 3),
|
||||
PINS_FIELD_BASE(178, 182, 5, 0x0000, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(183, 183, 7, 0x0000, 0x10, 9, 3),
|
||||
PINS_FIELD_BASE(184, 190, 7, 0x0000, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(191, 191, 7, 0x0000, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(192, 192, 7, 0x0000, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(193, 193, 7, 0x0000, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(194, 194, 7, 0x0000, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(195, 195, 7, 0x0010, 0x10, 3, 3),
|
||||
PINS_FIELD_BASE(196, 199, 7, 0x0000, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x0010, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x0010, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x0000, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x0010, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(204, 205, 6, 0x0000, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(206, 208, 7, 0x0010, 0x10, 12, 3),
|
||||
PINS_FIELD_BASE(209, 212, 7, 0x0000, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(213, 213, 7, 0x0000, 0x10, 24, 3),
|
||||
PINS_FIELD_BASE(214, 219, 7, 0x0000, 0x10, 0, 3),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_pupd_range[] = {
|
||||
PIN_FIELD_BASE(10, 15, 1, 0x0040, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(45, 45, 6, 0x0070, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(46, 46, 6, 0x0070, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(47, 47, 6, 0x0070, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(48, 49, 6, 0x0070, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(50, 50, 6, 0x0070, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(51, 52, 3, 0x0040, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(56, 56, 3, 0x0040, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(152, 152, 5, 0x0060, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(153, 153, 5, 0x0060, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(154, 155, 5, 0x0060, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(183, 184, 7, 0x0080, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(185, 185, 7, 0x0080, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(186, 186, 7, 0x0080, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(187, 187, 7, 0x0080, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(188, 188, 7, 0x0080, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(189, 189, 7, 0x0080, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(190, 191, 7, 0x0080, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(192, 192, 7, 0x0080, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(193, 193, 7, 0x0080, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(194, 194, 7, 0x0080, 0x10, 11, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_r0_range[] = {
|
||||
PIN_FIELD_BASE(10, 15, 1, 0x0060, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(24, 24, 7, 0x00e0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(25, 25, 7, 0x00e0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(45, 45, 6, 0x0090, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(46, 46, 6, 0x0090, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(47, 47, 6, 0x0090, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(48, 49, 6, 0x0090, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(50, 50, 6, 0x0090, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(51, 52, 3, 0x0060, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(56, 56, 3, 0x0060, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x00e0, 0x10, 12, 1),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x00e0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x00e0, 0x10, 22, 1),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x00e0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x00e0, 0x10, 20, 1),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x00e0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x00e0, 0x10, 18, 1),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x00e0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x00e0, 0x10, 16, 1),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x00e0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x00e0, 0x10, 14, 1),
|
||||
PIN_FIELD_BASE(152, 152, 5, 0x0080, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(153, 153, 5, 0x0080, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(154, 155, 5, 0x0080, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(160, 160, 5, 0x00b0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(161, 161, 5, 0x00b0, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(183, 184, 7, 0x00a0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(185, 185, 7, 0x00a0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(186, 186, 7, 0x00a0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(187, 187, 7, 0x00a0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(188, 188, 7, 0x00a0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(189, 189, 7, 0x00a0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(190, 191, 7, 0x00a0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(192, 192, 7, 0x00a0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(193, 193, 7, 0x00a0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(194, 194, 7, 0x00a0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x00e0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x00e0, 0x10, 10, 1),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x00e0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x00e0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(204, 204, 6, 0x00d0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(205, 205, 6, 0x00d0, 0x10, 2, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_r1_range[] = {
|
||||
PIN_FIELD_BASE(10, 15, 1, 0x0070, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(24, 24, 7, 0x00e0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(25, 25, 7, 0x00e0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(45, 45, 6, 0x00a0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(46, 46, 6, 0x00a0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(47, 47, 6, 0x00a0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(48, 49, 6, 0x00a0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(50, 50, 6, 0x00a0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(51, 52, 3, 0x0070, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(53, 53, 3, 0x0070, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(54, 54, 3, 0x0070, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(55, 55, 3, 0x0070, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(56, 56, 3, 0x0070, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x00e0, 0x10, 13, 1),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x00e0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x00e0, 0x10, 23, 1),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x00e0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x00e0, 0x10, 21, 1),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x00e0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x00e0, 0x10, 19, 1),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x00e0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x00e0, 0x10, 17, 1),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x00e0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x00e0, 0x10, 15, 1),
|
||||
PIN_FIELD_BASE(152, 152, 5, 0x0090, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(153, 153, 5, 0x0090, 0x10, 2, 1),
|
||||
PIN_FIELD_BASE(154, 155, 5, 0x0090, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(160, 160, 5, 0x00b0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(161, 161, 5, 0x00b0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(183, 184, 7, 0x00b0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(185, 185, 7, 0x00b0, 0x10, 4, 1),
|
||||
PIN_FIELD_BASE(186, 186, 7, 0x00b0, 0x10, 6, 1),
|
||||
PIN_FIELD_BASE(187, 187, 7, 0x00b0, 0x10, 8, 1),
|
||||
PIN_FIELD_BASE(188, 188, 7, 0x00b0, 0x10, 3, 1),
|
||||
PIN_FIELD_BASE(189, 189, 7, 0x00b0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(190, 191, 7, 0x00b0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(192, 192, 7, 0x00b0, 0x10, 0, 1),
|
||||
PIN_FIELD_BASE(193, 193, 7, 0x00b0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(194, 194, 7, 0x00b0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x00e0, 0x10, 7, 1),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x00e0, 0x10, 11, 1),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x00e0, 0x10, 5, 1),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x00e0, 0x10, 9, 1),
|
||||
PIN_FIELD_BASE(204, 204, 6, 0x00d0, 0x10, 1, 1),
|
||||
PIN_FIELD_BASE(205, 205, 6, 0x00d0, 0x10, 3, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_drv_adv_range[] = {
|
||||
PIN_FIELD_BASE(24, 24, 7, 0x0030, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(25, 25, 7, 0x0030, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 6, 5),
|
||||
PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 11, 5),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x0040, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x0040, 0x10, 18, 3),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x0040, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x0050, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x0040, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x0050, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x0040, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x0040, 0x10, 27, 3),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 24, 3),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x0040, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x0040, 0x10, 21, 3),
|
||||
PIN_FIELD_BASE(160, 160, 5, 0x0020, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(161, 161, 5, 0x0020, 0x10, 3, 3),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x0030, 0x10, 9, 3),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x0030, 0x10, 15, 3),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x0030, 0x10, 6, 3),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x0030, 0x10, 12, 3),
|
||||
PIN_FIELD_BASE(204, 204, 6, 0x0020, 0x10, 0, 3),
|
||||
PIN_FIELD_BASE(205, 205, 6, 0x0020, 0x10, 3, 3),
|
||||
};
|
||||
|
||||
static const struct mtk_pin_field_calc mt6893_pin_rsel_range[] = {
|
||||
PIN_FIELD_BASE(24, 24, 7, 0x00e0, 0x10, 0, 2),
|
||||
PIN_FIELD_BASE(25, 25, 7, 0x00e0, 0x10, 2, 2),
|
||||
PIN_FIELD_BASE(118, 118, 2, 0x00e0, 0x10, 0, 2),
|
||||
PIN_FIELD_BASE(119, 119, 2, 0x00e0, 0x10, 12, 2),
|
||||
PIN_FIELD_BASE(120, 120, 2, 0x00e0, 0x10, 10, 2),
|
||||
PIN_FIELD_BASE(121, 121, 2, 0x00e0, 0x10, 22, 2),
|
||||
PIN_FIELD_BASE(122, 122, 2, 0x00e0, 0x10, 8, 2),
|
||||
PIN_FIELD_BASE(123, 123, 2, 0x00e0, 0x10, 20, 2),
|
||||
PIN_FIELD_BASE(124, 124, 2, 0x00e0, 0x10, 6, 2),
|
||||
PIN_FIELD_BASE(125, 125, 2, 0x00e0, 0x10, 18, 2),
|
||||
PIN_FIELD_BASE(139, 139, 2, 0x00e0, 0x10, 4, 2),
|
||||
PIN_FIELD_BASE(140, 140, 2, 0x00e0, 0x10, 16, 2),
|
||||
PIN_FIELD_BASE(141, 141, 2, 0x00e0, 0x10, 2, 2),
|
||||
PIN_FIELD_BASE(142, 142, 2, 0x00e0, 0x10, 14, 2),
|
||||
PIN_FIELD_BASE(160, 160, 5, 0x00b0, 0x10, 0, 2),
|
||||
PIN_FIELD_BASE(161, 161, 5, 0x00b0, 0x10, 2, 2),
|
||||
PIN_FIELD_BASE(200, 200, 7, 0x00e0, 0x10, 6, 2),
|
||||
PIN_FIELD_BASE(201, 201, 7, 0x00e0, 0x10, 10, 2),
|
||||
PIN_FIELD_BASE(202, 202, 7, 0x00e0, 0x10, 4, 2),
|
||||
PIN_FIELD_BASE(203, 203, 7, 0x00e0, 0x10, 8, 2),
|
||||
PIN_FIELD_BASE(204, 204, 6, 0x00d0, 0x10, 0, 2),
|
||||
PIN_FIELD_BASE(205, 205, 6, 0x00d0, 0x10, 2, 2),
|
||||
};
|
||||
|
||||
static const unsigned int mt6893_pull_type[] = {
|
||||
MTK_PULL_PU_PD_TYPE, /* 0 */ MTK_PULL_PU_PD_TYPE, /* 1 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 2 */ MTK_PULL_PU_PD_TYPE, /* 3 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 4 */ MTK_PULL_PU_PD_TYPE, /* 5 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 6 */ MTK_PULL_PU_PD_TYPE, /* 7 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 8 */ MTK_PULL_PU_PD_TYPE, /* 9 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 10 */ MTK_PULL_PUPD_R1R0_TYPE, /* 11 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 12 */ MTK_PULL_PUPD_R1R0_TYPE, /* 13 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 14 */ MTK_PULL_PUPD_R1R0_TYPE, /* 15 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 16 */ MTK_PULL_PU_PD_TYPE, /* 17 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 18 */ MTK_PULL_PU_PD_TYPE, /* 19 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 20 */ MTK_PULL_PU_PD_TYPE, /* 21 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 22 */ MTK_PULL_PU_PD_TYPE, /* 23 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 24 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 25 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 26 */ MTK_PULL_PU_PD_TYPE, /* 27 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 28 */ MTK_PULL_PU_PD_TYPE, /* 29 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 30 */ MTK_PULL_PU_PD_TYPE, /* 31 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 32 */ MTK_PULL_PU_PD_TYPE, /* 33 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 34 */ MTK_PULL_PU_PD_TYPE, /* 35 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 36 */ MTK_PULL_PU_PD_TYPE, /* 37 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 38 */ MTK_PULL_PU_PD_TYPE, /* 39 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 40 */ MTK_PULL_PU_PD_TYPE, /* 41 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 42 */ MTK_PULL_PU_PD_TYPE, /* 43 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 44 */ MTK_PULL_PUPD_R1R0_TYPE, /* 45 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 46 */ MTK_PULL_PUPD_R1R0_TYPE, /* 47 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 48 */ MTK_PULL_PUPD_R1R0_TYPE, /* 49 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 50 */ MTK_PULL_PUPD_R1R0_TYPE, /* 51 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 52 */ MTK_PULL_PUPD_R1R0_TYPE, /* 53 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 54 */ MTK_PULL_PUPD_R1R0_TYPE, /* 55 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 56 */ MTK_PULL_PU_PD_TYPE, /* 57 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 58 */ MTK_PULL_PU_PD_TYPE, /* 59 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 60 */ MTK_PULL_PU_PD_TYPE, /* 61 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 62 */ MTK_PULL_PU_PD_TYPE, /* 63 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 64 */ MTK_PULL_PU_PD_TYPE, /* 65 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 66 */ MTK_PULL_PU_PD_TYPE, /* 67 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 68 */ MTK_PULL_PU_PD_TYPE, /* 69 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 70 */ MTK_PULL_PU_PD_TYPE, /* 71 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 72 */ MTK_PULL_PU_PD_TYPE, /* 73 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 74 */ MTK_PULL_PU_PD_TYPE, /* 75 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 76 */ MTK_PULL_PU_PD_TYPE, /* 77 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 78 */ MTK_PULL_PU_PD_TYPE, /* 79 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 80 */ MTK_PULL_PU_PD_TYPE, /* 81 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 82 */ MTK_PULL_PU_PD_TYPE, /* 83 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 84 */ MTK_PULL_PU_PD_TYPE, /* 85 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 86 */ MTK_PULL_PU_PD_TYPE, /* 87 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 88 */ MTK_PULL_PU_PD_TYPE, /* 89 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 90 */ MTK_PULL_PU_PD_TYPE, /* 91 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 92 */ MTK_PULL_PU_PD_TYPE, /* 93 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 94 */ MTK_PULL_PU_PD_TYPE, /* 95 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 96 */ MTK_PULL_PU_PD_TYPE, /* 97 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 98 */ MTK_PULL_PU_PD_TYPE, /* 99 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 100 */ MTK_PULL_PU_PD_TYPE, /* 101 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 102 */ MTK_PULL_PU_PD_TYPE, /* 103 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 104 */ MTK_PULL_PU_PD_TYPE, /* 105 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 106 */ MTK_PULL_PU_PD_TYPE, /* 107 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 108 */ MTK_PULL_PU_PD_TYPE, /* 109 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 110 */ MTK_PULL_PU_PD_TYPE, /* 111 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 112 */ MTK_PULL_PU_PD_TYPE, /* 113 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 114 */ MTK_PULL_PU_PD_TYPE, /* 115 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 116 */ MTK_PULL_PU_PD_TYPE, /* 117 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 118 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 119 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 120 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 121 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 122 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 123 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 124 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 125 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 126 */ MTK_PULL_PU_PD_TYPE, /* 127 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 128 */ MTK_PULL_PU_PD_TYPE, /* 129 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 130 */ MTK_PULL_PU_PD_TYPE, /* 131 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 132 */ MTK_PULL_PU_PD_TYPE, /* 133 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 134 */ MTK_PULL_PU_PD_TYPE, /* 135 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 136 */ MTK_PULL_PU_PD_TYPE, /* 137 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 138 */ MTK_PULL_PU_PD_TYPE, /* 139 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 140 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 141 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 142 */ MTK_PULL_PU_PD_TYPE, /* 143 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 144 */ MTK_PULL_PU_PD_TYPE, /* 145 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 146 */ MTK_PULL_PU_PD_TYPE, /* 147 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 148 */ MTK_PULL_PU_PD_TYPE, /* 149 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 150 */ MTK_PULL_PU_PD_TYPE, /* 151 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 152 */ MTK_PULL_PUPD_R1R0_TYPE, /* 153 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 154 */ MTK_PULL_PUPD_R1R0_TYPE, /* 155 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 156 */ MTK_PULL_PU_PD_TYPE, /* 157 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 158 */ MTK_PULL_PU_PD_TYPE, /* 159 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 160 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 161 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 162 */ MTK_PULL_PU_PD_TYPE, /* 163 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 164 */ MTK_PULL_PU_PD_TYPE, /* 165 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 166 */ MTK_PULL_PU_PD_TYPE, /* 167 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 168 */ MTK_PULL_PU_PD_TYPE, /* 169 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 170 */ MTK_PULL_PU_PD_TYPE, /* 171 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 172 */ MTK_PULL_PU_PD_TYPE, /* 173 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 174 */ MTK_PULL_PU_PD_TYPE, /* 175 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 176 */ MTK_PULL_PU_PD_TYPE, /* 177 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 178 */ MTK_PULL_PU_PD_TYPE, /* 179 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 180 */ MTK_PULL_PU_PD_TYPE, /* 181 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 182 */ MTK_PULL_PUPD_R1R0_TYPE, /* 183 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 184 */ MTK_PULL_PUPD_R1R0_TYPE, /* 185 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 186 */ MTK_PULL_PUPD_R1R0_TYPE, /* 187 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 188 */ MTK_PULL_PUPD_R1R0_TYPE, /* 189 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 190 */ MTK_PULL_PUPD_R1R0_TYPE, /* 191 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 192 */ MTK_PULL_PUPD_R1R0_TYPE, /* 193 */
|
||||
MTK_PULL_PUPD_R1R0_TYPE, /* 194 */ MTK_PULL_PU_PD_TYPE, /* 195 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 196 */ MTK_PULL_PU_PD_TYPE, /* 197 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 198 */ MTK_PULL_PU_PD_TYPE, /* 199 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 200 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 201 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 202 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 203 */
|
||||
MTK_PULL_PU_PD_RSEL_TYPE, /* 204 */ MTK_PULL_PU_PD_RSEL_TYPE, /* 205 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 206 */ MTK_PULL_PU_PD_TYPE, /* 207 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 208 */ MTK_PULL_PU_PD_TYPE, /* 209 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 210 */ MTK_PULL_PU_PD_TYPE, /* 211 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 212 */ MTK_PULL_PU_PD_TYPE, /* 213 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 214 */ MTK_PULL_PU_PD_TYPE, /* 215 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 216 */ MTK_PULL_PU_PD_TYPE, /* 217 */
|
||||
MTK_PULL_PU_PD_TYPE, /* 218 */ MTK_PULL_PU_PD_TYPE, /* 219 */
|
||||
};
|
||||
|
||||
static const char * const mt6893_pinctrl_register_base_name[] = {
|
||||
"base", "rm", "bm", "bl", "br", "lm", "lb", "rt", "lt", "tl",
|
||||
};
|
||||
|
||||
static const struct mtk_pin_reg_calc mt6893_reg_cals[PINCTRL_PIN_REG_MAX] = {
|
||||
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6893_pin_mode_range),
|
||||
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6893_pin_dir_range),
|
||||
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6893_pin_di_range),
|
||||
[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6893_pin_do_range),
|
||||
[PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6893_pin_dir_range),
|
||||
[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6893_pin_smt_range),
|
||||
[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6893_pin_ies_range),
|
||||
[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt6893_pin_pu_range),
|
||||
[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt6893_pin_pd_range),
|
||||
[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6893_pin_drv_range),
|
||||
[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt6893_pin_pupd_range),
|
||||
[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6893_pin_r0_range),
|
||||
[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt6893_pin_r1_range),
|
||||
[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt6893_pin_drv_adv_range),
|
||||
[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt6893_pin_rsel_range),
|
||||
};
|
||||
|
||||
static const struct mtk_eint_hw mt6893_eint_hw = {
|
||||
.port_mask = 7,
|
||||
.ports = 7,
|
||||
.ap_num = 224,
|
||||
.db_cnt = 32,
|
||||
.db_time = debounce_time_mt6765,
|
||||
};
|
||||
|
||||
static const struct mtk_pin_soc mt6893_data = {
|
||||
.reg_cal = mt6893_reg_cals,
|
||||
.pins = mtk_pins_mt6893,
|
||||
.npins = ARRAY_SIZE(mtk_pins_mt6893),
|
||||
.ngrps = ARRAY_SIZE(mtk_pins_mt6893),
|
||||
.eint_hw = &mt6893_eint_hw,
|
||||
.nfuncs = 8,
|
||||
.gpio_m = 0,
|
||||
.base_names = mt6893_pinctrl_register_base_name,
|
||||
.nbase_names = ARRAY_SIZE(mt6893_pinctrl_register_base_name),
|
||||
.pull_type = mt6893_pull_type,
|
||||
.bias_set_combo = mtk_pinconf_bias_set_combo,
|
||||
.bias_get_combo = mtk_pinconf_bias_get_combo,
|
||||
.drive_set = mtk_pinconf_drive_set_rev1,
|
||||
.drive_get = mtk_pinconf_drive_get_rev1,
|
||||
.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
|
||||
.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
|
||||
};
|
||||
|
||||
static const struct of_device_id mt6893_pinctrl_of_match[] = {
|
||||
{ .compatible = "mediatek,mt6893-pinctrl", .data = &mt6893_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static struct platform_driver mt6893_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "mt6893-pinctrl",
|
||||
.of_match_table = mt6893_pinctrl_of_match,
|
||||
.pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops)
|
||||
},
|
||||
.probe = mtk_paris_pinctrl_probe,
|
||||
};
|
||||
|
||||
static int __init mt6893_pinctrl_init(void)
|
||||
{
|
||||
return platform_driver_register(&mt6893_pinctrl_driver);
|
||||
}
|
||||
|
||||
arch_initcall(mt6893_pinctrl_init);
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek MT6893 Pinctrl Driver");
|
||||
1860
drivers/pinctrl/mediatek/pinctrl-mt8196.c
Normal file
1860
drivers/pinctrl/mediatek/pinctrl-mt8196.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -381,10 +381,13 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
count_reg_names = of_property_count_strings(np, "reg-names");
|
||||
if (count_reg_names < hw->soc->nbase_names)
|
||||
if (count_reg_names < 0)
|
||||
return -EINVAL;
|
||||
|
||||
hw->eint->nbase = count_reg_names - (int)hw->soc->nbase_names;
|
||||
if (hw->eint->nbase <= 0)
|
||||
return -EINVAL;
|
||||
|
||||
hw->eint->nbase = count_reg_names - hw->soc->nbase_names;
|
||||
hw->eint->base = devm_kmalloc_array(&pdev->dev, hw->eint->nbase,
|
||||
sizeof(*hw->eint->base), GFP_KERNEL | __GFP_ZERO);
|
||||
if (!hw->eint->base) {
|
||||
@ -416,7 +419,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
|
||||
hw->eint->pctl = hw;
|
||||
hw->eint->gpio_xlate = &mtk_eint_xt;
|
||||
|
||||
ret = mtk_eint_do_init(hw->eint);
|
||||
ret = mtk_eint_do_init(hw->eint, hw->soc->eint_pin);
|
||||
if (ret)
|
||||
goto err_free_eint;
|
||||
|
||||
|
||||
@ -86,7 +86,7 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int mtk_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
unsigned int reg_addr;
|
||||
unsigned int bit;
|
||||
@ -100,7 +100,7 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
else
|
||||
reg_addr = CLR_ADDR(reg_addr, pctl);
|
||||
|
||||
regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
|
||||
return regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
|
||||
}
|
||||
|
||||
static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
|
||||
@ -809,7 +809,12 @@ static const struct pinmux_ops mtk_pmx_ops = {
|
||||
static int mtk_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int value)
|
||||
{
|
||||
mtk_gpio_set(chip, offset, value);
|
||||
int ret;
|
||||
|
||||
ret = mtk_gpio_set(chip, offset, value);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return pinctrl_gpio_direction_output(chip, offset);
|
||||
}
|
||||
|
||||
@ -893,7 +898,7 @@ static const struct gpio_chip mtk_gpio_chip = {
|
||||
.direction_input = pinctrl_gpio_direction_input,
|
||||
.direction_output = mtk_gpio_direction_output,
|
||||
.get = mtk_gpio_get,
|
||||
.set = mtk_gpio_set,
|
||||
.set_rv = mtk_gpio_set,
|
||||
.to_irq = mtk_gpio_to_irq,
|
||||
.set_config = mtk_gpio_set_config,
|
||||
};
|
||||
@ -1039,7 +1044,7 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev)
|
||||
pctl->eint->pctl = pctl;
|
||||
pctl->eint->gpio_xlate = &mtk_eint_xt;
|
||||
|
||||
return mtk_eint_do_init(pctl->eint);
|
||||
return mtk_eint_do_init(pctl->eint, NULL);
|
||||
}
|
||||
|
||||
/* This is used as a common probe function */
|
||||
|
||||
2283
drivers/pinctrl/mediatek/pinctrl-mtk-mt6893.h
Normal file
2283
drivers/pinctrl/mediatek/pinctrl-mtk-mt6893.h
Normal file
File diff suppressed because it is too large
Load Diff
3085
drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h
Normal file
3085
drivers/pinctrl/mediatek/pinctrl-mtk-mt8196.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -840,9 +840,6 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
|
||||
const struct mtk_pin_desc *desc;
|
||||
int value, err;
|
||||
|
||||
if (gpio >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* "Virtual" GPIOs are always and only used for interrupts
|
||||
* Since they are only used for interrupts, they are always inputs
|
||||
@ -868,9 +865,6 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
||||
const struct mtk_pin_desc *desc;
|
||||
int value, err;
|
||||
|
||||
if (gpio >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
||||
|
||||
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
|
||||
@ -880,38 +874,29 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
||||
return !!value;
|
||||
}
|
||||
|
||||
static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
static int mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
{
|
||||
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
||||
const struct mtk_pin_desc *desc;
|
||||
|
||||
if (gpio >= hw->soc->npins)
|
||||
return;
|
||||
|
||||
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
|
||||
|
||||
mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
|
||||
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
|
||||
}
|
||||
|
||||
static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
|
||||
{
|
||||
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
||||
|
||||
if (gpio >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
return pinctrl_gpio_direction_input(chip, gpio);
|
||||
}
|
||||
|
||||
static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
|
||||
int value)
|
||||
{
|
||||
struct mtk_pinctrl *hw = gpiochip_get_data(chip);
|
||||
int ret;
|
||||
|
||||
if (gpio >= hw->soc->npins)
|
||||
return -EINVAL;
|
||||
|
||||
mtk_gpio_set(chip, gpio, value);
|
||||
ret = mtk_gpio_set(chip, gpio, value);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return pinctrl_gpio_direction_output(chip, gpio);
|
||||
}
|
||||
@ -964,7 +949,7 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
||||
chip->direction_input = mtk_gpio_direction_input;
|
||||
chip->direction_output = mtk_gpio_direction_output;
|
||||
chip->get = mtk_gpio_get;
|
||||
chip->set = mtk_gpio_set;
|
||||
chip->set_rv = mtk_gpio_set;
|
||||
chip->to_irq = mtk_gpio_to_irq;
|
||||
chip->set_config = mtk_gpio_set_config;
|
||||
chip->base = -1;
|
||||
|
||||
@ -3,7 +3,7 @@ menuconfig PINCTRL_MESON
|
||||
tristate "Amlogic SoC pinctrl drivers"
|
||||
depends on ARCH_MESON || COMPILE_TEST
|
||||
depends on OF
|
||||
default y
|
||||
default ARCH_MESON
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
@ -17,25 +17,25 @@ config PINCTRL_MESON8
|
||||
bool "Meson 8 SoC pinctrl driver"
|
||||
depends on ARM
|
||||
select PINCTRL_MESON8_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON8B
|
||||
bool "Meson 8b SoC pinctrl driver"
|
||||
depends on ARM
|
||||
select PINCTRL_MESON8_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON_GXBB
|
||||
tristate "Meson gxbb SoC pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON8_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON_GXL
|
||||
tristate "Meson gxl SoC pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON8_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON8_PMX
|
||||
tristate
|
||||
@ -44,7 +44,7 @@ config PINCTRL_MESON_AXG
|
||||
tristate "Meson axg Soc pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON_AXG_PMX
|
||||
tristate
|
||||
@ -53,24 +53,24 @@ config PINCTRL_MESON_G12A
|
||||
tristate "Meson g12a Soc pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON_A1
|
||||
tristate "Meson a1 Soc pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_MESON_S4
|
||||
tristate "Meson s4 Soc pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_AMLOGIC_A4
|
||||
bool "AMLOGIC pincontrol"
|
||||
depends on ARM64
|
||||
default y
|
||||
default ARCH_MESON
|
||||
help
|
||||
This is the driver for the pin controller found on Amlogic SoCs.
|
||||
|
||||
@ -82,12 +82,12 @@ config PINCTRL_AMLOGIC_C3
|
||||
tristate "Amlogic C3 SoC pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
config PINCTRL_AMLOGIC_T7
|
||||
tristate "Amlogic T7 SoC pinctrl driver"
|
||||
depends on ARM64
|
||||
select PINCTRL_MESON_AXG_PMX
|
||||
default y
|
||||
default ARCH_MESON
|
||||
|
||||
endif
|
||||
|
||||
@ -596,20 +596,6 @@ static int aml_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline const struct aml_pctl_group *
|
||||
aml_pctl_find_group_by_name(const struct aml_pinctrl *info,
|
||||
const char *name)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < info->ngroups; i++) {
|
||||
if (!strcmp(info->groups[i].name, name))
|
||||
return &info->groups[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
|
||||
unsigned int offset)
|
||||
{
|
||||
@ -806,15 +792,15 @@ static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
|
||||
value ? BIT(bit) : 0);
|
||||
}
|
||||
|
||||
static void aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
{
|
||||
struct aml_gpio_bank *bank = gpiochip_get_data(chip);
|
||||
unsigned int bit, reg;
|
||||
|
||||
aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, ®, &bit);
|
||||
|
||||
regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
|
||||
value ? BIT(bit) : 0);
|
||||
return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
|
||||
value ? BIT(bit) : 0);
|
||||
}
|
||||
|
||||
static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio)
|
||||
@ -832,7 +818,7 @@ static const struct gpio_chip aml_gpio_template = {
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.set_config = gpiochip_generic_config,
|
||||
.set = aml_gpio_set,
|
||||
.set_rv = aml_gpio_set,
|
||||
.get = aml_gpio_get,
|
||||
.direction_input = aml_gpio_direction_input,
|
||||
.direction_output = aml_gpio_direction_output,
|
||||
|
||||
@ -580,9 +580,9 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
|
||||
gpio, value);
|
||||
}
|
||||
|
||||
static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
|
||||
static int meson_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
|
||||
{
|
||||
meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
|
||||
return meson_pinconf_set_drive(gpiochip_get_data(chip), gpio, value);
|
||||
}
|
||||
|
||||
static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
|
||||
@ -616,7 +616,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc)
|
||||
pc->chip.direction_input = meson_gpio_direction_input;
|
||||
pc->chip.direction_output = meson_gpio_direction_output;
|
||||
pc->chip.get = meson_gpio_get;
|
||||
pc->chip.set = meson_gpio_set;
|
||||
pc->chip.set_rv = meson_gpio_set;
|
||||
pc->chip.base = -1;
|
||||
pc->chip.ngpio = pc->data->num_pins;
|
||||
pc->chip.can_sleep = false;
|
||||
|
||||
@ -358,9 +358,7 @@ static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
|
||||
|
||||
val = grp->val[func];
|
||||
|
||||
regmap_update_bits(info->regmap, reg, mask, val);
|
||||
|
||||
return 0;
|
||||
return regmap_update_bits(info->regmap, reg, mask, val);
|
||||
}
|
||||
|
||||
static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
|
||||
@ -402,10 +400,13 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
|
||||
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int reg = OUTPUT_EN;
|
||||
unsigned int val, mask;
|
||||
int ret;
|
||||
|
||||
armada_37xx_update_reg(®, &offset);
|
||||
mask = BIT(offset);
|
||||
regmap_read(info->regmap, reg, &val);
|
||||
ret = regmap_read(info->regmap, reg, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (val & mask)
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
@ -417,22 +418,22 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int reg = OUTPUT_EN;
|
||||
unsigned int en_offset = offset;
|
||||
unsigned int reg = OUTPUT_VAL;
|
||||
unsigned int mask, val, ret;
|
||||
|
||||
armada_37xx_update_reg(®, &offset);
|
||||
mask = BIT(offset);
|
||||
val = value ? mask : 0;
|
||||
|
||||
ret = regmap_update_bits(info->regmap, reg, mask, mask);
|
||||
|
||||
ret = regmap_update_bits(info->regmap, reg, mask, val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
reg = OUTPUT_VAL;
|
||||
val = value ? mask : 0;
|
||||
regmap_update_bits(info->regmap, reg, mask, val);
|
||||
reg = OUTPUT_EN;
|
||||
armada_37xx_update_reg(®, &en_offset);
|
||||
|
||||
return 0;
|
||||
return regmap_update_bits(info->regmap, reg, mask, mask);
|
||||
}
|
||||
|
||||
static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
@ -440,17 +441,20 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int reg = INPUT_VAL;
|
||||
unsigned int val, mask;
|
||||
int ret;
|
||||
|
||||
armada_37xx_update_reg(®, &offset);
|
||||
mask = BIT(offset);
|
||||
|
||||
regmap_read(info->regmap, reg, &val);
|
||||
ret = regmap_read(info->regmap, reg, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return (val & mask) != 0;
|
||||
}
|
||||
|
||||
static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
static int armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
|
||||
unsigned int reg = OUTPUT_VAL;
|
||||
@ -460,7 +464,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
mask = BIT(offset);
|
||||
val = value ? mask : 0;
|
||||
|
||||
regmap_update_bits(info->regmap, reg, mask, val);
|
||||
return regmap_update_bits(info->regmap, reg, mask, val);
|
||||
}
|
||||
|
||||
static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
@ -469,16 +473,17 @@ static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
{
|
||||
struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct gpio_chip *chip = range->gc;
|
||||
int ret;
|
||||
|
||||
dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
|
||||
offset, range->name, offset, input ? "input" : "output");
|
||||
|
||||
if (input)
|
||||
armada_37xx_gpio_direction_input(chip, offset);
|
||||
ret = armada_37xx_gpio_direction_input(chip, offset);
|
||||
else
|
||||
armada_37xx_gpio_direction_output(chip, offset, 0);
|
||||
ret = armada_37xx_gpio_direction_output(chip, offset, 0);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||
@ -513,7 +518,7 @@ static const struct pinmux_ops armada_37xx_pmx_ops = {
|
||||
static const struct gpio_chip armada_37xx_gpiolib_chip = {
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.set = armada_37xx_gpio_set,
|
||||
.set_rv = armada_37xx_gpio_set,
|
||||
.get = armada_37xx_gpio_get,
|
||||
.get_direction = armada_37xx_gpio_get_direction,
|
||||
.direction_input = armada_37xx_gpio_direction_input,
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
if ARCH_U8500
|
||||
if (ARCH_U8500 || COMPILE_TEST)
|
||||
|
||||
config PINCTRL_ABX500
|
||||
bool "ST-Ericsson ABx500 family Mixed Signal Circuit gpio functions"
|
||||
@ -10,11 +10,11 @@ config PINCTRL_ABX500
|
||||
|
||||
config PINCTRL_AB8500
|
||||
bool "AB8500 pin controller driver"
|
||||
depends on PINCTRL_ABX500 && ARCH_U8500
|
||||
depends on PINCTRL_ABX500 && (ARCH_U8500 || COMPILE_TEST)
|
||||
|
||||
config PINCTRL_AB8505
|
||||
bool "AB8505 pin controller driver"
|
||||
depends on PINCTRL_ABX500 && ARCH_U8500
|
||||
depends on PINCTRL_ABX500 && (ARCH_U8500 || COMPILE_TEST)
|
||||
|
||||
endif
|
||||
|
||||
|
||||
@ -167,14 +167,10 @@ out:
|
||||
return bit;
|
||||
}
|
||||
|
||||
static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
|
||||
static int abx500_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int val)
|
||||
{
|
||||
struct abx500_pinctrl *pct = gpiochip_get_data(chip);
|
||||
int ret;
|
||||
|
||||
ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
|
||||
if (ret < 0)
|
||||
dev_err(pct->dev, "%s write failed (%d)\n", __func__, ret);
|
||||
return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
|
||||
}
|
||||
|
||||
static int abx500_gpio_direction_output(struct gpio_chip *chip,
|
||||
@ -540,7 +536,7 @@ static const struct gpio_chip abx500gpio_chip = {
|
||||
.direction_input = abx500_gpio_direction_input,
|
||||
.get = abx500_gpio_get,
|
||||
.direction_output = abx500_gpio_direction_output,
|
||||
.set = abx500_gpio_set,
|
||||
.set_rv = abx500_gpio_set,
|
||||
.to_irq = abx500_gpio_to_irq,
|
||||
.dbg_show = abx500_gpio_dbg_show,
|
||||
};
|
||||
|
||||
@ -142,4 +142,21 @@ int pinconf_generic_parse_dt_config(struct device_node *np,
|
||||
int pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev,
|
||||
unsigned int **pid, unsigned int **pmux,
|
||||
unsigned int *npins);
|
||||
#else
|
||||
static inline int
|
||||
pinconf_generic_parse_dt_config(struct device_node *np,
|
||||
struct pinctrl_dev *pctldev,
|
||||
unsigned long **configs,
|
||||
unsigned int *nconfigs)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static inline int
|
||||
pinconf_generic_parse_dt_pinmux(struct device_node *np, struct device *dev,
|
||||
unsigned int **pid, unsigned int **pmux,
|
||||
unsigned int *npins)
|
||||
{
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -105,7 +105,8 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
|
||||
return !!(pin_reg & BIT(PIN_STS_OFF));
|
||||
}
|
||||
|
||||
static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
|
||||
static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
u32 pin_reg;
|
||||
unsigned long flags;
|
||||
@ -119,6 +120,8 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
|
||||
pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
|
||||
writel(pin_reg, gpio_dev->base + offset * 4);
|
||||
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
|
||||
@ -1173,7 +1176,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
|
||||
gpio_dev->gc.direction_input = amd_gpio_direction_input;
|
||||
gpio_dev->gc.direction_output = amd_gpio_direction_output;
|
||||
gpio_dev->gc.get = amd_gpio_get_value;
|
||||
gpio_dev->gc.set = amd_gpio_set_value;
|
||||
gpio_dev->gc.set_rv = amd_gpio_set_value;
|
||||
gpio_dev->gc.set_config = amd_gpio_set_config;
|
||||
gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
|
||||
|
||||
|
||||
@ -66,7 +66,7 @@ struct apple_gpio_pinctrl {
|
||||
#define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
|
||||
#define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
|
||||
|
||||
struct regmap_config regmap_config = {
|
||||
static const struct regmap_config regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
@ -79,13 +79,13 @@ struct regmap_config regmap_config = {
|
||||
|
||||
/* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
|
||||
static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
|
||||
unsigned int pin, u32 mask, u32 value)
|
||||
unsigned int pin, u32 mask, u32 value)
|
||||
{
|
||||
regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
|
||||
}
|
||||
|
||||
static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
|
||||
unsigned int pin)
|
||||
unsigned int pin)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
@ -100,9 +100,9 @@ static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
|
||||
/* Pin controller functions */
|
||||
|
||||
static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *node,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *num_maps)
|
||||
struct device_node *node,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
unsigned reserved_maps;
|
||||
struct apple_gpio_pinctrl *pctl;
|
||||
@ -147,8 +147,8 @@ static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
group_name = pinctrl_generic_get_group_name(pctldev, pin);
|
||||
function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
|
||||
ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
|
||||
&reserved_maps, num_maps,
|
||||
group_name, function_name);
|
||||
&reserved_maps, num_maps,
|
||||
group_name, function_name);
|
||||
if (ret)
|
||||
goto free_map;
|
||||
}
|
||||
@ -171,7 +171,7 @@ static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
|
||||
/* Pin multiplexer functions */
|
||||
|
||||
static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
|
||||
unsigned group)
|
||||
unsigned group)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
@ -237,7 +237,7 @@ static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offse
|
||||
}
|
||||
|
||||
static int apple_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
@ -282,7 +282,7 @@ static void apple_gpio_irq_mask(struct irq_data *data)
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
|
||||
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
|
||||
FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
|
||||
gpiochip_disable_irq(gc, data->hwirq);
|
||||
}
|
||||
|
||||
@ -294,7 +294,7 @@ static void apple_gpio_irq_unmask(struct irq_data *data)
|
||||
|
||||
gpiochip_enable_irq(gc, data->hwirq);
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
}
|
||||
|
||||
static unsigned int apple_gpio_irq_startup(struct irq_data *data)
|
||||
@ -303,7 +303,7 @@ static unsigned int apple_gpio_irq_startup(struct irq_data *data)
|
||||
struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
|
||||
FIELD_PREP(REG_GPIOx_GRP, 0));
|
||||
FIELD_PREP(REG_GPIOx_GRP, 0));
|
||||
|
||||
apple_gpio_direction_input(chip, data->hwirq);
|
||||
apple_gpio_irq_unmask(data);
|
||||
@ -320,7 +320,7 @@ static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
|
||||
return -EINVAL;
|
||||
|
||||
apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
FIELD_PREP(REG_GPIOx_MODE, irqtype));
|
||||
|
||||
if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(data, handle_level_irq);
|
||||
@ -429,7 +429,7 @@ static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
|
||||
unsigned int npins;
|
||||
const char **pin_names;
|
||||
unsigned int *pin_nums;
|
||||
static const char* pinmux_functions[] = {
|
||||
static const char *pinmux_functions[] = {
|
||||
"gpio", "periph1", "periph2", "periph3"
|
||||
};
|
||||
unsigned int i, nirqs = 0;
|
||||
|
||||
@ -390,7 +390,7 @@ static int atmel_gpio_direction_output(struct gpio_chip *chip,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
|
||||
static int atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
|
||||
{
|
||||
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
|
||||
struct atmel_pin *pin = atmel_pioctrl->pins[offset];
|
||||
@ -398,10 +398,12 @@ static void atmel_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
|
||||
atmel_gpio_write(atmel_pioctrl, pin->bank,
|
||||
val ? ATMEL_PIO_SODR : ATMEL_PIO_CODR,
|
||||
BIT(pin->line));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
|
||||
unsigned long *bits)
|
||||
static int atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
|
||||
unsigned long *bits)
|
||||
{
|
||||
struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
|
||||
unsigned int bank;
|
||||
@ -431,6 +433,8 @@ static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
|
||||
bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct gpio_chip atmel_gpio_chip = {
|
||||
@ -438,8 +442,8 @@ static struct gpio_chip atmel_gpio_chip = {
|
||||
.get = atmel_gpio_get,
|
||||
.get_multiple = atmel_gpio_get_multiple,
|
||||
.direction_output = atmel_gpio_direction_output,
|
||||
.set = atmel_gpio_set,
|
||||
.set_multiple = atmel_gpio_set_multiple,
|
||||
.set_rv = atmel_gpio_set,
|
||||
.set_multiple_rv = atmel_gpio_set_multiple,
|
||||
.to_irq = atmel_gpio_to_irq,
|
||||
.base = 0,
|
||||
};
|
||||
@ -609,8 +613,10 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
|
||||
ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps, num_maps,
|
||||
group, func);
|
||||
if (ret)
|
||||
goto exit;
|
||||
|
||||
if (num_configs) {
|
||||
ret = pinctrl_utils_add_map_configs(pctldev, map,
|
||||
|
||||
@ -1449,18 +1449,19 @@ static int at91_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
return (pdsr & mask) != 0;
|
||||
}
|
||||
|
||||
static void at91_gpio_set(struct gpio_chip *chip, unsigned offset,
|
||||
int val)
|
||||
static int at91_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
|
||||
{
|
||||
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
|
||||
void __iomem *pio = at91_gpio->regbase;
|
||||
unsigned mask = 1 << offset;
|
||||
|
||||
writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void at91_gpio_set_multiple(struct gpio_chip *chip,
|
||||
unsigned long *mask, unsigned long *bits)
|
||||
static int at91_gpio_set_multiple(struct gpio_chip *chip,
|
||||
unsigned long *mask, unsigned long *bits)
|
||||
{
|
||||
struct at91_gpio_chip *at91_gpio = gpiochip_get_data(chip);
|
||||
void __iomem *pio = at91_gpio->regbase;
|
||||
@ -1472,6 +1473,8 @@ static void at91_gpio_set_multiple(struct gpio_chip *chip,
|
||||
|
||||
writel_relaxed(set_mask, pio + PIO_SODR);
|
||||
writel_relaxed(clear_mask, pio + PIO_CODR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int at91_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
|
||||
@ -1798,8 +1801,8 @@ static const struct gpio_chip at91_gpio_template = {
|
||||
.direction_input = at91_gpio_direction_input,
|
||||
.get = at91_gpio_get,
|
||||
.direction_output = at91_gpio_direction_output,
|
||||
.set = at91_gpio_set,
|
||||
.set_multiple = at91_gpio_set_multiple,
|
||||
.set_rv = at91_gpio_set,
|
||||
.set_multiple_rv = at91_gpio_set_multiple,
|
||||
.dbg_show = at91_gpio_dbg_show,
|
||||
.can_sleep = false,
|
||||
.ngpio = MAX_NB_GPIO_PER_BANK,
|
||||
@ -1819,12 +1822,16 @@ static int at91_gpio_probe(struct platform_device *pdev)
|
||||
struct at91_gpio_chip *at91_chip = NULL;
|
||||
struct gpio_chip *chip;
|
||||
struct pinctrl_gpio_range *range;
|
||||
int alias_idx;
|
||||
int ret = 0;
|
||||
int irq, i;
|
||||
int alias_idx = of_alias_get_id(np, "gpio");
|
||||
uint32_t ngpio;
|
||||
char **names;
|
||||
|
||||
alias_idx = of_alias_get_id(np, "gpio");
|
||||
if (alias_idx < 0)
|
||||
return alias_idx;
|
||||
|
||||
BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
|
||||
if (gpio_chips[alias_idx])
|
||||
return dev_err_probe(dev, -EBUSY, "%d slot is occupied.\n", alias_idx);
|
||||
|
||||
@ -192,34 +192,30 @@ static int axp20x_gpio_get_direction(struct gpio_chip *chip,
|
||||
static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
chip->set(chip, offset, value);
|
||||
|
||||
return 0;
|
||||
return chip->set_rv(chip, offset, value);
|
||||
}
|
||||
|
||||
static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
static int axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct axp20x_pctl *pctl = gpiochip_get_data(chip);
|
||||
int reg;
|
||||
|
||||
/* AXP209 has GPIO3 status sharing the settings register */
|
||||
if (offset == 3) {
|
||||
regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
|
||||
AXP20X_GPIO3_FUNCTIONS,
|
||||
value ? AXP20X_GPIO3_FUNCTION_OUT_HIGH :
|
||||
AXP20X_GPIO3_FUNCTION_OUT_LOW);
|
||||
return;
|
||||
}
|
||||
if (offset == 3)
|
||||
return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
|
||||
AXP20X_GPIO3_FUNCTIONS,
|
||||
value ?
|
||||
AXP20X_GPIO3_FUNCTION_OUT_HIGH :
|
||||
AXP20X_GPIO3_FUNCTION_OUT_LOW);
|
||||
|
||||
reg = axp20x_gpio_get_reg(offset);
|
||||
if (reg < 0)
|
||||
return;
|
||||
return reg;
|
||||
|
||||
regmap_update_bits(pctl->regmap, reg,
|
||||
AXP20X_GPIO_FUNCTIONS,
|
||||
value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
|
||||
AXP20X_GPIO_FUNCTION_OUT_LOW);
|
||||
return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
|
||||
value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
|
||||
AXP20X_GPIO_FUNCTION_OUT_LOW);
|
||||
}
|
||||
|
||||
static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
|
||||
@ -229,12 +225,11 @@ static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
|
||||
int reg;
|
||||
|
||||
/* AXP209 GPIO3 settings have a different layout */
|
||||
if (offset == 3) {
|
||||
if (offset == 3)
|
||||
return regmap_update_bits(pctl->regmap, AXP20X_GPIO3_CTRL,
|
||||
AXP20X_GPIO3_FUNCTIONS,
|
||||
config == AXP20X_MUX_GPIO_OUT ? AXP20X_GPIO3_FUNCTION_OUT_LOW :
|
||||
AXP20X_GPIO3_FUNCTION_INPUT);
|
||||
}
|
||||
|
||||
reg = axp20x_gpio_get_reg(offset);
|
||||
if (reg < 0)
|
||||
@ -468,7 +463,7 @@ static int axp20x_pctl_probe(struct platform_device *pdev)
|
||||
pctl->chip.owner = THIS_MODULE;
|
||||
pctl->chip.get = axp20x_gpio_get;
|
||||
pctl->chip.get_direction = axp20x_gpio_get_direction;
|
||||
pctl->chip.set = axp20x_gpio_set;
|
||||
pctl->chip.set_rv = axp20x_gpio_set;
|
||||
pctl->chip.direction_input = pinctrl_gpio_direction_input;
|
||||
pctl->chip.direction_output = axp20x_gpio_output;
|
||||
|
||||
|
||||
@ -742,14 +742,15 @@ static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off)
|
||||
return reg_val ? 1 : 0;
|
||||
}
|
||||
|
||||
static void cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
|
||||
int val)
|
||||
static int cy8c95x0_gpio_set_value(struct gpio_chip *gc, unsigned int off,
|
||||
int val)
|
||||
{
|
||||
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
|
||||
u8 port = cypress_get_port(chip, off);
|
||||
u8 bit = cypress_get_pin_mask(chip, off);
|
||||
|
||||
cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit, val ? bit : 0);
|
||||
return cy8c95x0_regmap_write_bits(chip, CY8C95X0_OUTPUT, port, bit,
|
||||
val ? bit : 0);
|
||||
}
|
||||
|
||||
static int cy8c95x0_gpio_get_direction(struct gpio_chip *gc, unsigned int off)
|
||||
@ -908,12 +909,12 @@ static int cy8c95x0_gpio_get_multiple(struct gpio_chip *gc,
|
||||
return cy8c95x0_read_regs_mask(chip, CY8C95X0_INPUT, bits, mask);
|
||||
}
|
||||
|
||||
static void cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
|
||||
unsigned long *mask, unsigned long *bits)
|
||||
static int cy8c95x0_gpio_set_multiple(struct gpio_chip *gc,
|
||||
unsigned long *mask, unsigned long *bits)
|
||||
{
|
||||
struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc);
|
||||
|
||||
cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
|
||||
return cy8c95x0_write_regs_mask(chip, CY8C95X0_OUTPUT, bits, mask);
|
||||
}
|
||||
|
||||
static int cy8c95x0_add_pin_ranges(struct gpio_chip *gc)
|
||||
@ -938,10 +939,10 @@ static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip)
|
||||
gc->direction_input = cy8c95x0_gpio_direction_input;
|
||||
gc->direction_output = cy8c95x0_gpio_direction_output;
|
||||
gc->get = cy8c95x0_gpio_get_value;
|
||||
gc->set = cy8c95x0_gpio_set_value;
|
||||
gc->set_rv = cy8c95x0_gpio_set_value;
|
||||
gc->get_direction = cy8c95x0_gpio_get_direction;
|
||||
gc->get_multiple = cy8c95x0_gpio_get_multiple;
|
||||
gc->set_multiple = cy8c95x0_gpio_set_multiple;
|
||||
gc->set_multiple_rv = cy8c95x0_gpio_set_multiple;
|
||||
gc->set_config = gpiochip_generic_config;
|
||||
gc->can_sleep = true;
|
||||
gc->add_pin_ranges = cy8c95x0_add_pin_ranges;
|
||||
|
||||
@ -3800,12 +3800,14 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc)
|
||||
chained_irq_exit(irq_chip, desc);
|
||||
}
|
||||
|
||||
static void ingenic_gpio_set(struct gpio_chip *gc,
|
||||
unsigned int offset, int value)
|
||||
static int ingenic_gpio_set(struct gpio_chip *gc, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
|
||||
|
||||
ingenic_gpio_set_value(jzgc, offset, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
|
||||
@ -4449,7 +4451,7 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
|
||||
jzgc->gc.fwnode = fwnode;
|
||||
jzgc->gc.owner = THIS_MODULE;
|
||||
|
||||
jzgc->gc.set = ingenic_gpio_set;
|
||||
jzgc->gc.set_rv = ingenic_gpio_set;
|
||||
jzgc->gc.get = ingenic_gpio_get;
|
||||
jzgc->gc.direction_input = pinctrl_gpio_direction_input;
|
||||
jzgc->gc.direction_output = ingenic_gpio_direction_output;
|
||||
|
||||
@ -636,6 +636,14 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
|
||||
|
||||
mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
|
||||
|
||||
/*
|
||||
* Reset the chip - we don't really know what state it's in, so reset
|
||||
* all pins to input first to prevent surprises.
|
||||
*/
|
||||
ret = mcp_write(mcp, MCP_IODIR, mcp->chip.ngpio == 16 ? 0xFFFF : 0xFF);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* verify MCP_IOCON.SEQOP = 0, so sequential reads work,
|
||||
* and MCP_IOCON.HAEN = 1, so we work with all chips.
|
||||
*/
|
||||
|
||||
@ -555,10 +555,10 @@ static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio
|
||||
return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
|
||||
}
|
||||
|
||||
static void microchip_sgpio_set_value(struct gpio_chip *gc,
|
||||
unsigned int gpio, int value)
|
||||
static int microchip_sgpio_set_value(struct gpio_chip *gc, unsigned int gpio,
|
||||
int value)
|
||||
{
|
||||
microchip_sgpio_direction_output(gc, gpio, value);
|
||||
return microchip_sgpio_direction_output(gc, gpio, value);
|
||||
}
|
||||
|
||||
static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
|
||||
@ -858,7 +858,7 @@ static int microchip_sgpio_register_bank(struct device *dev,
|
||||
gc->direction_input = microchip_sgpio_direction_input;
|
||||
gc->direction_output = microchip_sgpio_direction_output;
|
||||
gc->get = microchip_sgpio_get_value;
|
||||
gc->set = microchip_sgpio_set_value;
|
||||
gc->set_rv = microchip_sgpio_set_value;
|
||||
gc->request = gpiochip_generic_request;
|
||||
gc->free = gpiochip_generic_free;
|
||||
gc->of_xlate = microchip_sgpio_of_xlate;
|
||||
|
||||
@ -1950,17 +1950,18 @@ static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
return !!(val & BIT(offset % 32));
|
||||
}
|
||||
|
||||
static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
static int ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct ocelot_pinctrl *info = gpiochip_get_data(chip);
|
||||
|
||||
if (value)
|
||||
regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
|
||||
BIT(offset % 32));
|
||||
else
|
||||
regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
|
||||
BIT(offset % 32));
|
||||
return regmap_write(info->map,
|
||||
REG(OCELOT_GPIO_OUT_SET, info, offset),
|
||||
BIT(offset % 32));
|
||||
|
||||
return regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
|
||||
BIT(offset % 32));
|
||||
}
|
||||
|
||||
static int ocelot_gpio_get_direction(struct gpio_chip *chip,
|
||||
@ -1996,7 +1997,7 @@ static int ocelot_gpio_direction_output(struct gpio_chip *chip,
|
||||
static const struct gpio_chip ocelot_gpiolib_chip = {
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.set = ocelot_gpio_set,
|
||||
.set_rv = ocelot_gpio_set,
|
||||
.get = ocelot_gpio_get,
|
||||
.get_direction = ocelot_gpio_get_direction,
|
||||
.direction_input = pinctrl_gpio_direction_input,
|
||||
|
||||
@ -1186,12 +1186,14 @@ static int pistachio_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
return !!(gpio_readl(bank, reg) & BIT(offset));
|
||||
}
|
||||
|
||||
static void pistachio_gpio_set(struct gpio_chip *chip, unsigned offset,
|
||||
int value)
|
||||
static int pistachio_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct pistachio_gpio_bank *bank = gpiochip_get_data(chip);
|
||||
|
||||
gpio_mask_writel(bank, GPIO_OUTPUT, offset, !!value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pistachio_gpio_direction_input(struct gpio_chip *chip,
|
||||
@ -1326,7 +1328,7 @@ static void pistachio_gpio_irq_handler(struct irq_desc *desc)
|
||||
.direction_input = pistachio_gpio_direction_input, \
|
||||
.direction_output = pistachio_gpio_direction_output, \
|
||||
.get = pistachio_gpio_get, \
|
||||
.set = pistachio_gpio_set, \
|
||||
.set_rv = pistachio_gpio_set, \
|
||||
.base = _pin_base, \
|
||||
.ngpio = _npins, \
|
||||
}, \
|
||||
|
||||
@ -325,26 +325,26 @@ static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
return !!(val & pci->pin_cfg[offset].val_msk);
|
||||
}
|
||||
|
||||
static void rk805_gpio_set(struct gpio_chip *chip,
|
||||
unsigned int offset,
|
||||
int value)
|
||||
static int rk805_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct rk805_pctrl_info *pci = gpiochip_get_data(chip);
|
||||
int ret;
|
||||
|
||||
ret = regmap_update_bits(pci->rk808->regmap,
|
||||
pci->pin_cfg[offset].reg,
|
||||
pci->pin_cfg[offset].val_msk,
|
||||
value ? pci->pin_cfg[offset].val_msk : 0);
|
||||
if (ret)
|
||||
dev_err(pci->dev, "set gpio%d value %d failed\n",
|
||||
offset, value);
|
||||
return regmap_update_bits(pci->rk808->regmap,
|
||||
pci->pin_cfg[offset].reg,
|
||||
pci->pin_cfg[offset].val_msk,
|
||||
value ? pci->pin_cfg[offset].val_msk : 0);
|
||||
}
|
||||
|
||||
static int rk805_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
rk805_gpio_set(chip, offset, value);
|
||||
int ret;
|
||||
|
||||
ret = rk805_gpio_set(chip, offset, value);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return pinctrl_gpio_direction_output(chip, offset);
|
||||
}
|
||||
|
||||
@ -378,7 +378,7 @@ static const struct gpio_chip rk805_gpio_chip = {
|
||||
.free = gpiochip_generic_free,
|
||||
.get_direction = rk805_gpio_get_direction,
|
||||
.get = rk805_gpio_get,
|
||||
.set = rk805_gpio_set,
|
||||
.set_rv = rk805_gpio_set,
|
||||
.direction_input = pinctrl_gpio_direction_input,
|
||||
.direction_output = rk805_gpio_direction_output,
|
||||
.can_sleep = true,
|
||||
|
||||
@ -507,6 +507,7 @@ static int pinctrl_scmi_get_pins(struct scmi_pinctrl *pmx,
|
||||
|
||||
static const char * const scmi_pinctrl_blocklist[] = {
|
||||
"fsl,imx95",
|
||||
"fsl,imx94",
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@ -115,14 +115,14 @@ static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
|
||||
return ret ? ret : !!(value & mask);
|
||||
}
|
||||
|
||||
static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
|
||||
static int stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
|
||||
{
|
||||
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
|
||||
u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
|
||||
u32 mask = get_mask(offset);
|
||||
|
||||
regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
|
||||
mask, mask);
|
||||
return regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
|
||||
mask, mask);
|
||||
}
|
||||
|
||||
static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
|
||||
@ -161,8 +161,11 @@ static int stmfx_gpio_direction_output(struct gpio_chip *gc,
|
||||
struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
|
||||
u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
|
||||
u32 mask = get_mask(offset);
|
||||
int ret;
|
||||
|
||||
stmfx_gpio_set(gc, offset, value);
|
||||
ret = stmfx_gpio_set(gc, offset, value);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
|
||||
}
|
||||
@ -694,7 +697,7 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev)
|
||||
pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
|
||||
pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
|
||||
pctl->gpio_chip.get = stmfx_gpio_get;
|
||||
pctl->gpio_chip.set = stmfx_gpio_set;
|
||||
pctl->gpio_chip.set_rv = stmfx_gpio_set;
|
||||
pctl->gpio_chip.set_config = gpiochip_generic_config;
|
||||
pctl->gpio_chip.base = -1;
|
||||
pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
|
||||
|
||||
@ -432,24 +432,25 @@ static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
|
||||
(value ? 0x1f : 0x10));
|
||||
}
|
||||
|
||||
static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
static int sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
if (sx150x_pin_is_oscio(pctl, offset))
|
||||
sx150x_gpio_oscio_set(pctl, value);
|
||||
else
|
||||
__sx150x_gpio_set(pctl, offset, value);
|
||||
return sx150x_gpio_oscio_set(pctl, value);
|
||||
|
||||
return __sx150x_gpio_set(pctl, offset, value);
|
||||
}
|
||||
|
||||
static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
|
||||
unsigned long *mask,
|
||||
unsigned long *bits)
|
||||
static int sx150x_gpio_set_multiple(struct gpio_chip *chip,
|
||||
unsigned long *mask,
|
||||
unsigned long *bits)
|
||||
{
|
||||
struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
|
||||
|
||||
regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
|
||||
return regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask,
|
||||
*bits);
|
||||
}
|
||||
|
||||
static int sx150x_gpio_direction_input(struct gpio_chip *chip,
|
||||
@ -1175,7 +1176,7 @@ static int sx150x_probe(struct i2c_client *client)
|
||||
pctl->gpio.direction_input = sx150x_gpio_direction_input;
|
||||
pctl->gpio.direction_output = sx150x_gpio_direction_output;
|
||||
pctl->gpio.get = sx150x_gpio_get;
|
||||
pctl->gpio.set = sx150x_gpio_set;
|
||||
pctl->gpio.set_rv = sx150x_gpio_set;
|
||||
pctl->gpio.set_config = gpiochip_generic_config;
|
||||
pctl->gpio.parent = dev;
|
||||
pctl->gpio.can_sleep = true;
|
||||
@ -1190,7 +1191,7 @@ static int sx150x_probe(struct i2c_client *client)
|
||||
* would require locking that is not in place at this time.
|
||||
*/
|
||||
if (pctl->data->model != SX150X_789)
|
||||
pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
|
||||
pctl->gpio.set_multiple_rv = sx150x_gpio_set_multiple;
|
||||
|
||||
/* Add Interrupt support if an irq is specified */
|
||||
if (client->irq > 0) {
|
||||
|
||||
@ -327,14 +327,14 @@ static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
|
||||
LPI_GPIO_VALUE_IN_MASK;
|
||||
}
|
||||
|
||||
static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
|
||||
static int lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
|
||||
{
|
||||
struct lpi_pinctrl *state = gpiochip_get_data(chip);
|
||||
unsigned long config;
|
||||
|
||||
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
|
||||
|
||||
lpi_config_set(state->ctrl, pin, &config, 1);
|
||||
return lpi_config_set(state->ctrl, pin, &config, 1);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
@ -398,7 +398,7 @@ static const struct gpio_chip lpi_gpio_template = {
|
||||
.direction_input = lpi_gpio_direction_input,
|
||||
.direction_output = lpi_gpio_direction_output,
|
||||
.get = lpi_gpio_get,
|
||||
.set = lpi_gpio_set,
|
||||
.set_rv = lpi_gpio_set,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.dbg_show = lpi_gpio_dbg_show,
|
||||
|
||||
@ -635,7 +635,7 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
return !!(val & BIT(g->in_bit));
|
||||
}
|
||||
|
||||
static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int msm_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
|
||||
{
|
||||
const struct msm_pingroup *g;
|
||||
struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
|
||||
@ -654,6 +654,8 @@ static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
msm_writel_io(val, pctrl, g);
|
||||
|
||||
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
@ -790,7 +792,7 @@ static const struct gpio_chip msm_gpio_template = {
|
||||
.direction_output = msm_gpio_direction_output,
|
||||
.get_direction = msm_gpio_get_direction,
|
||||
.get = msm_gpio_get,
|
||||
.set = msm_gpio_set,
|
||||
.set_rv = msm_gpio_set,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.dbg_show = msm_gpio_dbg_show,
|
||||
|
||||
@ -37,6 +37,8 @@
|
||||
.mux_bit = 2, \
|
||||
.pull_bit = 0, \
|
||||
.drv_bit = 6, \
|
||||
.egpio_enable = 12, \
|
||||
.egpio_present = 11, \
|
||||
.oe_bit = 9, \
|
||||
.in_bit = 0, \
|
||||
.out_bit = 1, \
|
||||
@ -387,6 +389,7 @@ enum qcm2290_functions {
|
||||
msm_mux_ddr_pxi1,
|
||||
msm_mux_ddr_pxi2,
|
||||
msm_mux_ddr_pxi3,
|
||||
msm_mux_egpio,
|
||||
msm_mux_gcc_gp1,
|
||||
msm_mux_gcc_gp2,
|
||||
msm_mux_gcc_gp3,
|
||||
@ -816,6 +819,13 @@ static const char * const sd_write_groups[] = {
|
||||
static const char * const jitter_bist_groups[] = {
|
||||
"gpio96", "gpio97",
|
||||
};
|
||||
static const char * const egpio_groups[] = {
|
||||
"gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103",
|
||||
"gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
|
||||
"gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
|
||||
"gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
|
||||
"gpio122", "gpio123", "gpio124", "gpio125", "gpio126",
|
||||
};
|
||||
static const char * const ddr_pxi2_groups[] = {
|
||||
"gpio102", "gpio103",
|
||||
};
|
||||
@ -851,6 +861,7 @@ static const struct pinfunction qcm2290_functions[] = {
|
||||
MSM_PIN_FUNCTION(ddr_pxi1),
|
||||
MSM_PIN_FUNCTION(ddr_pxi2),
|
||||
MSM_PIN_FUNCTION(ddr_pxi3),
|
||||
MSM_PIN_FUNCTION(egpio),
|
||||
MSM_PIN_FUNCTION(gcc_gp1),
|
||||
MSM_PIN_FUNCTION(gcc_gp2),
|
||||
MSM_PIN_FUNCTION(gcc_gp3),
|
||||
@ -1037,35 +1048,35 @@ static const struct msm_pingroup qcm2290_groups[] = {
|
||||
[95] = PINGROUP(95, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
|
||||
[96] = PINGROUP(96, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
|
||||
[97] = PINGROUP(97, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
|
||||
[98] = PINGROUP(98, _, _, _, _, _, _, _, _, _),
|
||||
[99] = PINGROUP(99, _, _, _, _, _, _, _, _, _),
|
||||
[100] = PINGROUP(100, atest, _, _, _, _, _, _, _, _),
|
||||
[101] = PINGROUP(101, atest, _, _, _, _, _, _, _, _),
|
||||
[102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
|
||||
[103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
|
||||
[104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, _),
|
||||
[105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
|
||||
[106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
|
||||
[107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
|
||||
[108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, _),
|
||||
[109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, _),
|
||||
[111] = PINGROUP(111, _, _, _, _, _, _, _, _, _),
|
||||
[112] = PINGROUP(112, _, _, _, _, _, _, _, _, _),
|
||||
[113] = PINGROUP(113, _, _, _, _, _, _, _, _, _),
|
||||
[114] = PINGROUP(114, _, _, _, _, _, _, _, _, _),
|
||||
[115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, _),
|
||||
[116] = PINGROUP(116, _, _, _, _, _, _, _, _, _),
|
||||
[117] = PINGROUP(117, _, _, _, _, _, _, _, _, _),
|
||||
[118] = PINGROUP(118, _, _, _, _, _, _, _, _, _),
|
||||
[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _),
|
||||
[120] = PINGROUP(120, _, _, _, _, _, _, _, _, _),
|
||||
[121] = PINGROUP(121, _, _, _, _, _, _, _, _, _),
|
||||
[122] = PINGROUP(122, _, _, _, _, _, _, _, _, _),
|
||||
[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _),
|
||||
[124] = PINGROUP(124, _, _, _, _, _, _, _, _, _),
|
||||
[125] = PINGROUP(125, _, _, _, _, _, _, _, _, _),
|
||||
[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
|
||||
[98] = PINGROUP(98, _, _, _, _, _, _, _, _, egpio),
|
||||
[99] = PINGROUP(99, _, _, _, _, _, _, _, _, egpio),
|
||||
[100] = PINGROUP(100, atest, _, _, _, _, _, _, _, egpio),
|
||||
[101] = PINGROUP(101, atest, _, _, _, _, _, _, _, egpio),
|
||||
[102] = PINGROUP(102, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio),
|
||||
[103] = PINGROUP(103, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, egpio),
|
||||
[104] = PINGROUP(104, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, pwm_8, _, egpio),
|
||||
[105] = PINGROUP(105, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, egpio),
|
||||
[106] = PINGROUP(106, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, egpio),
|
||||
[107] = PINGROUP(107, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, egpio),
|
||||
[108] = PINGROUP(108, nav_gpio, _, _, _, _, _, _, _, egpio),
|
||||
[109] = PINGROUP(109, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[110] = PINGROUP(110, _, qdss_gpio, _, _, _, _, _, _, egpio),
|
||||
[111] = PINGROUP(111, _, _, _, _, _, _, _, _, egpio),
|
||||
[112] = PINGROUP(112, _, _, _, _, _, _, _, _, egpio),
|
||||
[113] = PINGROUP(113, _, _, _, _, _, _, _, _, egpio),
|
||||
[114] = PINGROUP(114, _, _, _, _, _, _, _, _, egpio),
|
||||
[115] = PINGROUP(115, _, pwm_9, _, _, _, _, _, _, egpio),
|
||||
[116] = PINGROUP(116, _, _, _, _, _, _, _, _, egpio),
|
||||
[117] = PINGROUP(117, _, _, _, _, _, _, _, _, egpio),
|
||||
[118] = PINGROUP(118, _, _, _, _, _, _, _, _, egpio),
|
||||
[119] = PINGROUP(119, _, _, _, _, _, _, _, _, egpio),
|
||||
[120] = PINGROUP(120, _, _, _, _, _, _, _, _, egpio),
|
||||
[121] = PINGROUP(121, _, _, _, _, _, _, _, _, egpio),
|
||||
[122] = PINGROUP(122, _, _, _, _, _, _, _, _, egpio),
|
||||
[123] = PINGROUP(123, _, _, _, _, _, _, _, _, egpio),
|
||||
[124] = PINGROUP(124, _, _, _, _, _, _, _, _, egpio),
|
||||
[125] = PINGROUP(125, _, _, _, _, _, _, _, _, egpio),
|
||||
[126] = PINGROUP(126, _, _, _, _, _, _, _, _, egpio),
|
||||
[127] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x84004, 0, 0),
|
||||
[128] = SDC_QDSD_PINGROUP(sdc1_clk, 0x84000, 13, 6),
|
||||
[129] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x84000, 11, 3),
|
||||
@ -1095,6 +1106,7 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = {
|
||||
.ngpios = 127,
|
||||
.wakeirq_map = qcm2290_mpm_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map),
|
||||
.egpio_func = 9,
|
||||
};
|
||||
|
||||
static int qcm2290_pinctrl_probe(struct platform_device *pdev)
|
||||
|
||||
@ -1062,7 +1062,7 @@ static const struct msm_pinctrl_soc_data qcs615_tlmm = {
|
||||
.nfunctions = ARRAY_SIZE(qcs615_functions),
|
||||
.groups = qcs615_groups,
|
||||
.ngroups = ARRAY_SIZE(qcs615_groups),
|
||||
.ngpios = 123,
|
||||
.ngpios = 124,
|
||||
.tiles = qcs615_tiles,
|
||||
.ntiles = ARRAY_SIZE(qcs615_tiles),
|
||||
.wakeirq_map = qcs615_pdc_map,
|
||||
|
||||
@ -1204,7 +1204,7 @@ static const struct msm_pinctrl_soc_data qcs8300_pinctrl = {
|
||||
.nfunctions = ARRAY_SIZE(qcs8300_functions),
|
||||
.groups = qcs8300_groups,
|
||||
.ngroups = ARRAY_SIZE(qcs8300_groups),
|
||||
.ngpios = 133,
|
||||
.ngpios = 134,
|
||||
.wakeirq_map = qcs8300_pdc_map,
|
||||
.nwakeirq_map = ARRAY_SIZE(qcs8300_pdc_map),
|
||||
.egpio_func = 11,
|
||||
|
||||
@ -764,14 +764,14 @@ static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
|
||||
return !!pad->out_value;
|
||||
}
|
||||
|
||||
static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
|
||||
static int pmic_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
|
||||
{
|
||||
struct pmic_gpio_state *state = gpiochip_get_data(chip);
|
||||
unsigned long config;
|
||||
|
||||
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
|
||||
|
||||
pmic_gpio_config_set(state->ctrl, pin, &config, 1);
|
||||
return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
|
||||
}
|
||||
|
||||
static int pmic_gpio_of_xlate(struct gpio_chip *chip,
|
||||
@ -802,7 +802,7 @@ static const struct gpio_chip pmic_gpio_gpio_template = {
|
||||
.direction_input = pmic_gpio_direction_input,
|
||||
.direction_output = pmic_gpio_direction_output,
|
||||
.get = pmic_gpio_get,
|
||||
.set = pmic_gpio_set,
|
||||
.set_rv = pmic_gpio_set,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.of_xlate = pmic_gpio_of_xlate,
|
||||
|
||||
@ -600,14 +600,14 @@ static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
|
||||
return !!pad->out_value;
|
||||
}
|
||||
|
||||
static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value)
|
||||
static int pmic_mpp_set(struct gpio_chip *chip, unsigned int pin, int value)
|
||||
{
|
||||
struct pmic_mpp_state *state = gpiochip_get_data(chip);
|
||||
unsigned long config;
|
||||
|
||||
config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
|
||||
|
||||
pmic_mpp_config_set(state->ctrl, pin, &config, 1);
|
||||
return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
|
||||
}
|
||||
|
||||
static int pmic_mpp_of_xlate(struct gpio_chip *chip,
|
||||
@ -638,7 +638,7 @@ static const struct gpio_chip pmic_mpp_gpio_template = {
|
||||
.direction_input = pmic_mpp_direction_input,
|
||||
.direction_output = pmic_mpp_direction_output,
|
||||
.get = pmic_mpp_get,
|
||||
.set = pmic_mpp_set,
|
||||
.set_rv = pmic_mpp_set,
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.of_xlate = pmic_mpp_of_xlate,
|
||||
|
||||
@ -507,7 +507,8 @@ static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int pm8xxx_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
|
||||
struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
|
||||
@ -519,7 +520,7 @@ static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
val |= pin->open_drain << 1;
|
||||
val |= pin->output_value;
|
||||
|
||||
pm8xxx_write_bank(pctrl, pin, 1, val);
|
||||
return pm8xxx_write_bank(pctrl, pin, 1, val);
|
||||
}
|
||||
|
||||
static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
|
||||
@ -596,7 +597,7 @@ static const struct gpio_chip pm8xxx_gpio_template = {
|
||||
.direction_input = pm8xxx_gpio_direction_input,
|
||||
.direction_output = pm8xxx_gpio_direction_output,
|
||||
.get = pm8xxx_gpio_get,
|
||||
.set = pm8xxx_gpio_set,
|
||||
.set_rv = pm8xxx_gpio_set,
|
||||
.of_xlate = pm8xxx_gpio_of_xlate,
|
||||
.dbg_show = pm8xxx_gpio_dbg_show,
|
||||
.owner = THIS_MODULE,
|
||||
|
||||
@ -511,14 +511,15 @@ static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int pm8xxx_mpp_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct pm8xxx_mpp *pctrl = gpiochip_get_data(chip);
|
||||
struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
|
||||
|
||||
pin->output_value = !!value;
|
||||
|
||||
pm8xxx_mpp_update(pctrl, pin);
|
||||
return pm8xxx_mpp_update(pctrl, pin);
|
||||
}
|
||||
|
||||
static int pm8xxx_mpp_of_xlate(struct gpio_chip *chip,
|
||||
@ -633,7 +634,7 @@ static const struct gpio_chip pm8xxx_mpp_template = {
|
||||
.direction_input = pm8xxx_mpp_direction_input,
|
||||
.direction_output = pm8xxx_mpp_direction_output,
|
||||
.get = pm8xxx_mpp_get,
|
||||
.set = pm8xxx_mpp_set,
|
||||
.set_rv = pm8xxx_mpp_set,
|
||||
.of_xlate = pm8xxx_mpp_of_xlate,
|
||||
.dbg_show = pm8xxx_mpp_dbg_show,
|
||||
.owner = THIS_MODULE,
|
||||
|
||||
@ -547,6 +547,7 @@ static int tlmm_test_init(struct kunit *test)
|
||||
struct tlmm_test_priv *priv;
|
||||
|
||||
priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL);
|
||||
KUNIT_ASSERT_NOT_ERR_OR_NULL(test, priv);
|
||||
|
||||
atomic_set(&priv->intr_count, 0);
|
||||
atomic_set(&priv->thread_count, 0);
|
||||
|
||||
@ -42,6 +42,7 @@ config PINCTRL_RENESAS
|
||||
select PINCTRL_RZG2L if ARCH_RZG2L
|
||||
select PINCTRL_RZV2M if ARCH_R9A09G011
|
||||
select PINCTRL_RZG2L if ARCH_R9A09G047
|
||||
select PINCTRL_RZG2L if ARCH_R9A09G056
|
||||
select PINCTRL_RZG2L if ARCH_R9A09G057
|
||||
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
|
||||
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
|
||||
|
||||
@ -2230,135 +2230,146 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
|
||||
PIN_CFG_IO_VMC_SD1)) },
|
||||
};
|
||||
|
||||
static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
|
||||
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
|
||||
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN)) },
|
||||
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_NOD)) },
|
||||
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_NOD)) },
|
||||
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
static const struct {
|
||||
struct rzg2l_dedicated_configs common[77];
|
||||
struct rzg2l_dedicated_configs pcie1[1];
|
||||
} rzv2h_dedicated_pins = {
|
||||
.common = {
|
||||
{ "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
|
||||
{ "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN)) },
|
||||
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_NOD)) },
|
||||
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_NOD)) },
|
||||
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||
{ "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H |
|
||||
PIN_CFG_SR)) },
|
||||
{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H |
|
||||
PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||
{ "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H |
|
||||
PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD | PIN_CFG_OEN)) },
|
||||
{ "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
|
||||
PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
|
||||
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
|
||||
},
|
||||
.pcie1 = {
|
||||
{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H |
|
||||
PIN_CFG_SR)) },
|
||||
},
|
||||
};
|
||||
|
||||
static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
|
||||
@ -3349,13 +3360,37 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
|
||||
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
|
||||
};
|
||||
|
||||
static struct rzg2l_pinctrl_data r9a09g056_data = {
|
||||
.port_pins = rzv2h_gpio_names,
|
||||
.port_pin_configs = r9a09g057_gpio_configs,
|
||||
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
|
||||
.dedicated_pins = rzv2h_dedicated_pins.common,
|
||||
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
|
||||
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common),
|
||||
.hwcfg = &rzv2h_hwcfg,
|
||||
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
|
||||
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
|
||||
.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
|
||||
.custom_params = renesas_rzv2h_custom_bindings,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.custom_conf_items = renesas_rzv2h_conf_items,
|
||||
#endif
|
||||
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
|
||||
.pmc_writeb = &rzv2h_pmc_writeb,
|
||||
.oen_read = &rzv2h_oen_read,
|
||||
.oen_write = &rzv2h_oen_write,
|
||||
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
|
||||
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
|
||||
};
|
||||
|
||||
static struct rzg2l_pinctrl_data r9a09g057_data = {
|
||||
.port_pins = rzv2h_gpio_names,
|
||||
.port_pin_configs = r9a09g057_gpio_configs,
|
||||
.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
|
||||
.dedicated_pins = rzv2h_dedicated_pins,
|
||||
.dedicated_pins = rzv2h_dedicated_pins.common,
|
||||
.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
|
||||
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins),
|
||||
.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) +
|
||||
ARRAY_SIZE(rzv2h_dedicated_pins.pcie1),
|
||||
.hwcfg = &rzv2h_hwcfg,
|
||||
.variable_pin_cfg = r9a09g057_variable_pin_cfg,
|
||||
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
|
||||
@ -3389,6 +3424,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
|
||||
.compatible = "renesas,r9a09g047-pinctrl",
|
||||
.data = &r9a09g047_data,
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r9a09g056-pinctrl",
|
||||
.data = &r9a09g056_data,
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r9a09g057-pinctrl",
|
||||
.data = &r9a09g057_data,
|
||||
|
||||
@ -1419,8 +1419,8 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
|
||||
.pin_banks = exynosautov920_pin_banks0,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
|
||||
.eint_wkup_init = exynos_eint_wkup_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
.retention_data = &exynosautov920_retention_data,
|
||||
}, {
|
||||
/* pin-controller instance 1 AUD data */
|
||||
@ -1431,43 +1431,43 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
|
||||
.pin_banks = exynosautov920_pin_banks2,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
}, {
|
||||
/* pin-controller instance 3 HSI1 data */
|
||||
.pin_banks = exynosautov920_pin_banks3,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
}, {
|
||||
/* pin-controller instance 4 HSI2 data */
|
||||
.pin_banks = exynosautov920_pin_banks4,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
}, {
|
||||
/* pin-controller instance 5 HSI2UFS data */
|
||||
.pin_banks = exynosautov920_pin_banks5,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
}, {
|
||||
/* pin-controller instance 6 PERIC0 data */
|
||||
.pin_banks = exynosautov920_pin_banks6,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
}, {
|
||||
/* pin-controller instance 7 PERIC1 data */
|
||||
.pin_banks = exynosautov920_pin_banks7,
|
||||
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = exynosautov920_pinctrl_suspend,
|
||||
.resume = exynosautov920_pinctrl_resume,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1762,15 +1762,15 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
|
||||
.pin_banks = gs101_pin_alive,
|
||||
.nr_banks = ARRAY_SIZE(gs101_pin_alive),
|
||||
.eint_wkup_init = exynos_eint_wkup_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = gs101_pinctrl_suspend,
|
||||
.resume = gs101_pinctrl_resume,
|
||||
}, {
|
||||
/* pin banks of gs101 pin-controller (FAR_ALIVE) */
|
||||
.pin_banks = gs101_pin_far_alive,
|
||||
.nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
|
||||
.eint_wkup_init = exynos_eint_wkup_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = gs101_pinctrl_suspend,
|
||||
.resume = gs101_pinctrl_resume,
|
||||
}, {
|
||||
/* pin banks of gs101 pin-controller (GSACORE) */
|
||||
.pin_banks = gs101_pin_gsacore,
|
||||
@ -1784,29 +1784,29 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
|
||||
.pin_banks = gs101_pin_peric0,
|
||||
.nr_banks = ARRAY_SIZE(gs101_pin_peric0),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = gs101_pinctrl_suspend,
|
||||
.resume = gs101_pinctrl_resume,
|
||||
}, {
|
||||
/* pin banks of gs101 pin-controller (PERIC1) */
|
||||
.pin_banks = gs101_pin_peric1,
|
||||
.nr_banks = ARRAY_SIZE(gs101_pin_peric1),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = gs101_pinctrl_suspend,
|
||||
.resume = gs101_pinctrl_resume,
|
||||
}, {
|
||||
/* pin banks of gs101 pin-controller (HSI1) */
|
||||
.pin_banks = gs101_pin_hsi1,
|
||||
.nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = gs101_pinctrl_suspend,
|
||||
.resume = gs101_pinctrl_resume,
|
||||
}, {
|
||||
/* pin banks of gs101 pin-controller (HSI2) */
|
||||
.pin_banks = gs101_pin_hsi2,
|
||||
.nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
|
||||
.eint_gpio_init = exynos_eint_gpio_init,
|
||||
.suspend = exynos_pinctrl_suspend,
|
||||
.resume = exynos_pinctrl_resume,
|
||||
.suspend = gs101_pinctrl_suspend,
|
||||
.resume = gs101_pinctrl_resume,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
@ -370,6 +370,37 @@ struct exynos_eint_gpio_save {
|
||||
u32 eint_mask;
|
||||
};
|
||||
|
||||
static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con)
|
||||
{
|
||||
unsigned int val, shift;
|
||||
int i;
|
||||
|
||||
val = readl(reg);
|
||||
for (i = 0; i < cnt; i++) {
|
||||
shift = i * EXYNOS_FLTCON_LEN;
|
||||
val &= ~(EXYNOS_FLTCON_DIGITAL << shift);
|
||||
val |= con << shift;
|
||||
}
|
||||
writel(val, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set the desired filter (digital or analog delay) and enable it to
|
||||
* every pin in the bank. Note the filter selection bitfield is only
|
||||
* found on alive banks. The filter determines to what extent signal
|
||||
* fluctuations received through the pad are considered glitches.
|
||||
*/
|
||||
static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filter)
|
||||
{
|
||||
unsigned int off = EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offset;
|
||||
void __iomem *reg = bank->drvdata->virt_base + off;
|
||||
unsigned int con = EXYNOS_FLTCON_EN | filter;
|
||||
|
||||
for (int n = 0; n < bank->nr_pins; n += 4)
|
||||
exynos_eint_update_flt_reg(reg + n,
|
||||
min(bank->nr_pins - n, 4), con);
|
||||
}
|
||||
|
||||
/*
|
||||
* exynos_eint_gpio_init() - setup handling of external gpio interrupts.
|
||||
* @d: driver data of samsung pinctrl driver.
|
||||
@ -762,153 +793,190 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos_pinctrl_suspend_bank(
|
||||
struct samsung_pinctrl_drv_data *drvdata,
|
||||
struct samsung_pin_bank *bank)
|
||||
static void exynos_set_wakeup(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct exynos_irq_chip *irq_chip;
|
||||
|
||||
if (bank->irq_chip) {
|
||||
irq_chip = bank->irq_chip;
|
||||
irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
|
||||
}
|
||||
}
|
||||
|
||||
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
||||
const void __iomem *regs = bank->eint_base;
|
||||
|
||||
if (clk_enable(bank->drvdata->pclk)) {
|
||||
dev_err(bank->gpio_chip.parent,
|
||||
"unable to enable clock for saving state\n");
|
||||
return;
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset);
|
||||
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset);
|
||||
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset + 4);
|
||||
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset);
|
||||
|
||||
pr_debug("%s: save con %#010x\n",
|
||||
bank->name, save->eint_con);
|
||||
pr_debug("%s: save fltcon0 %#010x\n",
|
||||
bank->name, save->eint_fltcon0);
|
||||
pr_debug("%s: save fltcon1 %#010x\n",
|
||||
bank->name, save->eint_fltcon1);
|
||||
pr_debug("%s: save mask %#010x\n",
|
||||
bank->name, save->eint_mask);
|
||||
} else if (bank->eint_type == EINT_TYPE_WKUP) {
|
||||
exynos_set_wakeup(bank);
|
||||
}
|
||||
|
||||
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset);
|
||||
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset);
|
||||
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset + 4);
|
||||
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset);
|
||||
|
||||
clk_disable(bank->drvdata->pclk);
|
||||
|
||||
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
|
||||
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
|
||||
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
|
||||
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
|
||||
}
|
||||
|
||||
static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata,
|
||||
struct samsung_pin_bank *bank)
|
||||
void gs101_pinctrl_suspend(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
||||
const void __iomem *regs = bank->eint_base;
|
||||
|
||||
if (clk_enable(bank->drvdata->pclk)) {
|
||||
dev_err(bank->gpio_chip.parent,
|
||||
"unable to enable clock for saving state\n");
|
||||
return;
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset);
|
||||
|
||||
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ bank->eint_fltcon_offset);
|
||||
|
||||
/* fltcon1 register only exists for pins 4-7 */
|
||||
if (bank->nr_pins > 4)
|
||||
save->eint_fltcon1 = readl(regs +
|
||||
EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ bank->eint_fltcon_offset + 4);
|
||||
|
||||
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset);
|
||||
|
||||
pr_debug("%s: save con %#010x\n",
|
||||
bank->name, save->eint_con);
|
||||
pr_debug("%s: save fltcon0 %#010x\n",
|
||||
bank->name, save->eint_fltcon0);
|
||||
if (bank->nr_pins > 4)
|
||||
pr_debug("%s: save fltcon1 %#010x\n",
|
||||
bank->name, save->eint_fltcon1);
|
||||
pr_debug("%s: save mask %#010x\n",
|
||||
bank->name, save->eint_mask);
|
||||
} else if (bank->eint_type == EINT_TYPE_WKUP) {
|
||||
exynos_set_wakeup(bank);
|
||||
exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG);
|
||||
}
|
||||
|
||||
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
|
||||
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
|
||||
|
||||
clk_disable(bank->drvdata->pclk);
|
||||
|
||||
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
|
||||
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
|
||||
}
|
||||
|
||||
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
|
||||
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct samsung_pin_bank *bank = drvdata->pin_banks;
|
||||
struct exynos_irq_chip *irq_chip = NULL;
|
||||
int i;
|
||||
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
||||
const void __iomem *regs = bank->eint_base;
|
||||
|
||||
for (i = 0; i < drvdata->nr_banks; ++i, ++bank) {
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
if (bank->eint_con_offset)
|
||||
exynosauto_pinctrl_suspend_bank(drvdata, bank);
|
||||
else
|
||||
exynos_pinctrl_suspend_bank(drvdata, bank);
|
||||
}
|
||||
else if (bank->eint_type == EINT_TYPE_WKUP) {
|
||||
if (!irq_chip) {
|
||||
irq_chip = bank->irq_chip;
|
||||
irq_chip->set_eint_wakeup_mask(drvdata,
|
||||
irq_chip);
|
||||
}
|
||||
}
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
save->eint_con = readl(regs + bank->pctl_offset +
|
||||
bank->eint_con_offset);
|
||||
save->eint_mask = readl(regs + bank->pctl_offset +
|
||||
bank->eint_mask_offset);
|
||||
pr_debug("%s: save con %#010x\n",
|
||||
bank->name, save->eint_con);
|
||||
pr_debug("%s: save mask %#010x\n",
|
||||
bank->name, save->eint_mask);
|
||||
} else if (bank->eint_type == EINT_TYPE_WKUP) {
|
||||
exynos_set_wakeup(bank);
|
||||
}
|
||||
}
|
||||
|
||||
static void exynos_pinctrl_resume_bank(
|
||||
struct samsung_pinctrl_drv_data *drvdata,
|
||||
struct samsung_pin_bank *bank)
|
||||
void gs101_pinctrl_resume(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
||||
|
||||
void __iomem *regs = bank->eint_base;
|
||||
void __iomem *eint_fltcfg0 = regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ bank->eint_fltcon_offset;
|
||||
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
pr_debug("%s: con %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset), save->eint_con);
|
||||
|
||||
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
|
||||
readl(eint_fltcfg0), save->eint_fltcon0);
|
||||
|
||||
/* fltcon1 register only exists for pins 4-7 */
|
||||
if (bank->nr_pins > 4)
|
||||
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
|
||||
readl(eint_fltcfg0 + 4), save->eint_fltcon1);
|
||||
|
||||
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset), save->eint_mask);
|
||||
|
||||
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset);
|
||||
writel(save->eint_fltcon0, eint_fltcfg0);
|
||||
|
||||
if (bank->nr_pins > 4)
|
||||
writel(save->eint_fltcon1, eint_fltcfg0 + 4);
|
||||
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset);
|
||||
} else if (bank->eint_type == EINT_TYPE_WKUP) {
|
||||
exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL);
|
||||
}
|
||||
}
|
||||
|
||||
void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
||||
void __iomem *regs = bank->eint_base;
|
||||
|
||||
if (clk_enable(bank->drvdata->pclk)) {
|
||||
dev_err(bank->gpio_chip.parent,
|
||||
"unable to enable clock for restoring state\n");
|
||||
return;
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
pr_debug("%s: con %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset), save->eint_con);
|
||||
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset), save->eint_fltcon0);
|
||||
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset + 4),
|
||||
save->eint_fltcon1);
|
||||
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset), save->eint_mask);
|
||||
|
||||
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset);
|
||||
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset);
|
||||
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset + 4);
|
||||
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset);
|
||||
}
|
||||
|
||||
pr_debug("%s: con %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset), save->eint_con);
|
||||
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset), save->eint_fltcon0);
|
||||
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
|
||||
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
|
||||
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset), save->eint_mask);
|
||||
|
||||
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
|
||||
+ bank->eint_offset);
|
||||
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset);
|
||||
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
|
||||
+ 2 * bank->eint_offset + 4);
|
||||
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
|
||||
+ bank->eint_offset);
|
||||
|
||||
clk_disable(bank->drvdata->pclk);
|
||||
}
|
||||
|
||||
static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata,
|
||||
struct samsung_pin_bank *bank)
|
||||
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
|
||||
{
|
||||
struct exynos_eint_gpio_save *save = bank->soc_priv;
|
||||
void __iomem *regs = bank->eint_base;
|
||||
|
||||
if (clk_enable(bank->drvdata->pclk)) {
|
||||
dev_err(bank->gpio_chip.parent,
|
||||
"unable to enable clock for restoring state\n");
|
||||
return;
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
/* exynosautov920 has eint_con_offset for all but one bank */
|
||||
if (!bank->eint_con_offset)
|
||||
exynos_pinctrl_resume(bank);
|
||||
|
||||
pr_debug("%s: con %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->pctl_offset + bank->eint_con_offset),
|
||||
save->eint_con);
|
||||
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->pctl_offset +
|
||||
bank->eint_mask_offset), save->eint_mask);
|
||||
|
||||
writel(save->eint_con,
|
||||
regs + bank->pctl_offset + bank->eint_con_offset);
|
||||
writel(save->eint_mask,
|
||||
regs + bank->pctl_offset + bank->eint_mask_offset);
|
||||
}
|
||||
|
||||
pr_debug("%s: con %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
|
||||
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
|
||||
readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
|
||||
|
||||
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
|
||||
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
|
||||
|
||||
clk_disable(bank->drvdata->pclk);
|
||||
}
|
||||
|
||||
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
|
||||
{
|
||||
struct samsung_pin_bank *bank = drvdata->pin_banks;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
|
||||
if (bank->eint_type == EINT_TYPE_GPIO) {
|
||||
if (bank->eint_con_offset)
|
||||
exynosauto_pinctrl_resume_bank(drvdata, bank);
|
||||
else
|
||||
exynos_pinctrl_resume_bank(drvdata, bank);
|
||||
}
|
||||
}
|
||||
|
||||
static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata)
|
||||
|
||||
@ -52,6 +52,26 @@
|
||||
#define EXYNOS_EINT_MAX_PER_BANK 8
|
||||
#define EXYNOS_EINT_NR_WKUP_EINT
|
||||
|
||||
/*
|
||||
* EINT filter configuration register (on alive banks) has
|
||||
* the following layout.
|
||||
*
|
||||
* BitfieldName[PinNum][Bit:Bit]
|
||||
* FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
|
||||
* FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
|
||||
* FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
|
||||
* FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0]
|
||||
*
|
||||
* FLT_EN 0x0 = Disable, 0x1=Enable
|
||||
* FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count)
|
||||
* FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1
|
||||
*/
|
||||
|
||||
#define EXYNOS_FLTCON_EN BIT(7)
|
||||
#define EXYNOS_FLTCON_DIGITAL BIT(6)
|
||||
#define EXYNOS_FLTCON_ANALOG (0 << 6)
|
||||
#define EXYNOS_FLTCON_LEN 8
|
||||
|
||||
#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
|
||||
{ \
|
||||
.type = &bank_type_off, \
|
||||
@ -240,8 +260,12 @@ struct exynos_muxed_weint_data {
|
||||
|
||||
int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
|
||||
int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
|
||||
void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata);
|
||||
void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata);
|
||||
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
|
||||
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
|
||||
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
|
||||
void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
|
||||
void gs101_pinctrl_suspend(struct samsung_pin_bank *bank);
|
||||
void gs101_pinctrl_resume(struct samsung_pin_bank *bank);
|
||||
struct samsung_retention_ctrl *
|
||||
exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
|
||||
const struct samsung_retention_data *data);
|
||||
|
||||
@ -570,15 +570,18 @@ static void samsung_gpio_set_value(struct gpio_chip *gc,
|
||||
}
|
||||
|
||||
/* gpiolib gpio_set callback function */
|
||||
static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
|
||||
static int samsung_gpio_set(struct gpio_chip *gc, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct samsung_pin_bank *bank = gpiochip_get_data(gc);
|
||||
struct samsung_pinctrl_drv_data *drvdata = bank->drvdata;
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
if (clk_enable(drvdata->pclk)) {
|
||||
ret = clk_enable(drvdata->pclk);
|
||||
if (ret) {
|
||||
dev_err(drvdata->dev, "failed to enable clock\n");
|
||||
return;
|
||||
return ret;
|
||||
}
|
||||
|
||||
raw_spin_lock_irqsave(&bank->slock, flags);
|
||||
@ -586,6 +589,8 @@ static void samsung_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
|
||||
raw_spin_unlock_irqrestore(&bank->slock, flags);
|
||||
|
||||
clk_disable(drvdata->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* gpiolib gpio_get callback function */
|
||||
@ -1062,7 +1067,7 @@ static int samsung_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
|
||||
static const struct gpio_chip samsung_gpiolib_chip = {
|
||||
.request = gpiochip_generic_request,
|
||||
.free = gpiochip_generic_free,
|
||||
.set = samsung_gpio_set,
|
||||
.set_rv = samsung_gpio_set,
|
||||
.get = samsung_gpio_get,
|
||||
.direction_input = samsung_gpio_direction_input,
|
||||
.direction_output = samsung_gpio_direction_output,
|
||||
@ -1333,6 +1338,7 @@ err_put_banks:
|
||||
static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
|
||||
{
|
||||
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
|
||||
struct samsung_pin_bank *bank;
|
||||
int i;
|
||||
|
||||
i = clk_enable(drvdata->pclk);
|
||||
@ -1343,7 +1349,7 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
|
||||
}
|
||||
|
||||
for (i = 0; i < drvdata->nr_banks; i++) {
|
||||
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
|
||||
bank = &drvdata->pin_banks[i];
|
||||
const void __iomem *reg = bank->pctl_base + bank->pctl_offset;
|
||||
const u8 *offs = bank->type->reg_offset;
|
||||
const u8 *widths = bank->type->fld_width;
|
||||
@ -1371,10 +1377,14 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < drvdata->nr_banks; i++) {
|
||||
bank = &drvdata->pin_banks[i];
|
||||
if (drvdata->suspend)
|
||||
drvdata->suspend(bank);
|
||||
}
|
||||
|
||||
clk_disable(drvdata->pclk);
|
||||
|
||||
if (drvdata->suspend)
|
||||
drvdata->suspend(drvdata);
|
||||
if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable)
|
||||
drvdata->retention_ctrl->enable(drvdata);
|
||||
|
||||
@ -1392,6 +1402,7 @@ static int __maybe_unused samsung_pinctrl_suspend(struct device *dev)
|
||||
static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
|
||||
{
|
||||
struct samsung_pinctrl_drv_data *drvdata = dev_get_drvdata(dev);
|
||||
struct samsung_pin_bank *bank;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
@ -1406,11 +1417,14 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (drvdata->resume)
|
||||
drvdata->resume(drvdata);
|
||||
for (i = 0; i < drvdata->nr_banks; i++) {
|
||||
bank = &drvdata->pin_banks[i];
|
||||
if (drvdata->resume)
|
||||
drvdata->resume(bank);
|
||||
}
|
||||
|
||||
for (i = 0; i < drvdata->nr_banks; i++) {
|
||||
struct samsung_pin_bank *bank = &drvdata->pin_banks[i];
|
||||
bank = &drvdata->pin_banks[i];
|
||||
void __iomem *reg = bank->pctl_base + bank->pctl_offset;
|
||||
const u8 *offs = bank->type->reg_offset;
|
||||
const u8 *widths = bank->type->fld_width;
|
||||
|
||||
@ -285,8 +285,8 @@ struct samsung_pin_ctrl {
|
||||
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
|
||||
int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
|
||||
void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata);
|
||||
void (*suspend)(struct samsung_pinctrl_drv_data *);
|
||||
void (*resume)(struct samsung_pinctrl_drv_data *);
|
||||
void (*suspend)(struct samsung_pin_bank *bank);
|
||||
void (*resume)(struct samsung_pin_bank *bank);
|
||||
};
|
||||
|
||||
/**
|
||||
@ -335,8 +335,8 @@ struct samsung_pinctrl_drv_data {
|
||||
|
||||
struct samsung_retention_ctrl *retention_ctrl;
|
||||
|
||||
void (*suspend)(struct samsung_pinctrl_drv_data *);
|
||||
void (*resume)(struct samsung_pinctrl_drv_data *);
|
||||
void (*suspend)(struct samsung_pin_bank *bank);
|
||||
void (*resume)(struct samsung_pin_bank *bank);
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
/* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org> */
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
@ -721,6 +722,7 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spacemit_pinctrl *pctrl;
|
||||
struct clk *func_clk, *bus_clk;
|
||||
const struct spacemit_pinctrl_data *pctrl_data;
|
||||
int ret;
|
||||
|
||||
@ -739,6 +741,14 @@ static int spacemit_pinctrl_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(pctrl->regs))
|
||||
return PTR_ERR(pctrl->regs);
|
||||
|
||||
func_clk = devm_clk_get_enabled(dev, "func");
|
||||
if (IS_ERR(func_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(func_clk), "failed to get func clock\n");
|
||||
|
||||
bus_clk = devm_clk_get_enabled(dev, "bus");
|
||||
if (IS_ERR(bus_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n");
|
||||
|
||||
pctrl->pdesc.name = dev_name(dev);
|
||||
pctrl->pdesc.pins = pctrl_data->pins;
|
||||
pctrl->pdesc.npins = pctrl_data->npins;
|
||||
|
||||
@ -228,11 +228,14 @@ static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
|
||||
}
|
||||
|
||||
static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
static int stm32_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
|
||||
|
||||
__stm32_gpio_set(bank, offset, value);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_gpio_direction_output(struct gpio_chip *chip,
|
||||
@ -308,7 +311,7 @@ static const struct gpio_chip stm32_gpio_template = {
|
||||
.request = stm32_gpio_request,
|
||||
.free = pinctrl_gpio_free,
|
||||
.get = stm32_gpio_get,
|
||||
.set = stm32_gpio_set,
|
||||
.set_rv = stm32_gpio_set,
|
||||
.direction_input = pinctrl_gpio_direction_input,
|
||||
.direction_output = stm32_gpio_direction_output,
|
||||
.to_irq = stm32_gpio_to_irq,
|
||||
|
||||
@ -3,7 +3,7 @@ menuconfig PINCTRL_UNIPHIER
|
||||
bool "UniPhier SoC pinctrl drivers"
|
||||
depends on ARCH_UNIPHIER || COMPILE_TEST
|
||||
depends on OF && MFD_SYSCON
|
||||
default y
|
||||
default ARCH_UNIPHIER
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
|
||||
|
||||
@ -149,14 +149,18 @@ struct pinctrl_map {
|
||||
#define PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(dev, grp, cfgs) \
|
||||
PIN_MAP_CONFIGS_GROUP(dev, PINCTRL_STATE_DEFAULT, dev, grp, cfgs)
|
||||
|
||||
struct device;
|
||||
struct pinctrl_map;
|
||||
|
||||
#ifdef CONFIG_PINCTRL
|
||||
|
||||
extern int pinctrl_register_mappings(const struct pinctrl_map *map,
|
||||
unsigned int num_maps);
|
||||
extern void pinctrl_unregister_mappings(const struct pinctrl_map *map);
|
||||
extern void pinctrl_provide_dummies(void);
|
||||
int pinctrl_register_mappings(const struct pinctrl_map *map,
|
||||
unsigned int num_maps);
|
||||
int devm_pinctrl_register_mappings(struct device *dev,
|
||||
const struct pinctrl_map *map,
|
||||
unsigned int num_maps);
|
||||
void pinctrl_unregister_mappings(const struct pinctrl_map *map);
|
||||
void pinctrl_provide_dummies(void);
|
||||
#else
|
||||
|
||||
static inline int pinctrl_register_mappings(const struct pinctrl_map *map,
|
||||
@ -165,6 +169,13 @@ static inline int pinctrl_register_mappings(const struct pinctrl_map *map,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int devm_pinctrl_register_mappings(struct device *dev,
|
||||
const struct pinctrl_map *map,
|
||||
unsigned int num_maps)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void pinctrl_unregister_mappings(const struct pinctrl_map *map)
|
||||
{
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user