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amd-drm-fixes-6.19-2026-01-06:

Browse Source 
amdgpu:
 - Clang fixes
 - Navi1x PCIe DPM fixes
 - Ring reset fixes
 - ISP suspend fix
 - Analog DC fixes
 - VPE fixes
 - Mode1 reset fix
 
 radeon:
 - Variable sized array fix
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Merge tag 'amd-drm-fixes-6.19-2026-01-06' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes

amd-drm-fixes-6.19-2026-01-06:

amdgpu:
- Clang fixes
- Navi1x PCIe DPM fixes
- Ring reset fixes
- ISP suspend fix
- Analog DC fixes
- VPE fixes
- Mode1 reset fix

radeon:
- Variable sized array fix

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20260107223315.16095-1-alexander.deucher@amd.com
This commit is contained in:
Dave Airlie 2026-01-08 09:50:08 +10:00
commit f6eac56d6b
19 changed files with 332 additions and 480 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -3445,11 +3445,10 @@ int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX || (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GFX ||
adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA))
continue; continue;
/* skip CG for VCE/UVD/VPE, it's handled specially */ /* skip CG for VCE/UVD, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD && if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE && adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN && adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VPE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG && adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_JPEG &&
adev->ip_blocks[i].version->funcs->set_powergating_state) { adev->ip_blocks[i].version->funcs->set_powergating_state) {
/* enable powergating to save power */ /* enable powergating to save power */
@ -5867,6 +5866,9 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
if (ret) if (ret)
goto mode1_reset_failed; goto mode1_reset_failed;
/* enable mmio access after mode 1 reset completed */
adev->no_hw_access = false;
amdgpu_device_load_pci_state(adev->pdev); amdgpu_device_load_pci_state(adev->pdev);
ret = amdgpu_psp_wait_for_bootloader(adev); ret = amdgpu_psp_wait_for_bootloader(adev);
if (ret) if (ret)

36
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
View File

@ -89,6 +89,16 @@ static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
return seq; return seq;
} }
static void amdgpu_fence_save_fence_wptr_start(struct amdgpu_fence *af)
{
af->fence_wptr_start = af->ring->wptr;
}
static void amdgpu_fence_save_fence_wptr_end(struct amdgpu_fence *af)
{
af->fence_wptr_end = af->ring->wptr;
}
/** /**
* amdgpu_fence_emit - emit a fence on the requested ring * amdgpu_fence_emit - emit a fence on the requested ring
* *
@ -116,8 +126,10 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,
&ring->fence_drv.lock, &ring->fence_drv.lock,
adev->fence_context + ring->idx, seq); adev->fence_context + ring->idx, seq);
amdgpu_fence_save_fence_wptr_start(af);
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr, amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, flags | AMDGPU_FENCE_FLAG_INT); seq, flags | AMDGPU_FENCE_FLAG_INT);
amdgpu_fence_save_fence_wptr_end(af);
amdgpu_fence_save_wptr(af); amdgpu_fence_save_wptr(af);
pm_runtime_get_noresume(adev_to_drm(adev)->dev); pm_runtime_get_noresume(adev_to_drm(adev)->dev);
ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask]; ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
@ -709,6 +721,7 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)
struct amdgpu_ring *ring = af->ring; struct amdgpu_ring *ring = af->ring;
unsigned long flags; unsigned long flags;
u32 seq, last_seq; u32 seq, last_seq;
bool reemitted = false;
last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask; last_seq = amdgpu_fence_read(ring) & ring->fence_drv.num_fences_mask;
seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask; seq = ring->fence_drv.sync_seq & ring->fence_drv.num_fences_mask;
@ -726,7 +739,9 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)
if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) { if (unprocessed && !dma_fence_is_signaled_locked(unprocessed)) {
fence = container_of(unprocessed, struct amdgpu_fence, base); fence = container_of(unprocessed, struct amdgpu_fence, base);
if (fence == af) if (fence->reemitted > 1)
reemitted = true;
else if (fence == af)
dma_fence_set_error(&fence->base, -ETIME); dma_fence_set_error(&fence->base, -ETIME);
else if (fence->context == af->context) else if (fence->context == af->context)
dma_fence_set_error(&fence->base, -ECANCELED); dma_fence_set_error(&fence->base, -ECANCELED);
@ -734,9 +749,12 @@ void amdgpu_fence_driver_guilty_force_completion(struct amdgpu_fence *af)
rcu_read_unlock(); rcu_read_unlock();
} while (last_seq != seq); } while (last_seq != seq);
spin_unlock_irqrestore(&ring->fence_drv.lock, flags); spin_unlock_irqrestore(&ring->fence_drv.lock, flags);
/* signal the guilty fence */
amdgpu_fence_write(ring, (u32)af->base.seqno); if (reemitted) {
amdgpu_fence_process(ring); /* if we've already reemitted once then just cancel everything */
amdgpu_fence_driver_force_completion(af->ring);
af->ring->ring_backup_entries_to_copy = 0;
}
} }
void amdgpu_fence_save_wptr(struct amdgpu_fence *af) void amdgpu_fence_save_wptr(struct amdgpu_fence *af)
@ -784,10 +802,18 @@ void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
/* save everything if the ring is not guilty, otherwise /* save everything if the ring is not guilty, otherwise
* just save the content from other contexts. * just save the content from other contexts.
*/ */
if (!guilty_fence || (fence->context != guilty_fence->context)) if (!fence->reemitted &&
(!guilty_fence || (fence->context != guilty_fence->context))) {
amdgpu_ring_backup_unprocessed_command(ring, wptr, amdgpu_ring_backup_unprocessed_command(ring, wptr,
fence->wptr); fence->wptr);
} else if (!fence->reemitted) {
/* always save the fence */
amdgpu_ring_backup_unprocessed_command(ring,
fence->fence_wptr_start,
fence->fence_wptr_end);
}
wptr = fence->wptr; wptr = fence->wptr;
fence->reemitted++;
} }
rcu_read_unlock(); rcu_read_unlock();
} while (last_seq != seq); } while (last_seq != seq);

24
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c
View File

@ -318,12 +318,36 @@ void isp_kernel_buffer_free(void **buf_obj, u64 *gpu_addr, void **cpu_addr)
} }
EXPORT_SYMBOL(isp_kernel_buffer_free); EXPORT_SYMBOL(isp_kernel_buffer_free);
static int isp_resume(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_isp *isp = &adev->isp;
if (isp->funcs->hw_resume)
return isp->funcs->hw_resume(isp);
return -ENODEV;
}
static int isp_suspend(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_isp *isp = &adev->isp;
if (isp->funcs->hw_suspend)
return isp->funcs->hw_suspend(isp);
return -ENODEV;
}
static const struct amd_ip_funcs isp_ip_funcs = { static const struct amd_ip_funcs isp_ip_funcs = {
.name = "isp_ip", .name = "isp_ip",
.early_init = isp_early_init, .early_init = isp_early_init,
.hw_init = isp_hw_init, .hw_init = isp_hw_init,
.hw_fini = isp_hw_fini, .hw_fini = isp_hw_fini,
.is_idle = isp_is_idle, .is_idle = isp_is_idle,
.suspend = isp_suspend,
.resume = isp_resume,
.set_clockgating_state = isp_set_clockgating_state, .set_clockgating_state = isp_set_clockgating_state,
.set_powergating_state = isp_set_powergating_state, .set_powergating_state = isp_set_powergating_state,
}; };

2
drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h
View File

@ -38,6 +38,8 @@ struct amdgpu_isp;
struct isp_funcs { struct isp_funcs {
int (*hw_init)(struct amdgpu_isp *isp); int (*hw_init)(struct amdgpu_isp *isp);
int (*hw_fini)(struct amdgpu_isp *isp); int (*hw_fini)(struct amdgpu_isp *isp);
int (*hw_suspend)(struct amdgpu_isp *isp);
int (*hw_resume)(struct amdgpu_isp *isp);
}; };
struct amdgpu_isp { struct amdgpu_isp {

6
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -201,6 +201,9 @@ static enum amd_ip_block_type
type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
break; break;
case AMDGPU_HW_IP_VPE:
type = AMD_IP_BLOCK_TYPE_VPE;
break;
default: default:
type = AMD_IP_BLOCK_TYPE_NUM; type = AMD_IP_BLOCK_TYPE_NUM;
break; break;
@ -721,6 +724,9 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
case AMD_IP_BLOCK_TYPE_UVD: case AMD_IP_BLOCK_TYPE_UVD:
count = adev->uvd.num_uvd_inst; count = adev->uvd.num_uvd_inst;
break; break;
case AMD_IP_BLOCK_TYPE_VPE:
count = adev->vpe.num_instances;
break;
/* For all other IP block types not listed in the switch statement /* For all other IP block types not listed in the switch statement
* the ip status is valid here and the instance count is one. * the ip status is valid here and the instance count is one.
*/ */

7
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
View File

@ -144,10 +144,15 @@ struct amdgpu_fence {
struct amdgpu_ring *ring; struct amdgpu_ring *ring;
ktime_t start_timestamp; ktime_t start_timestamp;
/* wptr for the fence for resets */ /* wptr for the total submission for resets */
u64 wptr; u64 wptr;
/* fence context for resets */ /* fence context for resets */
u64 context; u64 context;
/* has this fence been reemitted */
unsigned int reemitted;
/* wptr for the fence for the submission */
u64 fence_wptr_start;
u64 fence_wptr_end;
}; };
extern const struct drm_sched_backend_ops amdgpu_sched_ops; extern const struct drm_sched_backend_ops amdgpu_sched_ops;

41
drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
View File

@ -26,6 +26,7 @@
*/ */
#include <linux/gpio/machine.h> #include <linux/gpio/machine.h>
#include <linux/pm_runtime.h>
#include "amdgpu.h" #include "amdgpu.h"
#include "isp_v4_1_1.h" #include "isp_v4_1_1.h"
@ -145,6 +146,9 @@ static int isp_genpd_add_device(struct device *dev, void *data)
return -ENODEV; return -ENODEV;
} }
/* The devices will be managed by the pm ops from the parent */
dev_pm_syscore_device(dev, true);
exit: exit:
/* Continue to add */ /* Continue to add */
return 0; return 0;
@ -177,12 +181,47 @@ static int isp_genpd_remove_device(struct device *dev, void *data)
drm_err(&adev->ddev, "Failed to remove dev from genpd %d\n", ret); drm_err(&adev->ddev, "Failed to remove dev from genpd %d\n", ret);
return -ENODEV; return -ENODEV;
} }
dev_pm_syscore_device(dev, false);
exit: exit:
/* Continue to remove */ /* Continue to remove */
return 0; return 0;
} }
static int isp_suspend_device(struct device *dev, void *data)
{
return pm_runtime_force_suspend(dev);
}
static int isp_resume_device(struct device *dev, void *data)
{
return pm_runtime_force_resume(dev);
}
static int isp_v4_1_1_hw_suspend(struct amdgpu_isp *isp)
{
int r;
r = device_for_each_child(isp->parent, NULL,
isp_suspend_device);
if (r)
dev_err(isp->parent, "failed to suspend hw devices (%d)\n", r);
return r;
}
static int isp_v4_1_1_hw_resume(struct amdgpu_isp *isp)
{
int r;
r = device_for_each_child(isp->parent, NULL,
isp_resume_device);
if (r)
dev_err(isp->parent, "failed to resume hw device (%d)\n", r);
return r;
}
static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp) static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)
{ {
const struct software_node *amd_camera_node, *isp4_node; const struct software_node *amd_camera_node, *isp4_node;
@ -369,6 +408,8 @@ static int isp_v4_1_1_hw_fini(struct amdgpu_isp *isp)
static const struct isp_funcs isp_v4_1_1_funcs = { static const struct isp_funcs isp_v4_1_1_funcs = {
.hw_init = isp_v4_1_1_hw_init, .hw_init = isp_v4_1_1_hw_init,
.hw_fini = isp_v4_1_1_hw_fini, .hw_fini = isp_v4_1_1_hw_fini,
.hw_suspend = isp_v4_1_1_hw_suspend,
.hw_resume = isp_v4_1_1_hw_resume,
}; };
void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp) void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp)

4
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
View File

@ -763,14 +763,14 @@ static enum bp_result bios_parser_encoder_control(
return BP_RESULT_FAILURE; return BP_RESULT_FAILURE;
return bp->cmd_tbl.dac1_encoder_control( return bp->cmd_tbl.dac1_encoder_control(
bp, cntl->action == ENCODER_CONTROL_ENABLE, bp, cntl->action,
cntl->pixel_clock, ATOM_DAC1_PS2); cntl->pixel_clock, ATOM_DAC1_PS2);
} else if (cntl->engine_id == ENGINE_ID_DACB) { } else if (cntl->engine_id == ENGINE_ID_DACB) {
if (!bp->cmd_tbl.dac2_encoder_control) if (!bp->cmd_tbl.dac2_encoder_control)
return BP_RESULT_FAILURE; return BP_RESULT_FAILURE;
return bp->cmd_tbl.dac2_encoder_control( return bp->cmd_tbl.dac2_encoder_control(
bp, cntl->action == ENCODER_CONTROL_ENABLE, bp, cntl->action,
cntl->pixel_clock, ATOM_DAC1_PS2); cntl->pixel_clock, ATOM_DAC1_PS2);
} }

44
drivers/gpu/drm/amd/display/dc/bios/command_table.c
View File

@ -1797,7 +1797,30 @@ static enum bp_result select_crtc_source_v3(
&params.ucEncodeMode)) &params.ucEncodeMode))
return BP_RESULT_BADINPUT; return BP_RESULT_BADINPUT;
params.ucDstBpc = bp_params->bit_depth; switch (bp_params->color_depth) {
case COLOR_DEPTH_UNDEFINED:
params.ucDstBpc = PANEL_BPC_UNDEFINE;
break;
case COLOR_DEPTH_666:
params.ucDstBpc = PANEL_6BIT_PER_COLOR;
break;
default:
case COLOR_DEPTH_888:
params.ucDstBpc = PANEL_8BIT_PER_COLOR;
break;
case COLOR_DEPTH_101010:
params.ucDstBpc = PANEL_10BIT_PER_COLOR;
break;
case COLOR_DEPTH_121212:
params.ucDstBpc = PANEL_12BIT_PER_COLOR;
break;
case COLOR_DEPTH_141414:
dm_error("14-bit color not supported by SelectCRTC_Source v3\n");
break;
case COLOR_DEPTH_161616:
params.ucDstBpc = PANEL_16BIT_PER_COLOR;
break;
}
if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params)) if (EXEC_BIOS_CMD_TABLE(SelectCRTC_Source, params))
result = BP_RESULT_OK; result = BP_RESULT_OK;
@ -1815,12 +1838,12 @@ static enum bp_result select_crtc_source_v3(
static enum bp_result dac1_encoder_control_v1( static enum bp_result dac1_encoder_control_v1(
struct bios_parser *bp, struct bios_parser *bp,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard); uint8_t dac_standard);
static enum bp_result dac2_encoder_control_v1( static enum bp_result dac2_encoder_control_v1(
struct bios_parser *bp, struct bios_parser *bp,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard); uint8_t dac_standard);
@ -1846,12 +1869,15 @@ static void init_dac_encoder_control(struct bios_parser *bp)
static void dac_encoder_control_prepare_params( static void dac_encoder_control_prepare_params(
DAC_ENCODER_CONTROL_PS_ALLOCATION *params, DAC_ENCODER_CONTROL_PS_ALLOCATION *params,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard) uint8_t dac_standard)
{ {
params->ucDacStandard = dac_standard; params->ucDacStandard = dac_standard;
if (enable) if (action == ENCODER_CONTROL_SETUP ||
action == ENCODER_CONTROL_INIT)
params->ucAction = ATOM_ENCODER_INIT;
else if (action == ENCODER_CONTROL_ENABLE)
params->ucAction = ATOM_ENABLE; params->ucAction = ATOM_ENABLE;
else else
params->ucAction = ATOM_DISABLE; params->ucAction = ATOM_DISABLE;
@ -1864,7 +1890,7 @@ static void dac_encoder_control_prepare_params(
static enum bp_result dac1_encoder_control_v1( static enum bp_result dac1_encoder_control_v1(
struct bios_parser *bp, struct bios_parser *bp,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard) uint8_t dac_standard)
{ {
@ -1873,7 +1899,7 @@ static enum bp_result dac1_encoder_control_v1(
dac_encoder_control_prepare_params( dac_encoder_control_prepare_params(
&params, &params,
enable, action,
pixel_clock, pixel_clock,
dac_standard); dac_standard);
@ -1885,7 +1911,7 @@ static enum bp_result dac1_encoder_control_v1(
static enum bp_result dac2_encoder_control_v1( static enum bp_result dac2_encoder_control_v1(
struct bios_parser *bp, struct bios_parser *bp,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard) uint8_t dac_standard)
{ {
@ -1894,7 +1920,7 @@ static enum bp_result dac2_encoder_control_v1(
dac_encoder_control_prepare_params( dac_encoder_control_prepare_params(
&params, &params,
enable, action,
pixel_clock, pixel_clock,
dac_standard); dac_standard);

4
drivers/gpu/drm/amd/display/dc/bios/command_table.h
View File

@ -57,12 +57,12 @@ struct cmd_tbl {
struct bp_crtc_source_select *bp_params); struct bp_crtc_source_select *bp_params);
enum bp_result (*dac1_encoder_control)( enum bp_result (*dac1_encoder_control)(
struct bios_parser *bp, struct bios_parser *bp,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard); uint8_t dac_standard);
enum bp_result (*dac2_encoder_control)( enum bp_result (*dac2_encoder_control)(
struct bios_parser *bp, struct bios_parser *bp,
bool enable, enum bp_encoder_control_action action,
uint32_t pixel_clock, uint32_t pixel_clock,
uint8_t dac_standard); uint8_t dac_standard);
enum bp_result (*dac1_output_control)( enum bp_result (*dac1_output_control)(

4
drivers/gpu/drm/amd/display/dc/dml/Makefile
View File

@ -30,7 +30,11 @@ dml_rcflags := $(CC_FLAGS_NO_FPU)
ifneq ($(CONFIG_FRAME_WARN),0) ifneq ($(CONFIG_FRAME_WARN),0)
ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y)
ifeq ($(CONFIG_CC_IS_CLANG)$(CONFIG_COMPILE_TEST),yy)
frame_warn_limit := 4096
else
frame_warn_limit := 3072 frame_warn_limit := 3072
endif
else else
frame_warn_limit := 2048 frame_warn_limit := 2048
endif endif

545
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
View File

@ -77,32 +77,14 @@ static unsigned int dscceComputeDelay(
static unsigned int dscComputeDelay( static unsigned int dscComputeDelay(
enum output_format_class pixelFormat, enum output_format_class pixelFormat,
enum output_encoder_class Output); enum output_encoder_class Output);
// Super monster function with some 45 argument
static bool CalculatePrefetchSchedule( static bool CalculatePrefetchSchedule(
struct display_mode_lib *mode_lib, struct display_mode_lib *mode_lib,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, unsigned int k,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
Pipe *myPipe, Pipe *myPipe,
unsigned int DSCDelay, unsigned int DSCDelay,
double DPPCLKDelaySubtotalPlusCNVCFormater,
double DPPCLKDelaySCL,
double DPPCLKDelaySCLLBOnly,
double DPPCLKDelayCNVCCursor,
double DISPCLKDelaySubtotal,
unsigned int DPP_RECOUT_WIDTH, unsigned int DPP_RECOUT_WIDTH,
enum output_format_class OutputFormat,
unsigned int MaxInterDCNTileRepeaters,
unsigned int VStartup, unsigned int VStartup,
unsigned int MaxVStartup, unsigned int MaxVStartup,
unsigned int GPUVMPageTableLevels,
bool GPUVMEnable,
bool HostVMEnable,
unsigned int HostVMMaxNonCachedPageTableLevels,
double HostVMMinPageSize,
bool DynamicMetadataEnable,
bool DynamicMetadataVMEnabled,
int DynamicMetadataLinesBeforeActiveRequired,
unsigned int DynamicMetadataTransmittedBytes,
double UrgentLatency, double UrgentLatency,
double UrgentExtraLatency, double UrgentExtraLatency,
double TCalc, double TCalc,
@ -116,7 +98,6 @@ static bool CalculatePrefetchSchedule(
unsigned int MaxNumSwathY, unsigned int MaxNumSwathY,
double PrefetchSourceLinesC, double PrefetchSourceLinesC,
unsigned int SwathWidthC, unsigned int SwathWidthC,
int BytePerPixelC,
double VInitPreFillC, double VInitPreFillC,
unsigned int MaxNumSwathC, unsigned int MaxNumSwathC,
long swath_width_luma_ub, long swath_width_luma_ub,
@ -124,9 +105,6 @@ static bool CalculatePrefetchSchedule(
unsigned int SwathHeightY, unsigned int SwathHeightY,
unsigned int SwathHeightC, unsigned int SwathHeightC,
double TWait, double TWait,
bool ProgressiveToInterlaceUnitInOPP,
double *DSTXAfterScaler,
double *DSTYAfterScaler,
double *DestinationLinesForPrefetch, double *DestinationLinesForPrefetch,
double *PrefetchBandwidth, double *PrefetchBandwidth,
double *DestinationLinesToRequestVMInVBlank, double *DestinationLinesToRequestVMInVBlank,
@ -135,14 +113,7 @@ static bool CalculatePrefetchSchedule(
double *VRatioPrefetchC, double *VRatioPrefetchC,
double *RequiredPrefetchPixDataBWLuma, double *RequiredPrefetchPixDataBWLuma,
double *RequiredPrefetchPixDataBWChroma, double *RequiredPrefetchPixDataBWChroma,
bool *NotEnoughTimeForDynamicMetadata, bool *NotEnoughTimeForDynamicMetadata);
double *Tno_bw,
double *prefetch_vmrow_bw,
double *Tdmdl_vm,
double *Tdmdl,
unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix);
static double RoundToDFSGranularityUp(double Clock, double VCOSpeed); static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
static double RoundToDFSGranularityDown(double Clock, double VCOSpeed); static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
static void CalculateDCCConfiguration( static void CalculateDCCConfiguration(
@ -294,62 +265,23 @@ static void CalculateDynamicMetadataParameters(
static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateWatermarksAndDRAMSpeedChangeSupport(
struct display_mode_lib *mode_lib, struct display_mode_lib *mode_lib,
unsigned int PrefetchMode, unsigned int PrefetchMode,
unsigned int NumberOfActivePlanes,
unsigned int MaxLineBufferLines,
unsigned int LineBufferSize,
unsigned int DPPOutputBufferPixels,
unsigned int DETBufferSizeInKByte,
unsigned int WritebackInterfaceBufferSize,
double DCFCLK, double DCFCLK,
double ReturnBW, double ReturnBW,
bool GPUVMEnable,
unsigned int dpte_group_bytes[],
unsigned int MetaChunkSize,
double UrgentLatency, double UrgentLatency,
double ExtraLatency, double ExtraLatency,
double WritebackLatency,
double WritebackChunkSize,
double SOCCLK, double SOCCLK,
double DRAMClockChangeLatency,
double SRExitTime,
double SREnterPlusExitTime,
double DCFCLKDeepSleep, double DCFCLKDeepSleep,
unsigned int DPPPerPlane[], unsigned int DPPPerPlane[],
bool DCCEnable[],
double DPPCLK[], double DPPCLK[],
unsigned int DETBufferSizeY[], unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[], unsigned int DETBufferSizeC[],
unsigned int SwathHeightY[], unsigned int SwathHeightY[],
unsigned int SwathHeightC[], unsigned int SwathHeightC[],
unsigned int LBBitPerPixel[],
double SwathWidthY[], double SwathWidthY[],
double SwathWidthC[], double SwathWidthC[],
double HRatio[],
double HRatioChroma[],
unsigned int vtaps[],
unsigned int VTAPsChroma[],
double VRatio[],
double VRatioChroma[],
unsigned int HTotal[],
double PixelClock[],
unsigned int BlendingAndTiming[],
double BytePerPixelDETY[], double BytePerPixelDETY[],
double BytePerPixelDETC[], double BytePerPixelDETC[],
double DSTXAfterScaler[], enum clock_change_support *DRAMClockChangeSupport);
double DSTYAfterScaler[],
bool WritebackEnable[],
enum source_format_class WritebackPixelFormat[],
double WritebackDestinationWidth[],
double WritebackDestinationHeight[],
double WritebackSourceHeight[],
enum clock_change_support *DRAMClockChangeSupport,
double *UrgentWatermark,
double *WritebackUrgentWatermark,
double *DRAMClockChangeWatermark,
double *WritebackDRAMClockChangeWatermark,
double *StutterExitWatermark,
double *StutterEnterPlusExitWatermark,
double *MinActiveDRAMClockChangeLatencySupported);
static void CalculateDCFCLKDeepSleep( static void CalculateDCFCLKDeepSleep(
struct display_mode_lib *mode_lib, struct display_mode_lib *mode_lib,
unsigned int NumberOfActivePlanes, unsigned int NumberOfActivePlanes,
@ -810,29 +742,12 @@ static unsigned int dscComputeDelay(enum output_format_class pixelFormat, enum o
static bool CalculatePrefetchSchedule( static bool CalculatePrefetchSchedule(
struct display_mode_lib *mode_lib, struct display_mode_lib *mode_lib,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, unsigned int k,
double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
Pipe *myPipe, Pipe *myPipe,
unsigned int DSCDelay, unsigned int DSCDelay,
double DPPCLKDelaySubtotalPlusCNVCFormater,
double DPPCLKDelaySCL,
double DPPCLKDelaySCLLBOnly,
double DPPCLKDelayCNVCCursor,
double DISPCLKDelaySubtotal,
unsigned int DPP_RECOUT_WIDTH, unsigned int DPP_RECOUT_WIDTH,
enum output_format_class OutputFormat,
unsigned int MaxInterDCNTileRepeaters,
unsigned int VStartup, unsigned int VStartup,
unsigned int MaxVStartup, unsigned int MaxVStartup,
unsigned int GPUVMPageTableLevels,
bool GPUVMEnable,
bool HostVMEnable,
unsigned int HostVMMaxNonCachedPageTableLevels,
double HostVMMinPageSize,
bool DynamicMetadataEnable,
bool DynamicMetadataVMEnabled,
int DynamicMetadataLinesBeforeActiveRequired,
unsigned int DynamicMetadataTransmittedBytes,
double UrgentLatency, double UrgentLatency,
double UrgentExtraLatency, double UrgentExtraLatency,
double TCalc, double TCalc,
@ -846,7 +761,6 @@ static bool CalculatePrefetchSchedule(
unsigned int MaxNumSwathY, unsigned int MaxNumSwathY,
double PrefetchSourceLinesC, double PrefetchSourceLinesC,
unsigned int SwathWidthC, unsigned int SwathWidthC,
int BytePerPixelC,
double VInitPreFillC, double VInitPreFillC,
unsigned int MaxNumSwathC, unsigned int MaxNumSwathC,
long swath_width_luma_ub, long swath_width_luma_ub,
@ -854,9 +768,6 @@ static bool CalculatePrefetchSchedule(
unsigned int SwathHeightY, unsigned int SwathHeightY,
unsigned int SwathHeightC, unsigned int SwathHeightC,
double TWait, double TWait,
bool ProgressiveToInterlaceUnitInOPP,
double *DSTXAfterScaler,
double *DSTYAfterScaler,
double *DestinationLinesForPrefetch, double *DestinationLinesForPrefetch,
double *PrefetchBandwidth, double *PrefetchBandwidth,
double *DestinationLinesToRequestVMInVBlank, double *DestinationLinesToRequestVMInVBlank,
@ -865,15 +776,10 @@ static bool CalculatePrefetchSchedule(
double *VRatioPrefetchC, double *VRatioPrefetchC,
double *RequiredPrefetchPixDataBWLuma, double *RequiredPrefetchPixDataBWLuma,
double *RequiredPrefetchPixDataBWChroma, double *RequiredPrefetchPixDataBWChroma,
bool *NotEnoughTimeForDynamicMetadata, bool *NotEnoughTimeForDynamicMetadata)
double *Tno_bw,
double *prefetch_vmrow_bw,
double *Tdmdl_vm,
double *Tdmdl,
unsigned int *VUpdateOffsetPix,
double *VUpdateWidthPix,
double *VReadyOffsetPix)
{ {
struct vba_vars_st *v = &mode_lib->vba;
double DPPCLKDelaySubtotalPlusCNVCFormater = v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater;
bool MyError = false; bool MyError = false;
unsigned int DPPCycles = 0, DISPCLKCycles = 0; unsigned int DPPCycles = 0, DISPCLKCycles = 0;
double DSTTotalPixelsAfterScaler = 0; double DSTTotalPixelsAfterScaler = 0;
@ -905,26 +811,26 @@ static bool CalculatePrefetchSchedule(
double Tdmec = 0; double Tdmec = 0;
double Tdmsks = 0; double Tdmsks = 0;
if (GPUVMEnable == true && HostVMEnable == true) { if (v->GPUVMEnable == true && v->HostVMEnable == true) {
HostVMInefficiencyFactor = PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; HostVMInefficiencyFactor = v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData / v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly;
HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels;
} else { } else {
HostVMInefficiencyFactor = 1; HostVMInefficiencyFactor = 1;
HostVMDynamicLevelsTrips = 0; HostVMDynamicLevelsTrips = 0;
} }
CalculateDynamicMetadataParameters( CalculateDynamicMetadataParameters(
MaxInterDCNTileRepeaters, v->MaxInterDCNTileRepeaters,
myPipe->DPPCLK, myPipe->DPPCLK,
myPipe->DISPCLK, myPipe->DISPCLK,
myPipe->DCFCLKDeepSleep, myPipe->DCFCLKDeepSleep,
myPipe->PixelClock, myPipe->PixelClock,
myPipe->HTotal, myPipe->HTotal,
myPipe->VBlank, myPipe->VBlank,
DynamicMetadataTransmittedBytes, v->DynamicMetadataTransmittedBytes[k],
DynamicMetadataLinesBeforeActiveRequired, v->DynamicMetadataLinesBeforeActiveRequired[k],
myPipe->InterlaceEnable, myPipe->InterlaceEnable,
ProgressiveToInterlaceUnitInOPP, v->ProgressiveToInterlaceUnitInOPP,
&Tsetup, &Tsetup,
&Tdmbf, &Tdmbf,
&Tdmec, &Tdmec,
@ -932,16 +838,16 @@ static bool CalculatePrefetchSchedule(
LineTime = myPipe->HTotal / myPipe->PixelClock; LineTime = myPipe->HTotal / myPipe->PixelClock;
trip_to_mem = UrgentLatency; trip_to_mem = UrgentLatency;
Tvm_trips = UrgentExtraLatency + trip_to_mem * (GPUVMPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1); Tvm_trips = UrgentExtraLatency + trip_to_mem * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1);
if (DynamicMetadataVMEnabled == true && GPUVMEnable == true) { if (v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true) {
*Tdmdl = TWait + Tvm_trips + trip_to_mem; v->Tdmdl[k] = TWait + Tvm_trips + trip_to_mem;
} else { } else {
*Tdmdl = TWait + UrgentExtraLatency; v->Tdmdl[k] = TWait + UrgentExtraLatency;
} }
if (DynamicMetadataEnable == true) { if (v->DynamicMetadataEnable[k] == true) {
if (VStartup * LineTime < Tsetup + *Tdmdl + Tdmbf + Tdmec + Tdmsks) { if (VStartup * LineTime < Tsetup + v->Tdmdl[k] + Tdmbf + Tdmec + Tdmsks) {
*NotEnoughTimeForDynamicMetadata = true; *NotEnoughTimeForDynamicMetadata = true;
} else { } else {
*NotEnoughTimeForDynamicMetadata = false; *NotEnoughTimeForDynamicMetadata = false;
@ -949,39 +855,39 @@ static bool CalculatePrefetchSchedule(
dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf); dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf);
dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec); dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec);
dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks); dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks);
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl); dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
} }
} else { } else {
*NotEnoughTimeForDynamicMetadata = false; *NotEnoughTimeForDynamicMetadata = false;
} }
*Tdmdl_vm = (DynamicMetadataEnable == true && DynamicMetadataVMEnabled == true && GPUVMEnable == true ? TWait + Tvm_trips : 0); v->Tdmdl_vm[k] = (v->DynamicMetadataEnable[k] == true && v->DynamicMetadataVMEnabled == true && v->GPUVMEnable == true ? TWait + Tvm_trips : 0);
if (myPipe->ScalerEnabled) if (myPipe->ScalerEnabled)
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCL; DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCL;
else else
DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + DPPCLKDelaySCLLBOnly; DPPCycles = DPPCLKDelaySubtotalPlusCNVCFormater + v->DPPCLKDelaySCLLBOnly;
DPPCycles = DPPCycles + myPipe->NumberOfCursors * DPPCLKDelayCNVCCursor; DPPCycles = DPPCycles + myPipe->NumberOfCursors * v->DPPCLKDelayCNVCCursor;
DISPCLKCycles = DISPCLKDelaySubtotal; DISPCLKCycles = v->DISPCLKDelaySubtotal;
if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0) if (myPipe->DPPCLK == 0.0 || myPipe->DISPCLK == 0.0)
return true; return true;
*DSTXAfterScaler = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK v->DSTXAfterScaler[k] = DPPCycles * myPipe->PixelClock / myPipe->DPPCLK + DISPCLKCycles * myPipe->PixelClock / myPipe->DISPCLK
+ DSCDelay; + DSCDelay;
*DSTXAfterScaler = *DSTXAfterScaler + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH; v->DSTXAfterScaler[k] = v->DSTXAfterScaler[k] + ((myPipe->ODMCombineEnabled)?18:0) + (myPipe->DPPPerPlane - 1) * DPP_RECOUT_WIDTH;
if (OutputFormat == dm_420 || (myPipe->InterlaceEnable && ProgressiveToInterlaceUnitInOPP)) if (v->OutputFormat[k] == dm_420 || (myPipe->InterlaceEnable && v->ProgressiveToInterlaceUnitInOPP))
*DSTYAfterScaler = 1; v->DSTYAfterScaler[k] = 1;
else else
*DSTYAfterScaler = 0; v->DSTYAfterScaler[k] = 0;
DSTTotalPixelsAfterScaler = *DSTYAfterScaler * myPipe->HTotal + *DSTXAfterScaler; DSTTotalPixelsAfterScaler = v->DSTYAfterScaler[k] * myPipe->HTotal + v->DSTXAfterScaler[k];
*DSTYAfterScaler = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1); v->DSTYAfterScaler[k] = dml_floor(DSTTotalPixelsAfterScaler / myPipe->HTotal, 1);
*DSTXAfterScaler = DSTTotalPixelsAfterScaler - ((double) (*DSTYAfterScaler * myPipe->HTotal)); v->DSTXAfterScaler[k] = DSTTotalPixelsAfterScaler - ((double) (v->DSTYAfterScaler[k] * myPipe->HTotal));
MyError = false; MyError = false;
@ -990,33 +896,33 @@ static bool CalculatePrefetchSchedule(
Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime; Tvm_trips_rounded = dml_ceil(4.0 * Tvm_trips / LineTime, 1) / 4 * LineTime;
Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime; Tr0_trips_rounded = dml_ceil(4.0 * Tr0_trips / LineTime, 1) / 4 * LineTime;
if (GPUVMEnable) { if (v->GPUVMEnable) {
if (GPUVMPageTableLevels >= 3) { if (v->GPUVMMaxPageTableLevels >= 3) {
*Tno_bw = UrgentExtraLatency + trip_to_mem * ((GPUVMPageTableLevels - 2) - 1); v->Tno_bw[k] = UrgentExtraLatency + trip_to_mem * ((v->GPUVMMaxPageTableLevels - 2) - 1);
} else } else
*Tno_bw = 0; v->Tno_bw[k] = 0;
} else if (!myPipe->DCCEnable) } else if (!myPipe->DCCEnable)
*Tno_bw = LineTime; v->Tno_bw[k] = LineTime;
else else
*Tno_bw = LineTime / 4; v->Tno_bw[k] = LineTime / 4;
dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, *Tdmdl)) / LineTime dst_y_prefetch_equ = VStartup - (Tsetup + dml_max(TWait + TCalc, v->Tdmdl[k])) / LineTime
- (*DSTYAfterScaler + *DSTXAfterScaler / myPipe->HTotal); - (v->DSTYAfterScaler[k] + v->DSTXAfterScaler[k] / myPipe->HTotal);
dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH dst_y_prefetch_equ = dml_min(dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH
Lsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC); Lsw_oto = dml_max(PrefetchSourceLinesY, PrefetchSourceLinesC);
Tsw_oto = Lsw_oto * LineTime; Tsw_oto = Lsw_oto * LineTime;
prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * BytePerPixelC) / Tsw_oto; prefetch_bw_oto = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k]) / Tsw_oto;
if (GPUVMEnable == true) { if (v->GPUVMEnable == true) {
Tvm_oto = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto, Tvm_oto = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_oto,
Tvm_trips, Tvm_trips,
LineTime / 4.0); LineTime / 4.0);
} else } else
Tvm_oto = LineTime / 4.0; Tvm_oto = LineTime / 4.0;
if ((GPUVMEnable == true || myPipe->DCCEnable == true)) { if ((v->GPUVMEnable == true || myPipe->DCCEnable == true)) {
Tr0_oto = dml_max3( Tr0_oto = dml_max3(
(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto, (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_oto,
LineTime - Tvm_oto, LineTime / 4); LineTime - Tvm_oto, LineTime / 4);
@ -1042,10 +948,10 @@ static bool CalculatePrefetchSchedule(
dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf); dml_print("DML: Tdmbf: %fus - time for dmd transfer from dchub to dio output buffer\n", Tdmbf);
dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec); dml_print("DML: Tdmec: %fus - time dio takes to transfer dmd\n", Tdmec);
dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks); dml_print("DML: Tdmsks: %fus - time before active dmd must complete transmission at dio\n", Tdmsks);
dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", *Tdmdl_vm); dml_print("DML: Tdmdl_vm: %fus - time for vm stages of dmd \n", v->Tdmdl_vm[k]);
dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", *Tdmdl); dml_print("DML: Tdmdl: %fus - time for fabric to become ready and fetch dmd \n", v->Tdmdl[k]);
dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", *DSTXAfterScaler); dml_print("DML: dst_x_after_scl: %f pixels - number of pixel clocks pipeline and buffer delay after scaler \n", v->DSTXAfterScaler[k]);
dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)*DSTYAfterScaler); dml_print("DML: dst_y_after_scl: %d lines - number of lines of pipeline and buffer delay after scaler \n", (int)v->DSTYAfterScaler[k]);
*PrefetchBandwidth = 0; *PrefetchBandwidth = 0;
*DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0;
@ -1059,26 +965,26 @@ static bool CalculatePrefetchSchedule(
double PrefetchBandwidth3 = 0; double PrefetchBandwidth3 = 0;
double PrefetchBandwidth4 = 0; double PrefetchBandwidth4 = 0;
if (Tpre_rounded - *Tno_bw > 0) if (Tpre_rounded - v->Tno_bw[k] > 0)
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte
+ 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor
+ PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY
+ PrefetchSourceLinesC * swath_width_chroma_ub * BytePerPixelC) + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
/ (Tpre_rounded - *Tno_bw); / (Tpre_rounded - v->Tno_bw[k]);
else else
PrefetchBandwidth1 = 0; PrefetchBandwidth1 = 0;
if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - *Tno_bw) > 0) { if (VStartup == MaxVStartup && (PrefetchBandwidth1 > 4 * prefetch_bw_oto) && (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]) > 0) {
PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - *Tno_bw); PrefetchBandwidth1 = (PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor + 2 * MetaRowByte + 2 * PixelPTEBytesPerRow * HostVMInefficiencyFactor) / (Tpre_rounded - Tsw_oto / 4 - 0.75 * LineTime - v->Tno_bw[k]);
} }
if (Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded > 0) if (Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded > 0)
PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame * PrefetchBandwidth2 = (PDEAndMetaPTEBytesFrame *
HostVMInefficiencyFactor + PrefetchSourceLinesY * HostVMInefficiencyFactor + PrefetchSourceLinesY *
swath_width_luma_ub * BytePerPixelY + swath_width_luma_ub * BytePerPixelY +
PrefetchSourceLinesC * swath_width_chroma_ub * PrefetchSourceLinesC * swath_width_chroma_ub *
BytePerPixelC) / v->BytePerPixelC[k]) /
(Tpre_rounded - *Tno_bw - 2 * Tr0_trips_rounded); (Tpre_rounded - v->Tno_bw[k] - 2 * Tr0_trips_rounded);
else else
PrefetchBandwidth2 = 0; PrefetchBandwidth2 = 0;
@ -1086,7 +992,7 @@ static bool CalculatePrefetchSchedule(
PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow * PrefetchBandwidth3 = (2 * MetaRowByte + 2 * PixelPTEBytesPerRow *
HostVMInefficiencyFactor + PrefetchSourceLinesY * HostVMInefficiencyFactor + PrefetchSourceLinesY *
swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC *
swath_width_chroma_ub * BytePerPixelC) / (Tpre_rounded - swath_width_chroma_ub * v->BytePerPixelC[k]) / (Tpre_rounded -
Tvm_trips_rounded); Tvm_trips_rounded);
else else
PrefetchBandwidth3 = 0; PrefetchBandwidth3 = 0;
@ -1096,7 +1002,7 @@ static bool CalculatePrefetchSchedule(
} }
if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0) if (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded > 0)
PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * BytePerPixelC) PrefetchBandwidth4 = (PrefetchSourceLinesY * swath_width_luma_ub * BytePerPixelY + PrefetchSourceLinesC * swath_width_chroma_ub * v->BytePerPixelC[k])
/ (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded); / (Tpre_rounded - Tvm_trips_rounded - 2 * Tr0_trips_rounded);
else else
PrefetchBandwidth4 = 0; PrefetchBandwidth4 = 0;
@ -1107,7 +1013,7 @@ static bool CalculatePrefetchSchedule(
bool Case3OK; bool Case3OK;
if (PrefetchBandwidth1 > 0) { if (PrefetchBandwidth1 > 0) {
if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1 if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth1
>= Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= Tr0_trips_rounded) { >= Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth1 >= Tr0_trips_rounded) {
Case1OK = true; Case1OK = true;
} else { } else {
@ -1118,7 +1024,7 @@ static bool CalculatePrefetchSchedule(
} }
if (PrefetchBandwidth2 > 0) { if (PrefetchBandwidth2 > 0) {
if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2 if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth2
>= Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < Tr0_trips_rounded) { >= Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth2 < Tr0_trips_rounded) {
Case2OK = true; Case2OK = true;
} else { } else {
@ -1129,7 +1035,7 @@ static bool CalculatePrefetchSchedule(
} }
if (PrefetchBandwidth3 > 0) { if (PrefetchBandwidth3 > 0) {
if (*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3 if (v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / PrefetchBandwidth3
< Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= Tr0_trips_rounded) { < Tvm_trips_rounded && (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / PrefetchBandwidth3 >= Tr0_trips_rounded) {
Case3OK = true; Case3OK = true;
} else { } else {
@ -1152,13 +1058,13 @@ static bool CalculatePrefetchSchedule(
dml_print("DML: prefetch_bw_equ: %f\n", prefetch_bw_equ); dml_print("DML: prefetch_bw_equ: %f\n", prefetch_bw_equ);
if (prefetch_bw_equ > 0) { if (prefetch_bw_equ > 0) {
if (GPUVMEnable) { if (v->GPUVMEnable) {
Tvm_equ = dml_max3(*Tno_bw + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4); Tvm_equ = dml_max3(v->Tno_bw[k] + PDEAndMetaPTEBytesFrame * HostVMInefficiencyFactor / prefetch_bw_equ, Tvm_trips, LineTime / 4);
} else { } else {
Tvm_equ = LineTime / 4; Tvm_equ = LineTime / 4;
} }
if ((GPUVMEnable || myPipe->DCCEnable)) { if ((v->GPUVMEnable || myPipe->DCCEnable)) {
Tr0_equ = dml_max4( Tr0_equ = dml_max4(
(MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_equ, (MetaRowByte + PixelPTEBytesPerRow * HostVMInefficiencyFactor) / prefetch_bw_equ,
Tr0_trips, Tr0_trips,
@ -1227,7 +1133,7 @@ static bool CalculatePrefetchSchedule(
} }
*RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData * BytePerPixelY * swath_width_luma_ub / LineTime; *RequiredPrefetchPixDataBWLuma = (double) PrefetchSourceLinesY / LinesToRequestPrefetchPixelData * BytePerPixelY * swath_width_luma_ub / LineTime;
*RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * BytePerPixelC * swath_width_chroma_ub / LineTime; *RequiredPrefetchPixDataBWChroma = (double) PrefetchSourceLinesC / LinesToRequestPrefetchPixelData * v->BytePerPixelC[k] * swath_width_chroma_ub / LineTime;
} else { } else {
MyError = true; MyError = true;
dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
@ -1243,9 +1149,9 @@ static bool CalculatePrefetchSchedule(
dml_print("DML: Tr0: %fus - time to fetch first row of data pagetables and first row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank); dml_print("DML: Tr0: %fus - time to fetch first row of data pagetables and first row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank);
dml_print("DML: Tr1: %fus - time to fetch second row of data pagetables and second row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank); dml_print("DML: Tr1: %fus - time to fetch second row of data pagetables and second row of meta data (done in parallel)\n", TimeForFetchingRowInVBlank);
dml_print("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n", (double)LinesToRequestPrefetchPixelData * LineTime); dml_print("DML: Tsw: %fus = time to fetch enough pixel data and cursor data to feed the scalers init position and detile\n", (double)LinesToRequestPrefetchPixelData * LineTime);
dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (*DSTYAfterScaler + ((*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime); dml_print("DML: To: %fus - time for propagation from scaler to optc\n", (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime);
dml_print("DML: Tvstartup - Tsetup - Tcalc - Twait - Tpre - To > 0\n"); dml_print("DML: Tvstartup - Tsetup - Tcalc - Twait - Tpre - To > 0\n");
dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (*DSTYAfterScaler + ((*DSTXAfterScaler) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup); dml_print("DML: Tslack(pre): %fus - time left over in schedule\n", VStartup * LineTime - TimeForFetchingMetaPTE - 2 * TimeForFetchingRowInVBlank - (v->DSTYAfterScaler[k] + ((v->DSTXAfterScaler[k]) / (double) myPipe->HTotal)) * LineTime - TWait - TCalc - Tsetup);
dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow); dml_print("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %d\n", PixelPTEBytesPerRow);
} else { } else {
@ -1276,7 +1182,7 @@ static bool CalculatePrefetchSchedule(
dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__); dml_print("DML: MyErr set %s:%d\n", __FILE__, __LINE__);
} }
*prefetch_vmrow_bw = dml_max(prefetch_vm_bw, prefetch_row_bw); v->prefetch_vmrow_bw[k] = dml_max(prefetch_vm_bw, prefetch_row_bw);
} }
if (MyError) { if (MyError) {
@ -2437,30 +2343,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->ErrorResult[k] = CalculatePrefetchSchedule( v->ErrorResult[k] = CalculatePrefetchSchedule(
mode_lib, mode_lib,
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, k,
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
&myPipe, &myPipe,
v->DSCDelay[k], v->DSCDelay[k],
v->DPPCLKDelaySubtotal
+ v->DPPCLKDelayCNVCFormater,
v->DPPCLKDelaySCL,
v->DPPCLKDelaySCLLBOnly,
v->DPPCLKDelayCNVCCursor,
v->DISPCLKDelaySubtotal,
(unsigned int) (v->SwathWidthY[k] / v->HRatio[k]), (unsigned int) (v->SwathWidthY[k] / v->HRatio[k]),
v->OutputFormat[k],
v->MaxInterDCNTileRepeaters,
dml_min(v->VStartupLines, v->MaxVStartupLines[k]), dml_min(v->VStartupLines, v->MaxVStartupLines[k]),
v->MaxVStartupLines[k], v->MaxVStartupLines[k],
v->GPUVMMaxPageTableLevels,
v->GPUVMEnable,
v->HostVMEnable,
v->HostVMMaxNonCachedPageTableLevels,
v->HostVMMinPageSize,
v->DynamicMetadataEnable[k],
v->DynamicMetadataVMEnabled,
v->DynamicMetadataLinesBeforeActiveRequired[k],
v->DynamicMetadataTransmittedBytes[k],
v->UrgentLatency, v->UrgentLatency,
v->UrgentExtraLatency, v->UrgentExtraLatency,
v->TCalc, v->TCalc,
@ -2474,7 +2362,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->MaxNumSwathY[k], v->MaxNumSwathY[k],
v->PrefetchSourceLinesC[k], v->PrefetchSourceLinesC[k],
v->SwathWidthC[k], v->SwathWidthC[k],
v->BytePerPixelC[k],
v->VInitPreFillC[k], v->VInitPreFillC[k],
v->MaxNumSwathC[k], v->MaxNumSwathC[k],
v->swath_width_luma_ub[k], v->swath_width_luma_ub[k],
@ -2482,9 +2369,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
v->SwathHeightY[k], v->SwathHeightY[k],
v->SwathHeightC[k], v->SwathHeightC[k],
TWait, TWait,
v->ProgressiveToInterlaceUnitInOPP,
&v->DSTXAfterScaler[k],
&v->DSTYAfterScaler[k],
&v->DestinationLinesForPrefetch[k], &v->DestinationLinesForPrefetch[k],
&v->PrefetchBandwidth[k], &v->PrefetchBandwidth[k],
&v->DestinationLinesToRequestVMInVBlank[k], &v->DestinationLinesToRequestVMInVBlank[k],
@ -2493,14 +2377,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
&v->VRatioPrefetchC[k], &v->VRatioPrefetchC[k],
&v->RequiredPrefetchPixDataBWLuma[k], &v->RequiredPrefetchPixDataBWLuma[k],
&v->RequiredPrefetchPixDataBWChroma[k], &v->RequiredPrefetchPixDataBWChroma[k],
&v->NotEnoughTimeForDynamicMetadata[k], &v->NotEnoughTimeForDynamicMetadata[k]);
&v->Tno_bw[k],
&v->prefetch_vmrow_bw[k],
&v->Tdmdl_vm[k],
&v->Tdmdl[k],
&v->VUpdateOffsetPix[k],
&v->VUpdateWidthPix[k],
&v->VReadyOffsetPix[k]);
if (v->BlendingAndTiming[k] == k) { if (v->BlendingAndTiming[k] == k) {
double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK); double TotalRepeaterDelayTime = v->MaxInterDCNTileRepeaters * (2 / v->DPPCLK[k] + 3 / v->DISPCLK);
v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k]; v->VUpdateWidthPix[k] = (14 / v->DCFCLKDeepSleep + 12 / v->DPPCLK[k] + TotalRepeaterDelayTime) * v->PixelClock[k];
@ -2730,62 +2607,23 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
CalculateWatermarksAndDRAMSpeedChangeSupport( CalculateWatermarksAndDRAMSpeedChangeSupport(
mode_lib, mode_lib,
PrefetchMode, PrefetchMode,
v->NumberOfActivePlanes,
v->MaxLineBufferLines,
v->LineBufferSize,
v->DPPOutputBufferPixels,
v->DETBufferSizeInKByte[0],
v->WritebackInterfaceBufferSize,
v->DCFCLK, v->DCFCLK,
v->ReturnBW, v->ReturnBW,
v->GPUVMEnable,
v->dpte_group_bytes,
v->MetaChunkSize,
v->UrgentLatency, v->UrgentLatency,
v->UrgentExtraLatency, v->UrgentExtraLatency,
v->WritebackLatency,
v->WritebackChunkSize,
v->SOCCLK, v->SOCCLK,
v->FinalDRAMClockChangeLatency,
v->SRExitTime,
v->SREnterPlusExitTime,
v->DCFCLKDeepSleep, v->DCFCLKDeepSleep,
v->DPPPerPlane, v->DPPPerPlane,
v->DCCEnable,
v->DPPCLK, v->DPPCLK,
v->DETBufferSizeY, v->DETBufferSizeY,
v->DETBufferSizeC, v->DETBufferSizeC,
v->SwathHeightY, v->SwathHeightY,
v->SwathHeightC, v->SwathHeightC,
v->LBBitPerPixel,
v->SwathWidthY, v->SwathWidthY,
v->SwathWidthC, v->SwathWidthC,
v->HRatio,
v->HRatioChroma,
v->vtaps,
v->VTAPsChroma,
v->VRatio,
v->VRatioChroma,
v->HTotal,
v->PixelClock,
v->BlendingAndTiming,
v->BytePerPixelDETY, v->BytePerPixelDETY,
v->BytePerPixelDETC, v->BytePerPixelDETC,
v->DSTXAfterScaler, &DRAMClockChangeSupport);
v->DSTYAfterScaler,
v->WritebackEnable,
v->WritebackPixelFormat,
v->WritebackDestinationWidth,
v->WritebackDestinationHeight,
v->WritebackSourceHeight,
&DRAMClockChangeSupport,
&v->UrgentWatermark,
&v->WritebackUrgentWatermark,
&v->DRAMClockChangeWatermark,
&v->WritebackDRAMClockChangeWatermark,
&v->StutterExitWatermark,
&v->StutterEnterPlusExitWatermark,
&v->MinActiveDRAMClockChangeLatencySupported);
for (k = 0; k < v->NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (v->WritebackEnable[k] == true) { if (v->WritebackEnable[k] == true) {
@ -4770,29 +4608,12 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule( v->NoTimeForPrefetch[i][j][k] = CalculatePrefetchSchedule(
mode_lib, mode_lib,
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData, k,
v->PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly,
&myPipe, &myPipe,
v->DSCDelayPerState[i][k], v->DSCDelayPerState[i][k],
v->DPPCLKDelaySubtotal + v->DPPCLKDelayCNVCFormater,
v->DPPCLKDelaySCL,
v->DPPCLKDelaySCLLBOnly,
v->DPPCLKDelayCNVCCursor,
v->DISPCLKDelaySubtotal,
v->SwathWidthYThisState[k] / v->HRatio[k], v->SwathWidthYThisState[k] / v->HRatio[k],
v->OutputFormat[k],
v->MaxInterDCNTileRepeaters,
dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]), dml_min(v->MaxVStartup, v->MaximumVStartup[i][j][k]),
v->MaximumVStartup[i][j][k], v->MaximumVStartup[i][j][k],
v->GPUVMMaxPageTableLevels,
v->GPUVMEnable,
v->HostVMEnable,
v->HostVMMaxNonCachedPageTableLevels,
v->HostVMMinPageSize,
v->DynamicMetadataEnable[k],
v->DynamicMetadataVMEnabled,
v->DynamicMetadataLinesBeforeActiveRequired[k],
v->DynamicMetadataTransmittedBytes[k],
v->UrgLatency[i], v->UrgLatency[i],
v->ExtraLatency, v->ExtraLatency,
v->TimeCalc, v->TimeCalc,
@ -4806,7 +4627,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
v->MaxNumSwY[k], v->MaxNumSwY[k],
v->PrefetchLinesC[i][j][k], v->PrefetchLinesC[i][j][k],
v->SwathWidthCThisState[k], v->SwathWidthCThisState[k],
v->BytePerPixelC[k],
v->PrefillC[k], v->PrefillC[k],
v->MaxNumSwC[k], v->MaxNumSwC[k],
v->swath_width_luma_ub_this_state[k], v->swath_width_luma_ub_this_state[k],
@ -4814,9 +4634,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
v->SwathHeightYThisState[k], v->SwathHeightYThisState[k],
v->SwathHeightCThisState[k], v->SwathHeightCThisState[k],
v->TWait, v->TWait,
v->ProgressiveToInterlaceUnitInOPP,
&v->DSTXAfterScaler[k],
&v->DSTYAfterScaler[k],
&v->LineTimesForPrefetch[k], &v->LineTimesForPrefetch[k],
&v->PrefetchBW[k], &v->PrefetchBW[k],
&v->LinesForMetaPTE[k], &v->LinesForMetaPTE[k],
@ -4825,14 +4642,7 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
&v->VRatioPreC[i][j][k], &v->VRatioPreC[i][j][k],
&v->RequiredPrefetchPixelDataBWLuma[i][j][k], &v->RequiredPrefetchPixelDataBWLuma[i][j][k],
&v->RequiredPrefetchPixelDataBWChroma[i][j][k], &v->RequiredPrefetchPixelDataBWChroma[i][j][k],
&v->NoTimeForDynamicMetadata[i][j][k], &v->NoTimeForDynamicMetadata[i][j][k]);
&v->Tno_bw[k],
&v->prefetch_vmrow_bw[k],
&v->Tdmdl_vm[k],
&v->Tdmdl[k],
&v->VUpdateOffsetPix[k],
&v->VUpdateWidthPix[k],
&v->VReadyOffsetPix[k]);
} }
for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) { for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
@ -5007,62 +4817,23 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
CalculateWatermarksAndDRAMSpeedChangeSupport( CalculateWatermarksAndDRAMSpeedChangeSupport(
mode_lib, mode_lib,
v->PrefetchModePerState[i][j], v->PrefetchModePerState[i][j],
v->NumberOfActivePlanes,
v->MaxLineBufferLines,
v->LineBufferSize,
v->DPPOutputBufferPixels,
v->DETBufferSizeInKByte[0],
v->WritebackInterfaceBufferSize,
v->DCFCLKState[i][j], v->DCFCLKState[i][j],
v->ReturnBWPerState[i][j], v->ReturnBWPerState[i][j],
v->GPUVMEnable,
v->dpte_group_bytes,
v->MetaChunkSize,
v->UrgLatency[i], v->UrgLatency[i],
v->ExtraLatency, v->ExtraLatency,
v->WritebackLatency,
v->WritebackChunkSize,
v->SOCCLKPerState[i], v->SOCCLKPerState[i],
v->FinalDRAMClockChangeLatency,
v->SRExitTime,
v->SREnterPlusExitTime,
v->ProjectedDCFCLKDeepSleep[i][j], v->ProjectedDCFCLKDeepSleep[i][j],
v->NoOfDPPThisState, v->NoOfDPPThisState,
v->DCCEnable,
v->RequiredDPPCLKThisState, v->RequiredDPPCLKThisState,
v->DETBufferSizeYThisState, v->DETBufferSizeYThisState,
v->DETBufferSizeCThisState, v->DETBufferSizeCThisState,
v->SwathHeightYThisState, v->SwathHeightYThisState,
v->SwathHeightCThisState, v->SwathHeightCThisState,
v->LBBitPerPixel,
v->SwathWidthYThisState, v->SwathWidthYThisState,
v->SwathWidthCThisState, v->SwathWidthCThisState,
v->HRatio,
v->HRatioChroma,
v->vtaps,
v->VTAPsChroma,
v->VRatio,
v->VRatioChroma,
v->HTotal,
v->PixelClock,
v->BlendingAndTiming,
v->BytePerPixelInDETY, v->BytePerPixelInDETY,
v->BytePerPixelInDETC, v->BytePerPixelInDETC,
v->DSTXAfterScaler, &v->DRAMClockChangeSupport[i][j]);
v->DSTYAfterScaler,
v->WritebackEnable,
v->WritebackPixelFormat,
v->WritebackDestinationWidth,
v->WritebackDestinationHeight,
v->WritebackSourceHeight,
&v->DRAMClockChangeSupport[i][j],
&v->UrgentWatermark,
&v->WritebackUrgentWatermark,
&v->DRAMClockChangeWatermark,
&v->WritebackDRAMClockChangeWatermark,
&v->StutterExitWatermark,
&v->StutterEnterPlusExitWatermark,
&v->MinActiveDRAMClockChangeLatencySupported);
} }
} }
@ -5179,63 +4950,25 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
static void CalculateWatermarksAndDRAMSpeedChangeSupport( static void CalculateWatermarksAndDRAMSpeedChangeSupport(
struct display_mode_lib *mode_lib, struct display_mode_lib *mode_lib,
unsigned int PrefetchMode, unsigned int PrefetchMode,
unsigned int NumberOfActivePlanes,
unsigned int MaxLineBufferLines,
unsigned int LineBufferSize,
unsigned int DPPOutputBufferPixels,
unsigned int DETBufferSizeInKByte,
unsigned int WritebackInterfaceBufferSize,
double DCFCLK, double DCFCLK,
double ReturnBW, double ReturnBW,
bool GPUVMEnable,
unsigned int dpte_group_bytes[],
unsigned int MetaChunkSize,
double UrgentLatency, double UrgentLatency,
double ExtraLatency, double ExtraLatency,
double WritebackLatency,
double WritebackChunkSize,
double SOCCLK, double SOCCLK,
double DRAMClockChangeLatency,
double SRExitTime,
double SREnterPlusExitTime,
double DCFCLKDeepSleep, double DCFCLKDeepSleep,
unsigned int DPPPerPlane[], unsigned int DPPPerPlane[],
bool DCCEnable[],
double DPPCLK[], double DPPCLK[],
unsigned int DETBufferSizeY[], unsigned int DETBufferSizeY[],
unsigned int DETBufferSizeC[], unsigned int DETBufferSizeC[],
unsigned int SwathHeightY[], unsigned int SwathHeightY[],
unsigned int SwathHeightC[], unsigned int SwathHeightC[],
unsigned int LBBitPerPixel[],
double SwathWidthY[], double SwathWidthY[],
double SwathWidthC[], double SwathWidthC[],
double HRatio[],
double HRatioChroma[],
unsigned int vtaps[],
unsigned int VTAPsChroma[],
double VRatio[],
double VRatioChroma[],
unsigned int HTotal[],
double PixelClock[],
unsigned int BlendingAndTiming[],
double BytePerPixelDETY[], double BytePerPixelDETY[],
double BytePerPixelDETC[], double BytePerPixelDETC[],
double DSTXAfterScaler[], enum clock_change_support *DRAMClockChangeSupport)
double DSTYAfterScaler[],
bool WritebackEnable[],
enum source_format_class WritebackPixelFormat[],
double WritebackDestinationWidth[],
double WritebackDestinationHeight[],
double WritebackSourceHeight[],
enum clock_change_support *DRAMClockChangeSupport,
double *UrgentWatermark,
double *WritebackUrgentWatermark,
double *DRAMClockChangeWatermark,
double *WritebackDRAMClockChangeWatermark,
double *StutterExitWatermark,
double *StutterEnterPlusExitWatermark,
double *MinActiveDRAMClockChangeLatencySupported)
{ {
struct vba_vars_st *v = &mode_lib->vba;
double EffectiveLBLatencyHidingY = 0; double EffectiveLBLatencyHidingY = 0;
double EffectiveLBLatencyHidingC = 0; double EffectiveLBLatencyHidingC = 0;
double LinesInDETY[DC__NUM_DPP__MAX] = { 0 }; double LinesInDETY[DC__NUM_DPP__MAX] = { 0 };
@ -5254,101 +4987,101 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
double WritebackDRAMClockChangeLatencyHiding = 0; double WritebackDRAMClockChangeLatencyHiding = 0;
unsigned int k, j; unsigned int k, j;
mode_lib->vba.TotalActiveDPP = 0; v->TotalActiveDPP = 0;
mode_lib->vba.TotalDCCActiveDPP = 0; v->TotalDCCActiveDPP = 0;
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
mode_lib->vba.TotalActiveDPP = mode_lib->vba.TotalActiveDPP + DPPPerPlane[k]; v->TotalActiveDPP = v->TotalActiveDPP + DPPPerPlane[k];
if (DCCEnable[k] == true) { if (v->DCCEnable[k] == true) {
mode_lib->vba.TotalDCCActiveDPP = mode_lib->vba.TotalDCCActiveDPP + DPPPerPlane[k]; v->TotalDCCActiveDPP = v->TotalDCCActiveDPP + DPPPerPlane[k];
} }
} }
*UrgentWatermark = UrgentLatency + ExtraLatency; v->UrgentWatermark = UrgentLatency + ExtraLatency;
*DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark; v->DRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->UrgentWatermark;
mode_lib->vba.TotalActiveWriteback = 0; v->TotalActiveWriteback = 0;
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (WritebackEnable[k] == true) { if (v->WritebackEnable[k] == true) {
mode_lib->vba.TotalActiveWriteback = mode_lib->vba.TotalActiveWriteback + 1; v->TotalActiveWriteback = v->TotalActiveWriteback + 1;
} }
} }
if (mode_lib->vba.TotalActiveWriteback <= 1) { if (v->TotalActiveWriteback <= 1) {
*WritebackUrgentWatermark = WritebackLatency; v->WritebackUrgentWatermark = v->WritebackLatency;
} else { } else {
*WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
} }
if (mode_lib->vba.TotalActiveWriteback <= 1) { if (v->TotalActiveWriteback <= 1) {
*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency; v->WritebackDRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->WritebackLatency;
} else { } else {
*WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; v->WritebackDRAMClockChangeWatermark = v->FinalDRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
} }
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
mode_lib->vba.LBLatencyHidingSourceLinesY = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1); v->LBLatencyHidingSourceLinesY = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1);
mode_lib->vba.LBLatencyHidingSourceLinesC = dml_min((double) MaxLineBufferLines, dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1); v->LBLatencyHidingSourceLinesC = dml_min((double) v->MaxLineBufferLines, dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1);
EffectiveLBLatencyHidingY = mode_lib->vba.LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]); EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]);
EffectiveLBLatencyHidingC = mode_lib->vba.LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]); EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]);
LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k]; LinesInDETY[k] = (double) DETBufferSizeY[k] / BytePerPixelDETY[k] / SwathWidthY[k];
LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]);
FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; FullDETBufferingTimeY[k] = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
if (BytePerPixelDETC[k] > 0) { if (BytePerPixelDETC[k] > 0) {
LinesInDETC = mode_lib->vba.DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k];
LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]);
FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k]; FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k];
} else { } else {
LinesInDETC = 0; LinesInDETC = 0;
FullDETBufferingTimeC = 999999; FullDETBufferingTimeC = 999999;
} }
ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - *UrgentWatermark - (HTotal[k] / PixelClock[k]) * (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) - *DRAMClockChangeWatermark; ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY[k] - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
if (NumberOfActivePlanes > 1) { if (v->NumberOfActivePlanes > 1) {
ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k]; ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k];
} }
if (BytePerPixelDETC[k] > 0) { if (BytePerPixelDETC[k] > 0) {
ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - *UrgentWatermark - (HTotal[k] / PixelClock[k]) * (DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) - *DRAMClockChangeWatermark; ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC - v->UrgentWatermark - (v->HTotal[k] / v->PixelClock[k]) * (v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) - v->DRAMClockChangeWatermark;
if (NumberOfActivePlanes > 1) { if (v->NumberOfActivePlanes > 1) {
ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k]; ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k];
} }
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC); v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC);
} else { } else {
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY; v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY;
} }
if (WritebackEnable[k] == true) { if (v->WritebackEnable[k] == true) {
WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024 / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4); WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024 / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4);
if (WritebackPixelFormat[k] == dm_444_64) { if (v->WritebackPixelFormat[k] == dm_444_64) {
WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2; WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2;
} }
if (mode_lib->vba.WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave) { if (v->WritebackConfiguration == dm_whole_buffer_for_single_stream_interleave) {
WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding * 2; WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding * 2;
} }
WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - mode_lib->vba.WritebackDRAMClockChangeWatermark; WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark;
mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] = dml_min(mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin); v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(v->ActiveDRAMClockChangeLatencyMargin[k], WritebackDRAMClockChangeLatencyMargin);
} }
} }
mode_lib->vba.MinActiveDRAMClockChangeMargin = 999999; v->MinActiveDRAMClockChangeMargin = 999999;
PlaneWithMinActiveDRAMClockChangeMargin = 0; PlaneWithMinActiveDRAMClockChangeMargin = 0;
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < mode_lib->vba.MinActiveDRAMClockChangeMargin) { if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) {
mode_lib->vba.MinActiveDRAMClockChangeMargin = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k];
if (BlendingAndTiming[k] == k) { if (v->BlendingAndTiming[k] == k) {
PlaneWithMinActiveDRAMClockChangeMargin = k; PlaneWithMinActiveDRAMClockChangeMargin = k;
} else { } else {
for (j = 0; j < NumberOfActivePlanes; ++j) { for (j = 0; j < v->NumberOfActivePlanes; ++j) {
if (BlendingAndTiming[k] == j) { if (v->BlendingAndTiming[k] == j) {
PlaneWithMinActiveDRAMClockChangeMargin = j; PlaneWithMinActiveDRAMClockChangeMargin = j;
} }
} }
@ -5356,40 +5089,40 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport(
} }
} }
*MinActiveDRAMClockChangeLatencySupported = mode_lib->vba.MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency; v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->FinalDRAMClockChangeLatency;
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999; SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999;
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) {
SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = mode_lib->vba.ActiveDRAMClockChangeLatencyMargin[k]; SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k];
} }
} }
mode_lib->vba.TotalNumberOfActiveOTG = 0; v->TotalNumberOfActiveOTG = 0;
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (BlendingAndTiming[k] == k) { if (v->BlendingAndTiming[k] == k) {
mode_lib->vba.TotalNumberOfActiveOTG = mode_lib->vba.TotalNumberOfActiveOTG + 1; v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1;
} }
} }
if (mode_lib->vba.MinActiveDRAMClockChangeMargin > 0) { if (v->MinActiveDRAMClockChangeMargin > 0) {
*DRAMClockChangeSupport = dm_dram_clock_change_vactive; *DRAMClockChangeSupport = dm_dram_clock_change_vactive;
} else if (((mode_lib->vba.SynchronizedVBlank == true || mode_lib->vba.TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) { } else if (((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0)) {
*DRAMClockChangeSupport = dm_dram_clock_change_vblank; *DRAMClockChangeSupport = dm_dram_clock_change_vblank;
} else { } else {
*DRAMClockChangeSupport = dm_dram_clock_change_unsupported; *DRAMClockChangeSupport = dm_dram_clock_change_unsupported;
} }
FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[0]; FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[0];
for (k = 0; k < NumberOfActivePlanes; ++k) { for (k = 0; k < v->NumberOfActivePlanes; ++k) {
if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) { if (FullDETBufferingTimeY[k] <= FullDETBufferingTimeYStutterCriticalPlane) {
FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[k]; FullDETBufferingTimeYStutterCriticalPlane = FullDETBufferingTimeY[k];
TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (HTotal[k] / PixelClock[k]) / VRatio[k]; TimeToFinishSwathTransferStutterCriticalPlane = (SwathHeightY[k] - (LinesInDETY[k] - LinesInDETYRoundedDownToSwath[k])) * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k];
} }
} }
*StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep; v->StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep;
*StutterEnterPlusExitWatermark = dml_max(SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep, TimeToFinishSwathTransferStutterCriticalPlane); v->StutterEnterPlusExitWatermark = dml_max(v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep, TimeToFinishSwathTransferStutterCriticalPlane);
} }

28
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
View File

@ -1610,38 +1610,12 @@ dce110_select_crtc_source(struct pipe_ctx *pipe_ctx)
struct dc_bios *bios = link->ctx->dc_bios; struct dc_bios *bios = link->ctx->dc_bios;
struct bp_crtc_source_select crtc_source_select = {0}; struct bp_crtc_source_select crtc_source_select = {0};
enum engine_id engine_id = link->link_enc->preferred_engine; enum engine_id engine_id = link->link_enc->preferred_engine;
uint8_t bit_depth;
if (dc_is_rgb_signal(pipe_ctx->stream->signal)) if (dc_is_rgb_signal(pipe_ctx->stream->signal))
engine_id = link->link_enc->analog_engine; engine_id = link->link_enc->analog_engine;
switch (pipe_ctx->stream->timing.display_color_depth) {
case COLOR_DEPTH_UNDEFINED:
bit_depth = 0;
break;
case COLOR_DEPTH_666:
bit_depth = 6;
break;
default:
case COLOR_DEPTH_888:
bit_depth = 8;
break;
case COLOR_DEPTH_101010:
bit_depth = 10;
break;
case COLOR_DEPTH_121212:
bit_depth = 12;
break;
case COLOR_DEPTH_141414:
bit_depth = 14;
break;
case COLOR_DEPTH_161616:
bit_depth = 16;
break;
}
crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst; crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst;
crtc_source_select.bit_depth = bit_depth; crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth;
crtc_source_select.engine_id = engine_id; crtc_source_select.engine_id = engine_id;
crtc_source_select.sink_signal = pipe_ctx->stream->signal; crtc_source_select.sink_signal = pipe_ctx->stream->signal;

4
drivers/gpu/drm/amd/display/dc/link/link_detection.c
View File

@ -932,7 +932,7 @@ static bool link_detect_dac_load_detect(struct dc_link *link)
struct link_encoder *link_enc = link->link_enc; struct link_encoder *link_enc = link->link_enc;
enum engine_id engine_id = link_enc->preferred_engine; enum engine_id engine_id = link_enc->preferred_engine;
enum dal_device_type device_type = DEVICE_TYPE_CRT; enum dal_device_type device_type = DEVICE_TYPE_CRT;
enum bp_result bp_result; enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
uint32_t enum_id; uint32_t enum_id;
switch (engine_id) { switch (engine_id) {
@ -946,7 +946,9 @@ static bool link_detect_dac_load_detect(struct dc_link *link)
break; break;
} }
if (bios->funcs->dac_load_detection)
bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id); bp_result = bios->funcs->dac_load_detection(bios, engine_id, device_type, enum_id);
return bp_result == BP_RESULT_OK; return bp_result == BP_RESULT_OK;
} }

2
drivers/gpu/drm/amd/display/include/bios_parser_types.h
View File

@ -136,7 +136,7 @@ struct bp_crtc_source_select {
enum engine_id engine_id; enum engine_id engine_id;
enum controller_id controller_id; enum controller_id controller_id;
enum signal_type sink_signal; enum signal_type sink_signal;
uint8_t bit_depth; enum dc_color_depth color_depth;
}; };
struct bp_transmitter_control { struct bp_transmitter_control {

9
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
View File

@ -2455,8 +2455,6 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
} }
for (i = 0; i < NUM_LINK_LEVELS; i++) { for (i = 0; i < NUM_LINK_LEVELS; i++) {
if (pptable->PcieGenSpeed[i] > pcie_gen_cap ||
pptable->PcieLaneCount[i] > pcie_width_cap) {
dpm_context->dpm_tables.pcie_table.pcie_gen[i] = dpm_context->dpm_tables.pcie_table.pcie_gen[i] =
pptable->PcieGenSpeed[i] > pcie_gen_cap ? pptable->PcieGenSpeed[i] > pcie_gen_cap ?
pcie_gen_cap : pptable->PcieGenSpeed[i]; pcie_gen_cap : pptable->PcieGenSpeed[i];
@ -2464,15 +2462,14 @@ static int navi10_update_pcie_parameters(struct smu_context *smu,
pptable->PcieLaneCount[i] > pcie_width_cap ? pptable->PcieLaneCount[i] > pcie_width_cap ?
pcie_width_cap : pptable->PcieLaneCount[i]; pcie_width_cap : pptable->PcieLaneCount[i];
smu_pcie_arg = i << 16; smu_pcie_arg = i << 16;
smu_pcie_arg |= pcie_gen_cap << 8; smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_gen[i] << 8;
smu_pcie_arg |= pcie_width_cap; smu_pcie_arg |= dpm_context->dpm_tables.pcie_table.pcie_lane[i];
ret = smu_cmn_send_smc_msg_with_param(smu, ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_OverridePcieParameters, SMU_MSG_OverridePcieParameters,
smu_pcie_arg, smu_pcie_arg,
NULL); NULL);
if (ret) if (ret)
break; return ret;
}
} }
return ret; return ret;

7
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View File

@ -2923,8 +2923,13 @@ static int smu_v13_0_0_mode1_reset(struct smu_context *smu)
break; break;
} }
if (!ret) if (!ret) {
/* disable mmio access while doing mode 1 reset*/
smu->adev->no_hw_access = true;
/* ensure no_hw_access is globally visible before any MMIO */
smp_mb();
msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
}
return ret; return ret;
} }

9
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
View File

@ -2143,11 +2143,16 @@ static int smu_v14_0_2_mode1_reset(struct smu_context *smu)
ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset); ret = smu_cmn_send_debug_smc_msg(smu, DEBUGSMC_MSG_Mode1Reset);
if (!ret) { if (!ret) {
if (amdgpu_emu_mode == 1) if (amdgpu_emu_mode == 1) {
msleep(50000); msleep(50000);
else } else {
/* disable mmio access while doing mode 1 reset*/
smu->adev->no_hw_access = true;
/* ensure no_hw_access is globally visible before any MMIO */
smp_mb();
msleep(1000); msleep(1000);
} }
}
return ret; return ret;
} }

2
drivers/gpu/drm/radeon/pptable.h
View File

@ -450,7 +450,7 @@ typedef struct _ClockInfoArray{
//sizeof(ATOM_PPLIB_CLOCK_INFO) //sizeof(ATOM_PPLIB_CLOCK_INFO)
UCHAR ucEntrySize; UCHAR ucEntrySize;
UCHAR clockInfo[] __counted_by(ucNumEntries); UCHAR clockInfo[] /*__counted_by(ucNumEntries)*/;
}ClockInfoArray; }ClockInfoArray;
typedef struct _NonClockInfoArray{ typedef struct _NonClockInfoArray{