4011 Commits

Author	SHA1	Message	Date
Linus Torvalds	522ba450b5	There's a bunch of patches here across drivers/clk/ to migrate drivers to use ... struct clk_ops::determine_rate() instead of the round_rate() one so that we can remove the round_rate clk_op entirely. Brian has taken up that task which nobody else has wanted to do for close to a decade. Thanks Brian! This is all prerequisite work to get to the real task of improving the clk rate setting process. Once we have determine_rate() used everywhere, we'll be able to do things like chain the rate request structs in linked lists to order the rate setting operations or add more parameters without having to change every clk driver in existence. It's also nice to not have multiple ways to do something which just causes confusion for clk driver authors. Overall I'm glad this is getting done. Beyond this change we also have a tweak to the clk_lookup() function in the core framework to use hashing on the clk name instead of a clk tree walk with string comparisons. We _still_ rely on the clk name to be unique, because historically we've used globally unique strings to describe the clk tree topology. This tree walk becomes increasingly slow as more clks are added to the system. Searching from the roots for a duplicate is simple but pretty dumb and it wastes boot time so we're using a hash table as an improvement. Ideally we wouldn't rely on the strings to be unique at all, relegating them to simply debug information, but that is future work that will likely require some sort of Kconfig knob indicating strings aren't used for topology description. Outside of the core framework changes we have the usual new SoC support and fixes to clk drivers for things that were discovered once the clks were used by consumer drivers. Nothing in particular is jumping out at me in the "misc" pile, except maybe the Amlogic driver that has gone through a refactoring. That series got a fix from testing in -next though so it seems likely that things have been getting good test coverage for a couple weeks already. -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmjkoQAUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSWfWBAA3cjpOX/qOBDPmYPvV+WgiTPcmnw+ PaMiGNqIWctnJiuYYUNVCfBIvTk9i1vYSgEosHAOqjXQV+7Ee31420xn5RYr6Zen cfeD58SJwZ1JVidvxwWclC5pnfTVXBC3wlHILCFHhckaGOT2k3d0ryN2io2TYuRx t9JsoW73YW+bmOWoFDHPMp4ow5Q87aa8k3/srhIP67tw2mzJp8Wp+EG0t0PVFF7Z aboz+QPwyT2YOLFKJxm6nTLb9FRVq3QLSO3Ek0+0TYXfRqkfegvGR+M82P4Jq2Y3 osmTsumWeI170iAETmx2Py+uUV8MmnvPFQ6mxrGoXYyOx9SclN+SC86cOsi+RsgD 830CHupZ/TrN3+DGyX6WVx1j7XKCplKhFXrXiFbkPnj4nJwi5UgiJrjAjPy78+iX LyvKfeT9ooAAVBVRMyZIWGF3kuQf5qHFMps5fwJk/j3R9yMiI10SVhruhYij1qAi EEisj955xqdyZV2gq85E7zHbjySA0nvNABn3NVUQOKPYQqtpglqXKGJuXZ1//9pa fZM2a3fH7w4fwH1x06FKut9zf1AZUgyasJPtgyCT9dpN+pcoNmJfoH3T42MCItbm XKEYgnv/kQT+M+GokBUfg8bJY5uPnPLa/f6aAAIAKGZV0HXAqz2q73SDlW7KUQmr vhgA4MRH4Vqviic= =fjY4 -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "There's a bunch of patches here across drivers/clk/ to migrate drivers to use struct clk_ops::determine_rate() instead of the round_rate() one so that we can remove the round_rate clk_op entirely. Brian has taken up that task which nobody else has wanted to do for close to a decade. Thanks Brian! This is all prerequisite work to get to the real task of improving the clk rate setting process. Once we have determine_rate() used everywhere, we'll be able to do things like chain the rate request structs in linked lists to order the rate setting operations or add more parameters without having to change every clk driver in existence. It's also nice to not have multiple ways to do something which just causes confusion for clk driver authors. Overall I'm glad this is getting done. Beyond this change we also have a tweak to the clk_lookup() function in the core framework to use hashing on the clk name instead of a clk tree walk with string comparisons. We _still_ rely on the clk name to be unique, because historically we've used globally unique strings to describe the clk tree topology. This tree walk becomes increasingly slow as more clks are added to the system. Searching from the roots for a duplicate is simple but pretty dumb and it wastes boot time so we're using a hash table as an improvement. Ideally we wouldn't rely on the strings to be unique at all, relegating them to simply debug information, but that is future work that will likely require some sort of Kconfig knob indicating strings aren't used for topology description. Outside of the core framework changes we have the usual new SoC support and fixes to clk drivers for things that were discovered once the clks were used by consumer drivers. Nothing in particular is jumping out at me in the "misc" pile, except maybe the Amlogic driver that has gone through a refactoring. That series got a fix from testing in -next though so it seems likely that things have been getting good test coverage for a couple weeks already" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits) clk: microchip: core: remove duplicate roclk_determine_rate() reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() clk: mmp: pxa1908: Instantiate power driver through auxiliary bus clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings ...	2025-10-07 09:28:37 -07:00
Stephen Boyd	f35f83208c	Merge branches 'clk-aspeed' and 'clk-rockchip' into clk-next ... * clk-aspeed: reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define * clk-rockchip: clk: rockchip: rk3368: use clock ids for SCLK_MIPIDSI_24M dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M	2025-10-06 13:00:50 -05:00
Stephen Boyd	8397c58ea7	Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next ... - Add Mediatek MT8196 clk drivers * clk-marvell: clk: mmp: pxa1908: Instantiate power driver through auxiliary bus * clk-xilinx: clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() * clk-mediatek: (31 commits) clk: mediatek: Add MT8196 vencsys clock support clk: mediatek: Add MT8196 vdecsys clock support clk: mediatek: Add MT8196 ovl1 clock support clk: mediatek: Add MT8196 ovl0 clock support clk: mediatek: Add MT8196 disp-ao clock support clk: mediatek: Add MT8196 disp1 clock support clk: mediatek: Add MT8196 disp0 clock support clk: mediatek: Add MT8196 mfg clock support clk: mediatek: Add MT8196 mdpsys clock support clk: mediatek: Add MT8196 mcu clock support clk: mediatek: Add MT8196 I2C clock support clk: mediatek: Add MT8196 pextpsys clock support clk: mediatek: Add MT8196 ufssys clock support clk: mediatek: Add MT8196 peripheral clock support clk: mediatek: Add MT8196 vlpckgen clock support clk: mediatek: Add MT8196 topckgen2 clock support clk: mediatek: Add MT8196 topckgen clock support clk: mediatek: Add MT8196 apmixedsys clock support dt-bindings: clock: mediatek: Describe MT8196 clock controllers clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro ... * clk-loongson: clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible	2025-10-06 13:00:22 -05:00
Stephen Boyd	b91217d912	Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next ... - Speed up clk_core_lookup() by using a hashtable * clk-microchip: ARM: at91: remove default values for PMC_PLL_ACR clk: at91: add ACR in all PLL settings clk: at91: sam9x7: Add peripheral clock id for pmecc clk: at91: clk-master: Add check for divide by 3 clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register ARM: at91: pm: save and restore ACR during PLL disable/enable * clk-lookup: clk: Use hashtable for global clk lookups clk: Sort include statements * clk-st: dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings	2025-10-06 13:00:12 -05:00
Stephen Boyd	f0fd248204	Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next ... * clk-scmi: clk: scmi: Add duty cycle ops only when duty cycle is supported * clk-qcom: (27 commits) clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock controller found on MSM8937 dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller clk: qcom: Select the intended config in QCS_DISPCC_615 clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register() clk: qcom: alpha-pll: convert from round_rate() to determine_rate() clk: qcom: milos: Constify 'struct qcom_cc_desc' clk: qcom: gcc: Add support for Global Clock Controller dt-bindings: clock: qcom: document the Glymur Global Clock Controller clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL clk: qcom: rpmh: Add support for Glymur rpmh clocks clk: qcom: Add TCSR clock driver for Glymur SoC dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs clk: qcom: dispcc-glymur: Add support for Display Clock Controller dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs ... * clk-broadcom: clk: bcm: rpi: Maximize V3D clock clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing clk: bcm: rpi: Add missing logs if firmware fails	2025-10-06 12:57:03 -05:00
Stephen Boyd	c1e102f349	Merge branches 'clk-imx', 'clk-allwinner' and 'clk-ti' into clk-next ... * clk-imx: clk: imx95-blk-ctl: Save/restore registers when RPM routines are called clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure * clk-allwinner: clk: sunxi-ng: add support for the A523/T527 MCU CCU clk: sunxi-ng: div: support power-of-two dividers clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock clk: sunxi-ng: sun6i-rtc: Add A523 specifics * clk-ti: clk: keystone: sci-clk: use devm_kmemdup_array() clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled	2025-10-06 12:56:54 -05:00
Stephen Boyd	3aae991cc2	Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next ... * clk-samsung: clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units clk: samsung: exynos990: Add missing USB clock registers to HSI0 clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC clk: samsung: Add clock PLL support for ARTPEC-8 SoC dt-bindings: clock: Add ARTPEC-8 clock controller clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP dt-bindings: clock: exynos990: Extend clocks IDs clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes clk: samsung: pll: convert from round_rate() to determine_rate() clk: samsung: cpu: convert from round_rate() to determine_rate() clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block dt-bindings: clock: Add CAM_CSI clock macro for FSD * clk-tegra: clk: tegra: dfll: Add CVB tables for Tegra114 clk: tegra: Add DFLL DVCO reset control for Tegra114 dt-bindings: arm: tegra: Add ASUS TF101G and SL101 dt-bindings: reset: Add Tegra114 CAR header dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) dt-bindings: clock: tegra30: Add IDs for CSI pad clocks dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C * clk-amlogic: clk: amlogic: fix recent code refactoring clk: amlogic: c3-peripherals: use helper for basic composite clocks clk: amlogic: align s4 and c3 pwm clock descriptions clk: amlogic: add composite clock helpers clk: amlogic: use the common pclk definition clk: amlogic: introduce a common pclk definition clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks clk: amlogic: move PCLK definition to clkc-utils clk: amlogic: aoclk: use clkc-utils syscon probe clk: amlogic: use probe helper in mmio based controllers clk: amlogic: add probe helper for mmio based controllers clk: amlogic: drop meson-clkcee clk: amlogic: naming consistency alignment	2025-10-06 12:56:46 -05:00
Stephen Boyd	ec7336475d	Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next ... * clk-bindings: dt-bindings: clock: mediatek: Add power-domains property dt-bindings: clock: silabs,si5341: Add missing properties dt-bindings: clock: adi,axi-clkgen: add clock-output-names property dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding dt-bindings: clock: Convert silabs,si570 to DT schema dt-bindings: clock: Convert silabs,si5341 to DT schema dt-bindings: clock: Convert silabs,si514/544 to DT schema * clk-cleanup: clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes dt-bindings: clock: st: flexgen: remove deprecated compatibles clk: st: flexgen: remove unused compatible clk: clk-axi-clkgen: remove unneeded semicolon clk: tegra: Remove redundant semicolons clk: npcm: select CONFIG_AUXILIARY_BUS clk: remove unneeded 'fast_io' parameter in regmap_config * clk-renesas: (27 commits) clk: renesas: r9a09g05[67]: Reduce differences clk: renesas: r9a09g047: Add USB3.0 clocks/resets clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init() clk: renesas: r9a09g056: Add clock and reset entries for I3C clk: renesas: r9a09g057: Add clock and reset entries for I3C dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert() clk: renesas: rzv2h: Re-assert reset on deassert timeout clk: renesas: rzg2l: Re-assert reset on deassert timeout clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert() dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs clk: renesas: r9a09g047: Add GPT clocks and resets clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5 clk: renesas: rzv2h: remove round_rate() in favor of determine_rate() clk: renesas: rzg2l: convert from round_rate() to determine_rate() clk: renesas: r9a07g04[34]: Use tabs instead of spaces clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL clk: renesas: r9a07g044: Add MSTOP for RZ/G2L clk: renesas: r9a08g045: Add MSTOP for GPIO ... * clk-thead: clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL clk: thead: support changing DPU pixel clock rate clk: thead: add support for enabling/disabling PLLs clk: thead: Correct parent for DPU pixel clocks clk: thead: th1520-ap: fix parent of padctrl0 clock clk: thead: th1520-ap: describe gate clocks with clk_gate * clk-spacemit: clk: spacemit: fix i2s clock clk: spacemit: introduce pre-div for ddn clock dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock clk: spacemit: ccu_pll: convert from round_rate() to determine_rate() clk: spacemit: ccu_mix: convert from round_rate() to determine_rate() clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate() clk: spacemit: fix sspax_clk dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA	2025-10-06 12:56:23 -05:00
Linus Torvalds	6093a688a0	Char/Misc/IIO/Binder changes for 6.18-rc1 ... Here is the big set of char/misc/iio and other driver subsystem changes for 6.18-rc1. Loads of different stuff in here, it was a busy development cycle in lots of different subsystems, with over 27k new lines added to the tree. Included in here are: - IIO updates including new drivers, reworking of existing apis, and other goodness in the sensor subsystems - MEI driver updates and additions - NVMEM driver updates - slimbus removal for an unused driver and some other minor updates - coresight driver updates and additions - MHI driver updates - comedi driver updates and fixes - extcon driver updates - interconnect driver additions - eeprom driver updates and fixes - minor UIO driver updates - tiny W1 driver updates But the majority of new code is in the rust bindings and additions, which includes: - misc driver rust binding updates for read/write support, we can now write "normal" misc drivers in rust fully, and the sample driver shows how this can be done. - Initial framework for USB driver rust bindings, which are disabled for now in the build, due to limited support, but coming in through this tree due to dependencies on other rust binding changes that were in here. I'll be enabling these back on in the build in the usb.git tree after -rc1 is out so that developers can continue to work on these in linux-next over the next development cycle. - Android Binder driver implemented in Rust. This is the big one, and was driving a huge majority of the rust binding work over the past years. Right now there are 2 binder drivers in the kernel, selected only at build time as to which one to use as binder wants to be included in the system at boot time. The binder C maintainers all agreed on this, as eventually, they want the C code to be removed from the tree, but it will take a few releases to get there while both are maintained to ensure that the rust implementation is fully stable and compliant with the existing userspace apis. All of these have been in linux-next for a while, with only minor merge issues showing up (you will hit them as well.) Just accept both sides of the merge, it's just some header and include file lines, nothing major. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -----BEGIN PGP SIGNATURE----- iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCaOEffA8cZ3JlZ0Brcm9h aC5jb20ACgkQMUfUDdst+ynI/wCgjLFWH9B+huZI5JQb06NShggZod4AnjFFJ4ID macHNv5/SjpAh7H5ssBU =cjWS -----END PGP SIGNATURE----- Merge tag 'char-misc-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull Char/Misc/IIO/Binder updates from Greg KH: "Here is the big set of char/misc/iio and other driver subsystem changes for 6.18-rc1. Loads of different stuff in here, it was a busy development cycle in lots of different subsystems, with over 27k new lines added to the tree. Included in here are: - IIO updates including new drivers, reworking of existing apis, and other goodness in the sensor subsystems - MEI driver updates and additions - NVMEM driver updates - slimbus removal for an unused driver and some other minor updates - coresight driver updates and additions - MHI driver updates - comedi driver updates and fixes - extcon driver updates - interconnect driver additions - eeprom driver updates and fixes - minor UIO driver updates - tiny W1 driver updates But the majority of new code is in the rust bindings and additions, which includes: - misc driver rust binding updates for read/write support, we can now write "normal" misc drivers in rust fully, and the sample driver shows how this can be done. - Initial framework for USB driver rust bindings, which are disabled for now in the build, due to limited support, but coming in through this tree due to dependencies on other rust binding changes that were in here. I'll be enabling these back on in the build in the usb.git tree after -rc1 is out so that developers can continue to work on these in linux-next over the next development cycle. - Android Binder driver implemented in Rust. This is the big one, and was driving a huge majority of the rust binding work over the past years. Right now there are two binder drivers in the kernel, selected only at build time as to which one to use as binder wants to be included in the system at boot time. The binder C maintainers all agreed on this, as eventually, they want the C code to be removed from the tree, but it will take a few releases to get there while both are maintained to ensure that the rust implementation is fully stable and compliant with the existing userspace apis. All of these have been in linux-next for a while" * tag 'char-misc-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (320 commits) rust: usb: keep usb::Device private for now rust: usb: don't retain device context for the interface parent USB: disable rust bindings from the build for now samples: rust: add a USB driver sample rust: usb: add basic USB abstractions coresight: Add label sysfs node support dt-bindings: arm: Add label in the coresight components coresight: tnoc: add new AMBA ID to support Trace Noc V2 coresight: Fix incorrect handling for return value of devm_kzalloc coresight: tpda: fix the logic to setup the element size coresight: trbe: Return NULL pointer for allocation failures coresight: Refactor runtime PM coresight: Make clock sequence consistent coresight: Refactor driver data allocation coresight: Consolidate clock enabling coresight: Avoid enable programming clock duplicately coresight: Appropriately disable trace bus clocks coresight: Appropriately disable programming clocks coresight: etm4x: Support atclk coresight: catu: Support atclk ...	2025-10-04 16:26:32 -07:00
Linus Torvalds	d955299b5c	soc: build fix for 6.18 ... One commit for the dt bindings was missing from the dt branch, this one is already pending in the clk tree that contains the corresponding device driver. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmje970ACgkQYKtH/8kJ UieWdQ/9EKbkRWleVJ9Cuz4oX1vOv6TKISkboqb4b7ZFh56AKV/PeVanAiy+wsaI tnVuiIi8aVBiPxddi4xVY4+RaRp0ZjaOEDYhxvJ1huc1p7i0I4viHo0G4MYflgbM Db+yjqaSGMfpKEcWJSmtVt1qZF89t/8ZE0vlPxQ0Z+wAqTEX3b6zofI1UnAiFtGH vgvXcW6798n+czaZulE98tC+oAWlrbyruVh0SC8q7UfchCrCFsJQYSkw9GecmoaR RS48mM+JHdKxgHsNXR5qbWkktHcsvC8TJ8Jscxqn71cJYB1TldGEdBAEpfxlVkYD rWbCr6mr6XHg0N/5yVF0n5VwLESGJeUhRsFMiBUHfq9HgWred6iwP/pu6LQGWaKE fKUDlM/ukTzuyVaG1Ipxr9wbecpIHlETmaVSBZMrBHYj0hSeDvV5qVkKHORYX/QN OdtIcIsoez7VReqhnHIBy/MNRbLrZZCkEscX6H2i41d7pXDmFdBZZIGTN7W9kuNx DEvPVJtXznLxTIOawftoB1AG/PBUaa8zLZ6w/7DmFXx4rRSztyBmYV14bE86JTwF y0Hux3DHaAYtj4qI25awwzMLdNyMDc7BQry9fF/5wdZYBzAHbbv1OEZ/J+Fm6YNn q4ERE7NpB8TVG1DAFuKrzI4OsFxHzurco2snso5yY8OYvDn/BMs= =DlPR -----END PGP SIGNATURE----- Merge tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC build fix from Arnd Bergmann: "One commit for the dt bindings was missing from the dt branch, this one is already pending in the clk tree that contains the corresponding device driver" * tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: dt-bindings: clock: Add ARTPEC-8 clock controller	2025-10-03 19:36:39 -07:00
Linus Torvalds	07fdad3a93	Networking changes for 6.18. ... Core & protocols ---------------- - Improve drop account scalability on NUMA hosts for RAW and UDP sockets and the backlog, almost doubling the Pps capacity under DoS. - Optimize the UDP RX performance under stress, reducing contention, revisiting the binary layout of the involved data structs and implementing NUMA-aware locking. This improves UDP RX performance by an additional 50%, even more under extreme conditions. - Add support for PSP encryption of TCP connections; this mechanism has some similarities with IPsec and TLS, but offers superior HW offloads capabilities. - Ongoing work to support Accurate ECN for TCP. AccECN allows more than one congestion notification signal per RTT and is a building block for Low Latency, Low Loss, and Scalable Throughput (L4S). - Reorganize the TCP socket binary layout for data locality, reducing the number of touched cachelines in the fastpath. - Refactor skb deferral free to better scale on large multi-NUMA hosts, this improves TCP and UDP RX performances significantly on such HW. - Increase the default socket memory buffer limits from 256K to 4M to better fit modern link speeds. - Improve handling of setups with a large number of nexthop, making dump operating scaling linearly and avoiding unneeded synchronize_rcu() on delete. - Improve bridge handling of VLAN FDB, storing a single entry per bridge instead of one entry per port; this makes the dump order of magnitude faster on large switches. - Restore IP ID correctly for encapsulated packets at GSO segmentation time, allowing GRO to merge packets in more scenarios. - Improve netfilter matching performance on large sets. - Improve MPTCP receive path performance by leveraging recently introduced core infrastructure (skb deferral free) and adopting recent TCP autotuning changes. - Allow bridges to redirect to a backup port when the bridge port is administratively down. - Introduce MPTCP 'laminar' endpoint that con be used only once per connection and simplify common MPTCP setups. - Add RCU safety to dst->dev, closing a lot of possible races. - A significant crypto library API for SCTP, MPTCP and IPv6 SR, reducing code duplication. - Supports pulling data from an skb frag into the linear area of an XDP buffer. Things we sprinkled into general kernel code -------------------------------------------- - Generate netlink documentation from YAML using an integrated YAML parser. Driver API ---------- - Support using IPv6 Flow Label in Rx hash computation and RSS queue selection. - Introduce API for fetching the DMA device for a given queue, allowing TCP zerocopy RX on more H/W setups. - Make XDP helpers compatible with unreadable memory, allowing more easily building DevMem-enabled drivers with a unified XDP/skbs datapath. - Add a new dedicated ethtool callback enabling drivers to provide the number of RX rings directly, improving efficiency and clarity in RX ring queries and RSS configuration. - Introduce a burst period for the health reporter, allowing better handling of multiple errors due to the same root cause. - Support for DPLL phase offset exponential moving average, controlling the average smoothing factor. Device drivers -------------- - Add a new Huawei driver for 3rd gen NIC (hinic3). - Add a new SpacemiT driver for K1 ethernet MAC. - Add a generic abstraction for shared memory communication devices (dibps) - Ethernet high-speed NICs: - nVidia/Mellanox: - Use multiple per-queue doorbell, to avoid MMIO contention issues - support adjacent functions, allowing them to delegate their SR-IOV VFs to sibling PFs - support RSS for IPSec offload - support exposing raw cycle counters in PTP and mlx5 - support for disabling host PFs. - Intel (100G, ice, idpf): - ice: support for SRIOV VFs over an Active-Active link aggregate - ice: support for firmware logging via debugfs - ice: support for Earliest TxTime First (ETF) hardware offload - idpf: support basic XDP functionalities and XSk - Broadcom (bnxt): - support Hyper-V VF ID - dynamic SRIOV resource allocations for RoCE - Meta (fbnic): - support queue API, zero-copy Rx and Tx - support basic XDP functionalities - devlink health support for FW crashes and OTP mem corruptions - expand hardware stats coverage to FEC, PHY, and Pause - Wangxun: - support ethtool coalesce options - support for multiple RSS contexts - Ethernet virtual: - Macsec: - replace custom netlink attribute checks with policy-level checks - Bonding: - support aggregator selection based on port priority - Microsoft vNIC: - use page pool fragments for RX buffers instead of full pages to improve memory efficiency - Ethernet NICs consumer, and embedded: - Qualcomm: support Ethernet function for IPQ9574 SoC - Airoha: implement wlan offloading via NPU - Freescale - enetc: add NETC timer PTP driver and add PTP support - fec: enable the Jumbo frame support for i.MX8QM - Renesas (R-Car S4): support HW offloading for layer 2 switching - support for RZ/{T2H, N2H} SoCs - Cadence (macb): support TAPRIO traffic scheduling - TI: - support for Gigabit ICSS ethernet SoC (icssm-prueth) - Synopsys (stmmac): a lot of cleanups - Ethernet PHYs: - Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS driver - Support bcm63268 GPHY power control - Support for Micrel lan8842 PHY and PTP - Support for Aquantia AQR412 and AQR115 - CAN: - a large CAN-XL preparation work - reorganize raw_sock and uniqframe struct to minimize memory usage - rcar_canfd: update the CAN-FD handling - WiFi: - extended Neighbor Awareness Networking (NAN) support - S1G channel representation cleanup - improve S1G support - WiFi drivers: - Intel (iwlwifi): - major refactor and cleanup - Broadcom (brcm80211): - support for AP isolation - RealTek (rtw88/89) rtw88/89: - preparation work for RTL8922DE support - MediaTek (mt76): - HW restart improvements - MLO support - Qualcomm/Atheros (ath10k_ - GTK rekey fixes - Bluetooth drivers: - btusb: support for several new IDs for MT7925 - btintel: support for BlazarIW core - btintel_pcie: support for _suspend() / _resume() - btintel_pcie: support for Scorpious, Panther Lake-H484 IDs Signed-off-by: Paolo Abeni <pabeni@redhat.com> -----BEGIN PGP SIGNATURE----- iQJGBAABCAAwFiEEg1AjqC77wbdLX2LbKSR5jcyPE6QFAmjdBdsSHHBhYmVuaUBy ZWRoYXQuY29tAAoJECkkeY3MjxOkWnAP/2Jz0ExnYMDxLxkkKqMte+3JNeF/KNjB zVIslYN/5ekkd1TMXyDLFlWHqUOUMSF9+cK5ZRMHG6/lzOueSzFuuuDFsWs6Kf2f q7Q9MzlXhR9++YCsdES1uS5x3PPjMInzo2ZivMFa6fUDLLFSzeAOKL9k+RS0EggU VlXv2Wkm73R0O6KAssgDsHke9cnNz+F0DzhQ0S3qkyZF9tS5NrDeUl7fZ47XZgwb ZuXdEzKmTTepo2XvZGxJoF2D7nekWFlHhLjEPpDJtET19nwhukCry41/FplJwlKR dWsYkqLkrOEQKFQ+q++/5c3BgFOG+IrQLbP5bGQF1tZRMl4Dqp9PDxK5fKJfccbS 0VY3Y2qWOSYejT2Ji2kEHR5E5rPyFm3Y5A4Rnpz0yEHj14vL2v4zf7CZRkCyyDfD doIZXFGkM0+N7QeXLEN833cje9zjaXuP9GAE+2bb+wAWAZAqof4KX8JgHh+y5Rwm pvUtvFxmEtntlMwNBap8aT3FquGtfZncU8pzAE5kvWjuMvyF0NVWiE5rB2kSQM/X NLmUdvDyjwwJqthXAJG0fl+a0mNJ/kOAqSOKJDJrfKDGWa+ovwY0iY06SpK0wIbO Wz7tpMk5MSlYXW8xWMlbyhvvU6T9xuoQ2KV4QTdMxc6Ir3sNX6YkQr+gjQjxB0gx ST2QF6lZeWFh =w2Kz -----END PGP SIGNATURE----- Merge tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next Pull networking updates from Paolo Abeni: "Core & protocols: - Improve drop account scalability on NUMA hosts for RAW and UDP sockets and the backlog, almost doubling the Pps capacity under DoS - Optimize the UDP RX performance under stress, reducing contention, revisiting the binary layout of the involved data structs and implementing NUMA-aware locking. This improves UDP RX performance by an additional 50%, even more under extreme conditions - Add support for PSP encryption of TCP connections; this mechanism has some similarities with IPsec and TLS, but offers superior HW offloads capabilities - Ongoing work to support Accurate ECN for TCP. AccECN allows more than one congestion notification signal per RTT and is a building block for Low Latency, Low Loss, and Scalable Throughput (L4S) - Reorganize the TCP socket binary layout for data locality, reducing the number of touched cachelines in the fastpath - Refactor skb deferral free to better scale on large multi-NUMA hosts, this improves TCP and UDP RX performances significantly on such HW - Increase the default socket memory buffer limits from 256K to 4M to better fit modern link speeds - Improve handling of setups with a large number of nexthop, making dump operating scaling linearly and avoiding unneeded synchronize_rcu() on delete - Improve bridge handling of VLAN FDB, storing a single entry per bridge instead of one entry per port; this makes the dump order of magnitude faster on large switches - Restore IP ID correctly for encapsulated packets at GSO segmentation time, allowing GRO to merge packets in more scenarios - Improve netfilter matching performance on large sets - Improve MPTCP receive path performance by leveraging recently introduced core infrastructure (skb deferral free) and adopting recent TCP autotuning changes - Allow bridges to redirect to a backup port when the bridge port is administratively down - Introduce MPTCP 'laminar' endpoint that con be used only once per connection and simplify common MPTCP setups - Add RCU safety to dst->dev, closing a lot of possible races - A significant crypto library API for SCTP, MPTCP and IPv6 SR, reducing code duplication - Supports pulling data from an skb frag into the linear area of an XDP buffer Things we sprinkled into general kernel code: - Generate netlink documentation from YAML using an integrated YAML parser Driver API: - Support using IPv6 Flow Label in Rx hash computation and RSS queue selection - Introduce API for fetching the DMA device for a given queue, allowing TCP zerocopy RX on more H/W setups - Make XDP helpers compatible with unreadable memory, allowing more easily building DevMem-enabled drivers with a unified XDP/skbs datapath - Add a new dedicated ethtool callback enabling drivers to provide the number of RX rings directly, improving efficiency and clarity in RX ring queries and RSS configuration - Introduce a burst period for the health reporter, allowing better handling of multiple errors due to the same root cause - Support for DPLL phase offset exponential moving average, controlling the average smoothing factor Device drivers: - Add a new Huawei driver for 3rd gen NIC (hinic3) - Add a new SpacemiT driver for K1 ethernet MAC - Add a generic abstraction for shared memory communication devices (dibps) - Ethernet high-speed NICs: - nVidia/Mellanox: - Use multiple per-queue doorbell, to avoid MMIO contention issues - support adjacent functions, allowing them to delegate their SR-IOV VFs to sibling PFs - support RSS for IPSec offload - support exposing raw cycle counters in PTP and mlx5 - support for disabling host PFs. - Intel (100G, ice, idpf): - ice: support for SRIOV VFs over an Active-Active link aggregate - ice: support for firmware logging via debugfs - ice: support for Earliest TxTime First (ETF) hardware offload - idpf: support basic XDP functionalities and XSk - Broadcom (bnxt): - support Hyper-V VF ID - dynamic SRIOV resource allocations for RoCE - Meta (fbnic): - support queue API, zero-copy Rx and Tx - support basic XDP functionalities - devlink health support for FW crashes and OTP mem corruptions - expand hardware stats coverage to FEC, PHY, and Pause - Wangxun: - support ethtool coalesce options - support for multiple RSS contexts - Ethernet virtual: - Macsec: - replace custom netlink attribute checks with policy-level checks - Bonding: - support aggregator selection based on port priority - Microsoft vNIC: - use page pool fragments for RX buffers instead of full pages to improve memory efficiency - Ethernet NICs consumer, and embedded: - Qualcomm: support Ethernet function for IPQ9574 SoC - Airoha: implement wlan offloading via NPU - Freescale - enetc: add NETC timer PTP driver and add PTP support - fec: enable the Jumbo frame support for i.MX8QM - Renesas (R-Car S4): - support HW offloading for layer 2 switching - support for RZ/{T2H, N2H} SoCs - Cadence (macb): support TAPRIO traffic scheduling - TI: - support for Gigabit ICSS ethernet SoC (icssm-prueth) - Synopsys (stmmac): a lot of cleanups - Ethernet PHYs: - Support 10g-qxgmi phy-mode for AQR412C, Felix DSA and Lynx PCS driver - Support bcm63268 GPHY power control - Support for Micrel lan8842 PHY and PTP - Support for Aquantia AQR412 and AQR115 - CAN: - a large CAN-XL preparation work - reorganize raw_sock and uniqframe struct to minimize memory usage - rcar_canfd: update the CAN-FD handling - WiFi: - extended Neighbor Awareness Networking (NAN) support - S1G channel representation cleanup - improve S1G support - WiFi drivers: - Intel (iwlwifi): - major refactor and cleanup - Broadcom (brcm80211): - support for AP isolation - RealTek (rtw88/89) rtw88/89: - preparation work for RTL8922DE support - MediaTek (mt76): - HW restart improvements - MLO support - Qualcomm/Atheros (ath10k): - GTK rekey fixes - Bluetooth drivers: - btusb: support for several new IDs for MT7925 - btintel: support for BlazarIW core - btintel_pcie: support for _suspend() / _resume() - btintel_pcie: support for Scorpious, Panther Lake-H484 IDs" * tag 'net-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1536 commits) net: stmmac: Add support for Allwinner A523 GMAC200 dt-bindings: net: sun8i-emac: Add A523 GMAC200 compatible Revert "Documentation: net: add flow control guide and document ethtool API" octeontx2-pf: fix bitmap leak octeontx2-vf: fix bitmap leak net/mlx5e: Use extack in set rxfh callback net/mlx5e: Introduce mlx5e_rss_params for RSS configuration net/mlx5e: Introduce mlx5e_rss_init_params net/mlx5e: Remove unused mdev param from RSS indir init net/mlx5: Improve QoS error messages with actual depth values net/mlx5e: Prevent entering switchdev mode with inconsistent netns net/mlx5: HWS, Generalize complex matchers net/mlx5: Improve write-combining test reliability for ARM64 Grace CPUs selftests/net: add tcp_port_share to .gitignore Revert "net/mlx5e: Update and set Xon/Xoff upon MTU set" net: add NUMA awareness to skb_attempt_defer_free() net: use llist for sd->defer_list net: make softnet_data.defer_count an atomic selftests: drv-net: psp: add tests for destroying devices selftests: drv-net: psp: add test for auto-adjusting TCP MSS ...	2025-10-02 15:17:01 -07:00
Linus Torvalds	f79e772258	[GIT PULL for v6.18] media updates ... -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE+QmuaPwR3wnBdVwACF8+vY7k4RUFAmjdReIACgkQCF8+vY7k 4RUyzxAAmqaYUomji7+Imoy/M9lFE5EBwC5HAZ2wfS9c8l7sYw9kZEaoq+JOapKB EU+dLr/judjpntmIOYqGPBgbVdzalGEvYsZ2KgVbygZS5JgF0K+Yb4ary3t+wN+H 43pGExsdRdwZhVU02xkSOohBcvWTEtWCjypdRSxSs03oLQtJ7AOcSNvsD25DTSNC 05l3Fr/5Ckjr9PpjjYaTX1SdRyPWoRD536yeGbbRo3ZTCGG8dFXwqZdhAqrMfFmb dAVttiTvMBHY/4LdA7YFLW/Ww3ty9uMgwv7D2LYCBPwKr01W32x4e0hZjQNjltlk omcw13oKMDhWm7bsB4ja2X3DjFLZnFcULyAtdhgR/+5748fIL82pp16XR80Zbweb UgO5WsUCQbYAfKdiu6CG/amwG1yHJW/2fRh6xD8WEKcsLjnIFhPN4rTsLXo6IeMY KVru2OOfXJUdo6fMfHk7EZElWGMS9H1iQy64v3eJe1bAIa0tMZKhwxrpAJTk1Ykf fvWdqdp761c1+P53is/LHtt7fqCN6aHsDcwXTCsJGH1YI4b/qxXjcgPMyedf6kRu GY+soXWcpldhxrR4yblMFhaJGFgIdFmnYDHWWzMxgQ0a8ch0ORf8aGlF5kT5SP+9 VPnZqY+EECrHqvI3DU4CaHNbZFXp6RKW+2ZkXFpIRH12v1aARmE= =Fuey -----END PGP SIGNATURE----- Merge tag 'media/v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media Pull media updates from Mauro Carvalho Chehab: - Added a new V4L2 clock helper - New camera sensor drivers - iris: Enable H.264/H.265 encoder support and fixes in iris driver common code - camss: add support for new SoC flavors - venus: add new SoC support - tc358743: support more infoframe types - Various fixes, driver improvements and cleanups * tag 'media/v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (439 commits) media: venus: pm_helpers: add fallback for the opp-table media: qcom: camss: vfe: Fix BPL alignment for QCM2290 media: tuner: xc5000: Fix use-after-free in xc5000_release media: i2c: tc358743: Fix use-after-free bugs caused by orphan timer in probe media: b2c2: Fix use-after-free causing by irq_check_work in flexcop_pci_remove media: vsp1: Export missing vsp1_isp_free_buffer symbol media: renesas: vsp1: Convert to SYSTEM_SLEEP/RUNTIME_PM_OPS() media: renesas: ceu: Convert to RUNTIME_PM_OPS() media: renesas: fdp1: Convert to RUNTIME_PM_OPS() media: renesas: rcar-vin: Convert to DEFINE_SIMPLE_DEV_PM_OPS() media: renesas: rcar_drif: Convert to DEFINE_SIMPLE_DEV_PM_OPS() media: uvcvideo: Mark invalid entities with id UVC_INVALID_ENTITY_ID media: uvcvideo: Support UVC_CROSXU_CONTROL_IQ_PROFILE media: uvcvideo: Run uvc_ctrl_init_ctrl for all controls media: uvcvideo: Shorten the transfer size non compliance message media: uvcvideo: Do not re-reference dev->udev media: uvcvideo: Use intf instead of udev for printks media: uvcvideo: Move video_device under video_queue media: uvcvideo: Drop stream->mutex media: uvcvideo: Move MSXU_CONTROL_METADATA definition to header ...	2025-10-02 13:13:26 -07:00
Linus Torvalds	38057e3236	soc: driver updates for 6.18 ... Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdpaoACgkQmmx57+YA GNnBXA//QgmFXYGG7QfB825mt0orKZxpfpLcwvqO7hkWgbXtl7Gokw2lGYN6bwLu zvY4MQ/bVoZ8R5uTVmuaSHBRsttSen8mBf+V0vzsBM/DRRVxvIN/7TESrY3J7Dtx J5syHKIBiUtdkDebWWC6jIElczIBItsd03Ln4Xjjt8Vas5YOO4n44zFrPo+FwlN/ I6D2K86AiNZTtUCDMtB6VfJ6YtjYBWcWnJm7FXw/vE8FAXdZUnNWnZ8hbdQ5GaME JZGepUhONaOMUoGNZNaDGw511RdPhYzPjj9rCsIx2qdsRO9/4tJ8ccpW2aUMYh8c nA6w8Hj8jCwco6aYYrDUDV9uRtURDrmyJgTJBNLU05e/L+MuJ3IZNlzHFWlsxIAE vhyTdmg/P04ClQyixCl67IH/66F/0smX9C+1761LrD7GTdfR92KPl5W6q+DPBg/x yf+s2p3+f7ItV5XobKOrbf3w0xazeDb5o/EK8BufMx9vSe9bpzJ0gOf0CmNXEpyZ owAhbh6wXX1YwPcyA9LHv6gthyJwc/3fLu49ggMZP2rU01ccKOYn9H0cr7C8NVmy wEpJR0lp5aSw2oRkPkxB6sFmUohcpr8/OXGGJuvCXkYsUY1BEup4lewvbIWK4WoE c84kbbaHsjgFhe3IRlQw3G4KLYQT3jRtF7fH+gPx556BcI6K+lg= =mcZR -----END PGP SIGNATURE----- Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0" * tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits) soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu() soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Change GPIO driver to a proper platform driver tee: fix register_shm_helper() pmdomain: apple: Add "apple,t8103-pmgr-pwrstate" dt-bindings: spmi: Add Apple A11 and T2 compatible serial: qcom-geni: Load UART qup Firmware from linux side spi: geni-qcom: Load spi qup Firmware from linux side i2c: qcom-geni: Load i2c qup Firmware from linux side soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem soc: qcom: geni-se: Cleanup register defines and update copyright dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Documentation: tee: Add Qualcomm TEE driver tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl tee: qcom: add primordial object tee: add Qualcomm TEE driver tee: increase TEE_MAX_ARG_SIZE to 4096 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF tee: add close_context to TEE driver operation ...	2025-10-01 17:32:51 -07:00
Linus Torvalds	0f048c878e	soc: dt changes for 6.18 ... There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdn9oACgkQmmx57+YA GNnHwg//RBWBI+6Wj8DP9vkz+0/UKNNPVPZNIwL3+X9zWBnQ/nRDj8U6Z8q8uqeP 42M+kWTt6WwgHLYItcKa7o1YTdkq1cNuxSt4QIliWxcy58RnsJUbfYErmB6ouM3I yUbJNJdarQAkewypsZ6TYA1z/fMPK8uWLSCvEpIsfxMn6GV9bKOaCSDCM1htDwYV /CXiJEP4ytlpOXz1JkrQ8yljiEX5mBTe4Gfc70FKS+9UMdOwx74od8cUwmptw2ej g/LiDPbKWJ3OLUeUBxZiJW6PDEH0MjBmXTamZo56cniSP3ZJ5H4T//ZEqYspYR+f Dcj9AjtT0QHOpLnrTPsTmXHme/oGodmgEXuooSJxEEfFSv0fxfjNXHOR6gUoSSLz cCe6wcu4nBLmAK0QqI8oMJO4Ey6NE74Kz4kJwad2Oe7Aee7eCnjX6ZwyB4sJvBtf ii401i3GYdOWV0DkgAAqREMNPbUZH9WWdCYd/izI3fO1TooBptaPWRo60rrIpx3M u1ntYyj1PFrnYadESATgmmj+3PE7mRaL6prvCtI19vt12qQONDVzoFgzjxh+I7tV 8PQTb3QbciZuMiX36GNgt5OLz9KqE31xtZtxo/+a8CNOzuZu8UwonpkMkkrwGMRU /3jjZvuiRBh2xW32yqszAFw0JII+2cGPQUG5dcoijcEqWorKMto= =9OtD -----END PGP SIGNATURE----- Merge tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC dt updates from Arnd Bergmann: "There are five sets of new SoCs that get added in existing families, all of them being either upgrades or cut-down versions of the older chips: - Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation of high-end workstations and laptops from Apple. Linux has been working on these for a while but stil requires patches. - Axis Artpec8 is an Armv8 chip based on Samsung Exynos design, unlike the earlier Armv7 Artpec6 from the same company that was part of a separate family of chips. - NXP i.MX91 is a cut-down version of i.MX93, using only a single Cortex-A55 core. - Qualcomm Lemans Auto is a variant of the Lemans SoC that was originally merged under the sa8775p name, the differences being mostly the firmware configuration of the platform. - Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44), RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial bedded SoCs based on Cortex-A55 cores In total, there are 65 new machines, including: - Industrial embedded system and single-board computers based on NXP, Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips. - Reference boards for the newly added Renesas, Qualcomm, NXP and Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC - Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1 chips. - Several Samsung phones using Qualcomm Snapdragon chips - Set-top boxes based on Allwinner H313 - Five BMC boards using 32-bit ASpeed SoCs - Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708 (ARMv7) SoCs Two machines get phased out because they were available only in small quantities but never made it into products: one STi407 based reference board, and a Snapdragon 845 based Chromebook. Aside from the newly added machines, a lot of work went into improving hardware support on the existing machines and cleaning up contents for validation" * tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits) arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node ARM: dts: microchip: sam9x7: Add qspi controller arm64: dts: qcom: Add MST pixel streams for displayport arm64: dts: qcom: sm6350: correct DP compatibility strings arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU arm64: dts: qcom: qcs8300: Add gpu and gmu nodes arm64: dts: allwinner: h313: Add Amediatech X96Q dt-bindings: arm: sunxi: Add Amediatech X96Q arm64: dts: apple: t8015: Add SPMI node arm64: dts: apple: t8012: Add SPMI node arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT arm64: dts: rockchip: update pinctrl names for Radxa E52C arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C arm64: dts: apple: Add J474s, J475c and J475d device trees arm64: dts: apple: Add J414 and J416 Macbook Pro device trees arm64: dts: apple: Add initial t6020/t6021/t6022 DTs ...	2025-10-01 17:19:38 -07:00
Linus Torvalds	f13ee7cc2d	Thermal control updates for 6.18-rc1 ... - Add new thermal driver for the Renesas RZ/G3S SoC (Claudiu Beznea) - Add new thermal driver for the Renesas RZ/G3E SoC (John Madieu) - Add support for new platform power slider feature to the Intel int340x driver (Srinivas Pandruvada). - Add new Tegra114-specific SOCTHERM driver and document Tegra114 SOCTHERM Thermal Management System in DT bindings (Svyatoslav Ryhel) - Add temperature sensor channel to thermal-generic-adc (Svyatoslav Ryhel) - Add support for per-SoC default trim values to the Renesas rcar_gen3 thermal driver, use it for adding R-Car V4H default trim values, fix a comment typo in that driver and document Gen4 support in its Kconfig entry (Marek Vasut) - Fix mapping SoCs to generic Gen4 entry in the Renesas rcar_gen3 thermal driver (Wolfram Sang) - Document the TSU unit in the r9a08g045-tsu and r9a09g047-tsu DT bindings (Claudiu Beznea, John Madieu) - Make LMH select QCOM_SCM and add missing IRQ includes to the qcom/lmh thermal driver (Dmitry Baryshkov) - Fix incorrect error message in the qcom/lmh thermal driver (Sumeet Pawnikar) - Add QCS615 compatible to tsens thermal DT bindings (Gaurav Kohli) - Document the Glymur temperature sensor in qcom-tsens thermal DT bindings (Manaf Meethalavalappu Pallikunhi) - Make k3_j72xx_bandgap thermal driver register the thermal sensor with hwmon (Michael Walle) - Tighten GRF requirements in the rockchip thermal DT bindings, silence a GRF warning in the rockchip thermal driver and unify struct rockchip_tsadc_chip format in it (Sebastian Reichel) - Update the Step-wise thermal governor to allow it to reduce the cooling level earlier if thermal zone temperature is dropping and clean it up (Rafael Wysocki) - Clean up the thermal testing code (Rafael Wysocki) - Assorted cleanups of thermal drivers (Jiapeng Chong, Salah Triki, Osama Abdelkader) -----BEGIN PGP SIGNATURE----- iQFGBAABCAAwFiEEcM8Aw/RY0dgsiRUR7l+9nS/U47UFAmjamT4SHHJqd0Byand5 c29ja2kubmV0AAoJEO5fvZ0v1OO1BOwH/3ZL/GN+iJ7oFU/jOW4EktnLowCMgIKF DURhmrZRoqJzZUY8PXysUekXYmniT6Itzv2h4psKMihn/khtapmkRkE23exmR9Gy h5V4Nxbx4Ero6YfZ3KT4+AY1x2eRO6aDY29EdIAVeWacwOleTPhUvP70d5dZTHdy QYi21qZarrkG3uiiNrBfgRW2IAcvQ37G1dy6fxJrURhUG3E9u2P9C9REBwQfkxBj LxaV42oiQNU0S5+r4/0f1UbqR88FTh/X4xmpEFHK+zWewKYdYhXHBdCYlcegH7oO WwQW8u3ofR/COpFNPdWrpDb9fYia0fbcJ131CVmAy8RySVd4dBAPKDM= =okDy -----END PGP SIGNATURE----- Merge tag 'thermal-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull thermal control updates from Rafael Wysocki: "These are mostly thermal driver updates, including new thermal drivers for Renesas RZ/G3S and Renesas RZ/G3E SoCs, a new power slider platform feature support in the Intel int340x thermal driver, a new Tegra114- specific SOCTHERM driver and more. There is also a Step-wise thermal governor update allowing it to start reducing cooling somewhat earlier if the temperature of the given thermal zone is falling down and a thermal testing code cleanup. Specifics: - Add new thermal driver for the Renesas RZ/G3S SoC (Claudiu Beznea) - Add new thermal driver for the Renesas RZ/G3E SoC (John Madieu) - Add support for new platform power slider feature to the Intel int340x driver (Srinivas Pandruvada). - Add new Tegra114-specific SOCTHERM driver and document Tegra114 SOCTHERM Thermal Management System in DT bindings (Svyatoslav Ryhel) - Add temperature sensor channel to thermal-generic-adc (Svyatoslav Ryhel) - Add support for per-SoC default trim values to the Renesas rcar_gen3 thermal driver, use it for adding R-Car V4H default trim values, fix a comment typo in that driver and document Gen4 support in its Kconfig entry (Marek Vasut) - Fix mapping SoCs to generic Gen4 entry in the Renesas rcar_gen3 thermal driver (Wolfram Sang) - Document the TSU unit in the r9a08g045-tsu and r9a09g047-tsu DT bindings (Claudiu Beznea, John Madieu) - Make LMH select QCOM_SCM and add missing IRQ includes to the qcom/lmh thermal driver (Dmitry Baryshkov) - Fix incorrect error message in the qcom/lmh thermal driver (Sumeet Pawnikar) - Add QCS615 compatible to tsens thermal DT bindings (Gaurav Kohli) - Document the Glymur temperature sensor in qcom-tsens thermal DT bindings (Manaf Meethalavalappu Pallikunhi) - Make k3_j72xx_bandgap thermal driver register the thermal sensor with hwmon (Michael Walle) - Tighten GRF requirements in the rockchip thermal DT bindings, silence a GRF warning in the rockchip thermal driver and unify struct rockchip_tsadc_chip format in it (Sebastian Reichel) - Update the Step-wise thermal governor to allow it to reduce the cooling level earlier if thermal zone temperature is dropping and clean it up (Rafael Wysocki) - Clean up the thermal testing code (Rafael Wysocki) - Assorted cleanups of thermal drivers (Jiapeng Chong, Salah Triki, Osama Abdelkader)" * tag 'thermal-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (37 commits) thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas RZ/G3E SoC dt-bindings: thermal: qcom-tsens: Document the Glymur temperature Sensor thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas RZ/G3E SoC dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit thermal/drivers/thermal-generic-adc: Add temperature sensor channel dt-bindings: thermal: rockchip: Tighten grf requirements thermal/drivers/rockchip: Shut up GRF warning thermal/drivers/rockchip: Unify struct rockchip_tsadc_chip format thermal/drivers/renesas/rzg3s: Add thermal driver for the Renesas RZ/G3S SoC dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit thermal/drivers/k3_j72xx_bandgap: Register sensors with hwmon thermal/drivers/rcar_gen3: Fix mapping SoCs to generic Gen4 entry thermal/drivers/tegra: Add Tegra114 specific SOCTHERM driver dt-bindings: thermal: add Tegra114 soctherm header thermal/drivers/tegra/soctherm-fuse: Prepare calibration for Tegra114 support dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System thermal/drivers/rcar_gen3: Document Gen4 support in Kconfig entry thermal/drivers/rcar_gen3: Fix comment typo drivers/thermal/qcom/lmh: Fix incorrect error message thermal/drivers/qcom/lmh: Add missing IRQ includes ...	2025-10-01 16:33:14 -07:00
Linus Torvalds	5fb0249319	Pin control changes for the v6.18 kernel cycle: ... Core changes: - Allow pins to be identified/marked as GPIO mode with a special callback. The pin controller core is now "aware" if a pin is in GPIO mode if the callback is implemented in the driver, and can thus be marked as "strict", i.e. disallowing simultaneous use of a line as GPIO and another function such as I2C. This is enabled in the Qualcomm TLMM driver and also implemeted from day 1 in the new Broadcom STB driver. - Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL to better describe what the config is doing, as well as making it more intuitive what shall be returned when reading this property. New drivers: - Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver. - Qualcomm Glymur family pin controller driver. - Broadcom STB family pin controller driver. - Tegra186 pin controller driver. - AAEON UP pin controller support. This is some special pin controller that works as an external advanced line MUX and amplifier for signals from an Intel SoC. A cooperative effort with the GPIO maintainer was needed to reach a solution where we reuse code from the GPIO aggregator/forwarder driver. - Renesas RZ/T2H and RZ/N2H pin controller support. - Axis ARTPEC-8 subdriver for the Samsung pin controller driver. Improvements: - Output enable (OEN) support in the Renesas RZG2L driver. - Properly support bias pull up/down in the pinctrl-single driver. - Move over all GPIO portions using generic MMIO GPIO to the new generic GPIO chip management which has a nice and separate API. - Proper DT bindings for some older Broadcom SoCs. - External GPIO (EGPIO) support in the Qualcomm SM8250. Deleted code: - Dropped the now unused Samsung S3C24xx drivers. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmjcI6IACgkQQRCzN7AZ XXMFYxAApJr9Rlqh3WlOzvAa2kVrGev0m3S2I0SiQUAIy2TwfMBGBRjDTOQJ+db/ ZazjsTyL+ObuCRmWJpoqlRThEB9oh5xgqN5OHCSIBQXqnjCzG9jnw+s50dGl5r77 vX5RtS5OxPgqe2ay9DY9SA8Ix0G5Yxdq9eP2MfeX45zjAfGWGq6bJT+Llkpf5y8L a1k1EQmQbogw6DLLmpiSUA2qtFitGdB9rLkk/inYWZHq6g8qva4eoVdE+PhzG1ky DrkXaJF3+hC/fBBGk4yrzHfnLL7pqIzyhN3on5Xy9lMfytU8bxGESZck1BxaauHZ 63w8kEfGOsOztbKQ9VLAzDg9Jd+t7fVMmQw5kXT53TEhB0hfX0SbiK2I8UAF3vkV dCe6AWD2Zzz5XlDJpl5vOOYr9lSmuVCZuaIdvgoyLk4BJSLau+24Rme9gqfulT92 /z2mxCHO6CIzIgH4ILiyM90pIE4OCXp0II7SinZ34alO8ZoMyFHAT2Sqa736WdlQ PVfBRBIIJF02os3bcudXpwCD7Xn0ksE5UwVgdDSIk9MKdRI5ZGdbt0y9HUrnfTDk 5hFH3rbm8Vdk65UHcgIiYTN9C9JlbPscNyQG0z4a1OUr2O4wurr0eFBn+kFpluRn ZQBQwjxtEqedsunb5W5Ny79srN6okddpzCIUSQDL20Uw69zy9L0= =DZy/ -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "We have GPIO awareness in the pin control core and an interesting AAEON driver. Core changes: - Allow pins to be identified/marked as GPIO mode with a special callback. The pin controller core is now "aware" if a pin is in GPIO mode if the callback is implemented in the driver, and can thus be marked as "strict", i.e. disallowing simultaneous use of a line as GPIO and another function such as I2C. This is enabled in the Qualcomm TLMM driver and also implemeted from day 1 in the new Broadcom STB driver - Rename the pin config option PIN_CONFIG_OUTPUT to PIN_CONFIG_LEVEL to better describe what the config is doing, as well as making it more intuitive what shall be returned when reading this property New drivers: - Qualcomm SDM660 LPASS LPI TLMM pin controller subdriver - Qualcomm Glymur family pin controller driver - Broadcom STB family pin controller driver - Tegra186 pin controller driver - AAEON UP pin controller support. This is some special pin controller that works as an external advanced line MUX and amplifier for signals from an Intel SoC. A cooperative effort with the GPIO maintainer was needed to reach a solution where we reuse code from the GPIO aggregator/forwarder driver - Renesas RZ/T2H and RZ/N2H pin controller support - Axis ARTPEC-8 subdriver for the Samsung pin controller driver Improvements: - Output enable (OEN) support in the Renesas RZG2L driver - Properly support bias pull up/down in the pinctrl-single driver - Move over all GPIO portions using generic MMIO GPIO to the new generic GPIO chip management which has a nice and separate API - Proper DT bindings for some older Broadcom SoCs - External GPIO (EGPIO) support in the Qualcomm SM8250 Deleted code: - Dropped the now unused Samsung S3C24xx drivers" * tag 'pinctrl-v6.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (75 commits) pinctrl: use more common syntax for compound literals pinctrl: Simplify printks with pOF format pinctrl: qcom: Add SDM660 LPASS LPI TLMM dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl pinctrl: qcom: lpass-lpi: Add ability to use custom pin offsets pinctrl: qcom: Add glymur pinctrl driver dt-bindings: pinctrl: qcom: Add Glymur pinctrl pinctrl: qcom: sm8250: Add egpio support pinctrl: generic: rename PIN_CONFIG_OUTPUT to LEVEL pinctrl: keembay: fix double free in keembay_build_functions() pinctrl: spacemit: fix typo in PRI_TDI pin name pinctrl: eswin: Fix regulator error check and Kconfig dependency pinctrl: bcm: Add STB family pin controller driver dt-bindings: pinctrl: Add support for Broadcom STB pin controller pinctrl: qcom: make the pinmuxing strict pinctrl: qcom: mark the `gpio` and `egpio` pins function as non-strict functions pinctrl: qcom: add infrastructure for marking pin functions as GPIOs pinctrl: allow to mark pin functions as requestable GPIOs pinctrl: qcom: use generic pin function helpers pinctrl: make struct pinfunction a pointer in struct function_desc ...	2025-10-01 13:14:48 -07:00
Linus Torvalds	e93bcbaa71	pmdomain providers: ... - amlogic: Add support for S6/S7/S7D power-domains controller - imx: Add support for i.MX91 power-domains - marvell: Add support for PXA1908 power-domains - mediatek: Add support for modem power sequence - mediatek: Add support for RTFF Hardware in MT8196/MT6991 - qcom: Align power-domain definitions for rpmpd - rockchip: Default to use power-domain support - thead: Create auxiliary device along with a corresponding reset driver - ti: Synchronize on/off state with HW-state for ti-sci power-domains -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAmjacIIXHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCk8NA/9ECu+/I22bthMdCbDhmXkmryI KbFqrvgxsHNBvqMnwbTkufj/ayDEgHvg2uoXrDU5YkP6UaO47m94UAoyyhn0p8QU tfeUE4QH1xKYTQgnZC4og5VdKGWYx/OFNTtki2AWf8Yc37crzfMC3wTsvTvtSxd8 iA9l0FkKy4MS530kPyO5h6u7h8vWzKFYSVbzRzA1tZZ8g0nmpBRpr26DL51+vKoa NYHU3EZ/FTtzu9U6A0ZWmMJoc9PboCHl3WPaCrPwXtVV4K8+QqHeqh0JEBV3p9Au LrS+DFcIeWlKYQy4MxAUl9UU4KwHubyhwtY0nS2sp/+GiOUSkZxxu6m4PE/zZDEo YGibtBrZ2Qkh/5zcjN8LI2NVV7MfnEZtlTBfak72mVR/0xTcz17hNda7QC2Iki0r qVjNjeuwu5mZ6nAAufHz3dReULwjfKqhQbhGx1gyuBRRkxPpt/0/JmKr4g/rz3c5 51O/o5j2k7UcTic1SBDYWADtROnIcAAaEGkfk5koRK0GHHKtuZYDcEoM5+Ls1frF ga+5H5DqanFfS/XUXOZ9eQNG5rScUFstwH6Hh26awjPXta7wSz6AVKJAj+X9/RKG 4KoEL5u4q6O8kAU0Y6QxvF8h7aC0qw6rsc6rZCg2Fi1uaSDB8eqMtwR7PVU8DHYw AbCd7TVjrecKpJGmGK0= =/gH0 -----END PGP SIGNATURE----- Merge tag 'pmdomain-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm Pull pmdomain updates from Ulf Hansson: - amlogic: Add support for S6/S7/S7D power-domains controller - imx: Add support for i.MX91 power-domains - marvell: Add support for PXA1908 power-domains - mediatek: - Add support for modem power sequence - Add support for RTFF Hardware in MT8196/MT6991 - qcom: Align power-domain definitions for rpmpd - rockchip: Default to use power-domain support - thead: Create auxiliary device along with a corresponding reset driver - ti: Synchronize on/off state with HW-state for ti-sci power-domains * tag 'pmdomain-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (25 commits) pmdomain: thead: Fix error pointer vs NULL bug in th1520_pd_reboot_init() pmdomain: thead: create auxiliary device for rebooting driver: reset: th1520-aon: add driver for poweroff/reboot via AON FW pmdomain: mediatek: airoha: convert from round_rate() to determine_rate() pmdomain: rockchip: enable ROCKCHIP_PM_DOMAINS with ARCH_ROCKCHIP pmdomain: marvell: Add PXA1908 power domains dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu pmdomain: ti-sci: Set PD on/off state according to the HW state pmdomain: amlogic: Add support for S6 S7 S7D power domains controller dt-bindings: power: add Amlogic S6 S7 S7D power domains pmdomain: mediatek: Convert all SoCs to new style regmap retrieval pmdomain: mediatek: Add support for RTFF Hardware in MT8196/MT6991 pmdomain: mediatek: Add support for modem power sequences pmdomain: mediatek: Move ctl sequences out of power_on/off functions pmdomain: mediatek: Handle SoCs with inverted SRAM power-down bits pmdomain: mediatek: Refactor bus protection regmaps retrieval dt-bindings: power: mediatek: Document access-controllers property pmdomain: remove unneeded 'fast_io' parameter in regmap_config pmdomain: imx93-blk-ctrl: mask DSI and PXP PD domain register on i.MX91 pmdomain: imx93-blk-ctrl: use ARRAY_SIZE() instead of hardcode number ...	2025-10-01 11:51:53 -07:00
Linus Torvalds	d5f7411411	gpio updates for v6.18-rc1 ... GPIO core: - add support for sparse pin ranges to the glue between GPIO and pinctrl - use a common prefix across all GPIO descriptor flags for improved namespacing New drivers: - add new GPIO driver for the Nuvoton NCT6694 - add new GPIO driver for MAX7360 Driver improvements: - add support for Tegra 256 to the gpio-tegra186 driver - add support for Loongson-2K0300 to the gpio-loongson-64bit driver - refactor the gpio-aggregator module to expose its GPIO forwarder API to other in-kernel users (to enable merging of a new pinctrl driver that uses it) - convert all remaining drivers to using the modernized generic GPIO chip API and remove the old interface - stop displaying global GPIO numbers in debugfs output of controller drivers - extend the gpio-regmap helper with a new config option and improve its support for GPIO interrupts - remove redundant fast_io parameter from regmap configs in GPIO drivers that already use MMIO regmaps which imply it - add support for a new model in gpio-mmio: ixp4xx expansion bus - order includes alphabetically in a few drivers for better readability - use generic device properties where applicable - use devm_mutex_init() where applicable - extend build coverage of drivers by enabling more to be compiled with COMPILE_TEST enabled - allow building gpio-stmpe as a module - use dev_err_probe() where it makes sense in drivers Late driver fixes: - fix setting GPIO direction to output in gpio-mpfs Documentation: - document the usage of software nodes with GPIO chips Device-tree bindings: - Add DT bindings documents for new hardware: Tegra256, MAX7360 - Document a new model in Loongson bindings: LS2K0300 - Document a new model using the generic GPIO binding: IXP4xx - Convert the DT binding for fsl,mxs-pinctrl to YAML - fix the schema ID in the "trivial" GPIO schema - describe GPIO hogs in the generic GPIO binding -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEFp3rbAvDxGAT0sefEacuoBRx13IFAmjaTpAACgkQEacuoBRx 13Iqwg//bcAxAcYGsEzMqcid9ugu+1KFiULWhgIYi4PBeX72UR7ZtSbzQ+hwTY68 Vs1W7eoeaglHwd46K/oXEBsnOvot/gQBjuw4QmYbO6viDWY9OuU81xppgAyw4IEx wBmPiRVHHRNhcAA9/lu5OkFSWeeBNqcUkWlGgyUzsIIpQnadBRYXga+qFW9mq4m5 FMSCagsNP0tnRG4ae1Ek8SAbi3BiKaC/bpxukLVvv6Ma6CUktN2d49gW24h9NbKi clflMVWgWgZBgYVk7Nmz5IQwYtvQz2M3y4Mb4VsuSWXWKRjX+gJb0knmq1fa8SEn lx1MyhSgkpdtUx/bzLjZrPvesbiS1JnyLRAQVa+vtOU8ct2GSWjbKK9vY9w6guVT KlptBNxxyQQi3WVtC+lvYz303gAlm5R2veehTMkmR6PIAE+zQ3EBNstiEEQsoMb2 npAqr/maodIo+FvUpFghSTfG2dSNRnXpRXmGzn49Y3LSjZu/7gC0B5mZYuGghK/g UIvo3m40G/ajTUSyWOWPViUnJPkNMiQTHiH8MrXFUO/sbCavZCC2xp37D0ezWfIx KRq3KPLHEL39dDvLFkpTQccOfSXch/bVFNX0X6EtfyAx4rSCphbX25IaWeuhJ9Ox N3bALHVs0hMvY5nq0sUDTgf8oQMbpqKdAhKnSae3SBWLhon/EaA= =TZ1G -----END PGP SIGNATURE----- Merge tag 'gpio-updates-for-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux Pull gpio updates from Bartosz Golaszewski: "There are two new drivers and support for more models in existing ones. The generic GPIO API has been reworked and all users converted which allowed us to move the fields specific to the generic GPIO implementation out of the high-level struct gpio_chip into its own structure that wraps the gpio_chip. Other than that, there's nothing too exciting. Mostly minor tweaks and fixes all over the place, some refactoring and some small new features in helper modules. GPIO core: - add support for sparse pin ranges to the glue between GPIO and pinctrl - use a common prefix across all GPIO descriptor flags for improved namespacing New drivers: - add new GPIO driver for the Nuvoton NCT6694 - add new GPIO driver for MAX7360 Driver improvements: - add support for Tegra 256 to the gpio-tegra186 driver - add support for Loongson-2K0300 to the gpio-loongson-64bit driver - refactor the gpio-aggregator module to expose its GPIO forwarder API to other in-kernel users (to enable merging of a new pinctrl driver that uses it) - convert all remaining drivers to using the modernized generic GPIO chip API and remove the old interface - stop displaying global GPIO numbers in debugfs output of controller drivers - extend the gpio-regmap helper with a new config option and improve its support for GPIO interrupts - remove redundant fast_io parameter from regmap configs in GPIO drivers that already use MMIO regmaps which imply it - add support for a new model in gpio-mmio: ixp4xx expansion bus - order includes alphabetically in a few drivers for better readability - use generic device properties where applicable - use devm_mutex_init() where applicable - extend build coverage of drivers by enabling more to be compiled with COMPILE_TEST enabled - allow building gpio-stmpe as a module - use dev_err_probe() where it makes sense in drivers Late driver fixes: - fix setting GPIO direction to output in gpio-mpfs Documentation: - document the usage of software nodes with GPIO chips Device-tree bindings: - Add DT bindings documents for new hardware: Tegra256, MAX7360 - Document a new model in Loongson bindings: LS2K0300 - Document a new model using the generic GPIO binding: IXP4xx - Convert the DT binding for fsl,mxs-pinctrl to YAML - fix the schema ID in the "trivial" GPIO schema - describe GPIO hogs in the generic GPIO binding" * tag 'gpio-updates-for-v6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (122 commits) gpio: mpfs: fix setting gpio direction to output gpio: generic: move GPIO_GENERIC_ flags to the correct header gpio: generic: rename BGPIOF_ flags to GPIO_GENERIC_ gpio: nomadik: fix the debugfs helper stub MAINTAINERS: Add entry on MAX7360 driver input: misc: Add support for MAX7360 rotary input: keyboard: Add support for MAX7360 keypad gpio: max7360: Add MAX7360 gpio support gpio: regmap: Allow to provide init_valid_mask callback gpio: regmap: Allow to allocate regmap-irq device pwm: max7360: Add MAX7360 PWM support pinctrl: Add MAX7360 pinctrl driver mfd: Add max7360 support dt-bindings: mfd: gpio: Add MAX7360 rtc: Add Nuvoton NCT6694 RTC support hwmon: Add Nuvoton NCT6694 HWMON support watchdog: Add Nuvoton NCT6694 WDT support can: Add Nuvoton NCT6694 CANFD support i2c: Add Nuvoton NCT6694 I2C support gpio: Add Nuvoton NCT6694 GPIO support ...	2025-10-01 11:34:12 -07:00
Svyatoslav Ryhel	10e1dcb62a	dt-bindings: thermal: add Tegra114 soctherm header ... This adds header for the Tegra114 SOCTHERM device tree node. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20250828055104.8073-5-clamor95@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>	2025-09-25 22:11:00 +02:00
Arnd Bergmann	ebc5eb9ea0	Memory controller drivers for v6.18 ... 1. STM32 OMM: Fix ineffective/missing setting of the req2ack in the device based on DT property, if the value is different than 0. 2. Samsung Exynos SROM: Fix IO map resource leak if of_platform_populate() in probe() failed. 3. Broadcom brcmstb: Document existing, older devices in Devicetree bindings. 4. Tegra 210 EMC: Document OPP table for interconnects (driver usage will come later) and define memory client IDs as bindings, because these are shared between DTS and driver. -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAmjEJ1cQHGtyemtAa2Vy bmVsLm9yZwAKCRDBN2bmhouD18U9D/9yJMQHjwf+ztRI7MDJwMa3uPhKm38qrr6x YIc2eDooXsYmG05aXsqtUZSxCFD38O1kQzrfTYjbRTNzA4D9jZn5jiFUPUrDlZmT RFOkwxDO1Ks3D4ly5e1t5oeI5LTJ9LGLuafjQ76uN5waIdKhIYDIio9JcYycdyvM ULkPghHEp6WP5arnRivp3FsbyDTIOsBvF1GYvjNgvQxO88smfByjtonH5zeUXyv3 YaMdzKN7d/ORZhf3amov86QbeENVEVLtCb65G3j28N0IVSrV8DkfHopVbYNtFouL mfhmsQQGAPJYrNdOAs72whuGe4Z1xlJQmhW7CpfiV55woMSyw+jSXM0muFOIcjBc lMPtLU/C38aqCepKbESiFomRpgd4JyvzB35D5yeign2cd10kY01Q2oVmWIeVFkyq yC9nADwIVXJ7PR53O9BlwgnMn6RTdqlGko75oWaOdOTD4sSeaEBo+RyB/zx2xLsz upvBSHQ964BD7YSDW2rlOC6n48o68NaNXK8UncQwQVIBtfYOQLHIdbMS2ll580Fl K/yiRpDS96YDyrdh0b47xfSHMjSKi6C9AJlVrStuVEjKgbSBA7WbjbQiMIoR+8Nt 7AnCN1J7SjYfQ6kl8fT3ZLvmYr1V6fFldh1wTGOm23IEXLq84RN6XxPo9Nbww6FX vHOhmoyRmQ== =w0Tq -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjTDBYACgkQmmx57+YA GNlzIw//cp0CtBP9PBB7qxbwoR8ppRBQdrLiuc+cDqDMC5wURXkEw7VbqAoMqiAv grBVcqlQoc4+iycCIKZF/JTjQJnlruBn5AFkaBNdf5lwNQ93qX/KrtfelcJNsIL9 LKMI3a58tjothVJgnN4TXRw5nJhSoTv3+YK2r/IGdGfEB7Nt+FCvxWBk0LWEXAqY KUZCxq9DgBPPtF+8zQ8EVMIBGZGoqkoBR74AzN/SHbLwWRfGLPGy3WfiK21FjZ1c YIwfOCeYHOtb/x8rh3kyeaIT6EZVOLEeZJ07ID0IPyv5qMOatzVEgPSQmJOYdI9Y v7q3wk6QmqYphJ60Tdsawi8zVXvlsgnJPpmFrKNx27P6zaAf2rYgGUcEeTEKfv4T NYCqn39jEj19kajM6h52s4x8efzex3VvA6wdV5iyt/Uqtw3sujhSjpKs081UUyOj y/qjdXV91bB9k2iyIq8FqQ2wea4eAK0bGt1ylAYXwhiqsNn7RFH+WNSfJ/iJJukD PTee8DEySMaIWxOV7nYRb+oy8SMN3txLIF5emI6hZw1Xw+2pid3fkZdt/F3F0yEY xBwKprIcruZYglk0DY7JvboraKd4Ly71GBPcAT4YDcsHT8gXznogb8ZgafotgOrp Rd5nE8oWfCaRQrsGdXMkca0+NYriRAKkyTK5MmqEdjyfYvyxJnw= =VjUi -----END PGP SIGNATURE----- Merge tag 'memory-controller-drv-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers Memory controller drivers for v6.18 1. STM32 OMM: Fix ineffective/missing setting of the req2ack in the device based on DT property, if the value is different than 0. 2. Samsung Exynos SROM: Fix IO map resource leak if of_platform_populate() in probe() failed. 3. Broadcom brcmstb: Document existing, older devices in Devicetree bindings. 4. Tegra 210 EMC: Document OPP table for interconnects (driver usage will come later) and define memory client IDs as bindings, because these are shared between DTS and driver. * tag 'memory-controller-drv-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: tegra210: Use bindings for client ids dt-bindings: memory: tegra210: Add memory client IDs dt-bindings: memory: tegra210: emc: Document OPP table and interconnect dt-bindings: memory: Update brcmstb-memc-ddr binding with older chips memory: samsung: exynos-srom: Fix of_iomap leak in exynos_srom_probe memory: stm32_omm: Fix req2ack update test Link: https://lore.kernel.org/r/20250912140030.204650-2-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-23 23:07:34 +02:00
Arnd Bergmann	17752efeca	Allwinner Device Tree changes for 6.18 ... This tag contains two DT binding header changes that are shared with the clk tree. In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. 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In this cycle we gained support for the MCU PRCM clock and reset controller on the A523/A527/T527 family of SoCs, the NPU which is a Vivante GC9000 IP block, and the NPU clock that was missing. The other PRCM clock controller gained default bus clock rate settings. These were not configured in the upstream U-boot bootloader, leading to them running at slower rates. The assigned rates are from the user manual. There is also a new board, the NetCube Systems Nagami SoM and two of its carrier boards. The A523 family development boards now have their internal RTC clocks configured correctly, so that the RTC does not drift wildly. The missing functions for the AXP717 on these boards are added. Missing reset GPIOs and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its LEDs described and usable. An overlay for the Orange Pi Zero interface (addon) board was added. This can be used with the Orange Pi Zero and Zero Plus 2. Default audio routing for these two boards (to be used with the addon) were added to complement the overlay. * tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier ARM: dts: sunxi: add support for NetCube Systems Nagami SoM riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing ARM: dts: allwinner: orangepi-zero: Add default audio routing arm64: dts: allwinner: a523: Add NPU device node arm64: dts: allwinner: a523: Add MCU PRCM CCU node dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting arm64: dts: allwinner: a527: cubie-a5e: Add LEDs Link: https://lore.kernel.org/r/aMrtuZg8HlR--TAt@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-23 22:17:56 +02:00
Ryan Chen	8ea304cff0	dt-bindings: clock: ast2700: modify soc0/1 clock define ... -add SOC0_CLK_AHBMUX: add SOC0_CLK_AHBMUX for ahb clock source divide. mpll-> ahb_mux -> div_table -> clk_ahb hpll-> -new add clock: SOC0_CLK_MPHYSRC: UFS MPHY clock source. SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source. SOC1_CLK_I3C: I3C clock source. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 13:14:04 -07:00
Yao Zi	793e6b7480	dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible ... Document the clock controller shipped in Loongson-2K0300 SoC, which generates various clock signals for SoC peripherals. Differing from previous generations of SoCs, LS2K0300 requires a 120MHz external clock input. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 12:48:30 -07:00
Gabriel Fernandez	49f6c8b74d	dt-bindings: stm32: add STM32MP21 clocks and reset bindings ... Adds clock and reset binding entries for STM32MP21 SoC family. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 10:31:55 -07:00
Laura Nao	dd240e95f1	dt-bindings: clock: mediatek: Describe MT8196 clock controllers ... Introduce binding documentation for system clocks, functional clocks, and PEXTP0/1 and UFS reset controllers on MediaTek MT8196. This binding also includes a handle to the hardware voter, a fixed-function MCU designed to aggregate votes from the application processor and other remote processors to manage clocks and power domains. The HWV on MT8196/MT6991 is incomplete and requires software to manually enable power supplies, parent clocks, and FENC, as well as write to both the HWV MMIO and the controller registers. Because of these constraints, the HWV cannot be modeled using generic clock, power domain, or interconnect APIs. Instead, a custom phandle is exceptionally used to provide direct, syscon-like register access to drivers. Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Laura Nao <laura.nao@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 09:35:59 -07:00
AngeloGioacchino Del Regno	64e7df08ed	dt-bindings: clock: mt7622: Add AFE_MRGIF clock ... Add the missing AFE Merge Interface clock to MT7622 to make use of it in the audio subsystem. While at it, also remove the useless CLK_AUDIO_NR_CLK definition. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-21 09:31:43 -07:00
Troy Mitchell	8be1f29904	dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock ... Previously, the K1 clock driver did not include the parent clocks of the I2S sysclk. Introduce pre-clock to fix I2S clock. Otherwise, the I2S clock may not work as expected. This patch adds their definitions to allow proper registration in the driver and usage in the device tree. Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC") Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2025-09-19 22:54:40 -07:00
Duje Mihanović	5bcf9e1d0a	dt-bindings: clock: marvell,pxa1908: Add syscon compatible to apmu ... Add required syscon compatible and #power-domain-cells to the APMU controller. This is required for the SoC's power domain controller as the registers are shared. Device tree bindings for said power domains are also added. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>	2025-09-17 16:09:14 +02:00
Lad Prabhakar	8c01cc2382	dt-bindings: net: pcs: renesas,rzn1-miic: Add RZ/T2H and RZ/N2H support ... Add device tree binding support for RZ/T2H and RZ/N2H SoCs to the existing RZ/N1 MIIC converter binding. These SoCs share similar MIIC functionality but have architectural differences that require schema updates. Add new compatible strings "renesas,r9a09g077-miic" for RZ/T2H and "renesas,r9a09g087-miic" for RZ/N2H, with the latter falling back to the RZ/T2H variant. The new SoCs require reset support with two reset lines for converter register reset and converter reset, which are not present on RZ/N1. Update port configurations to accommodate the different architectures. RZ/N1 supports 5 ports numbered 1-5 with complex input mappings covering indices 0-13, while RZ/T2H and RZ/N2H support 4 ports numbered 0-3 with simplified input mappings covering indices 0-8. Extend the switch port configuration property to support value 0 for the new SoCs. Add a new dt-bindings header file with media interface connection matrix constants that map GMAC, ESC, and ETHSW ports to numeric identifiers for use with RZ/T2H and RZ/N2H device trees. Update DT schema validation to ensure proper port numbering and input mappings per SoC variant. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250910204132.319975-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>	2025-09-15 17:44:35 -07:00
Arnd Bergmann	b609d74217	This pull request contains Broadcom SoC drivers updates for 6.18: ... - Andrea adds the missing MIPI DSI clock defines for the RP1 and then continues to implement the remaining clocks for the RP1 chip (ADC, I2S, Audio in/out, DMA, MIPI, PWM, SDIO, UART, encoder) - Akhilesh fixes a spelling typo in the bcm47xx_sprom driver - Brian converts the RP1 clock driver to use the new determine_rate() API -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEm+Rq3+YGJdiR9yuFh9CWnEQHBwQFAmjBsfEACgkQh9CWnEQH BwRk7A//auWiAmOmrk/T5qV2v7whmnmafYO7blhwj9ltz496OnRJZtPExN7eLcze 9SaiPwP6vDjvys6nkfipsviT+E8UKRRqT7aEes/v6nqhGfuoNslTQyPKKzrgsoXm fOKgrsw6wDuUpp5nmkpDMJASFgYJd3xSH2SbZlwAizxuiSzGO8gMdxzo8oCMJ3tv 3NtzBuaVFScrpwX8/4fFdafQcxl0gWrEHx4bwDkhh5PFTL1/3tH10IcD1iuAwTvo 6DBndgYhqv7aA/N1hXuYZgnqVAApjpfGWcF1O8Hwq+3shcp/iOOSqFgnibq34yyv RU8wxE4OansaR1uVdrpSjrNmqRb14uNrBfZP/XOefpcu38YBeKF9WvBhmMzwoI94 sStmtpbzisXQnLF8MzOHH0byOO0BB1ITWZLeHoYtHmpvOqhhF2PFq9qCzpgKJnG8 G6P/IZDMxhFtvyQ/GPSTR8cqHtUMpOQ8K69Mz04gSFp2cAz4tYuKvtR3OVo5GfxI ibmcW2biTEh5y0sRdr/K7cZ3RgP82xsu2Ogeh6pKMUAJaaARwXpJD0/ozm96K0xH NaZDGlRwo4aeicdekLbrHmlwuACVYV7B7kQJy72Oe5ZIibdQ7T4ejMRqtjT3Sbg/ LMxW28rN2nQhgycgB3vV1QNJjCvHkedNFgpvWgF8XPIZ/Hp5VeQ= =qQ7G -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIGfIACgkQmmx57+YA GNmHJBAAqeytiS9Iz42+aE93AqI3uyzHELubQBYjWUcz88H/UNn3jjnlPUIOJFgX m/Xcgqnj5tgBkVqcwPl38GyV3Sd8EgerwP47mrt36JTVgK3EgsDeSUJs/sRNHrD/ R8rhScthlETwAr4uApcL+SPIcENuf6kk8AyIrP1kFyyq6bOHzVbEJVCT0qFqzQfn MDLy3BxJKbhgW7EX5Mg20OhuI4Kezk+lRpWwVszqhXe9mfMLuB+egS/gLKbvsF1Q rsL+aL3MvTDh0Ya+lX9NCs5o6j/YcFr5507TwupLg6ZJUBgzm82FEWjyU4641V8H LtFmgouekG1boKKX+pA3Ow5lwiAKXGxhB/0DR4OMBqDhWoD+LyycqyKvBGQVFon2 q3T8ywQLkKcpPD5VcmgWSHdsqK+vNq83k31etZK/pTlzso/pcm2fEoHBkE0bo8cS YwNPuDwAQ7D9o50T4Pa9FnGhU0y9qGvt3nD5ZjyN3DKyjVeWsnPZvpkiNMCi58Xt 4+bKNSEHqOi4CnIfbpu0CEy1RY8C4/exKDO4rWOcfdEo8u7hW8IwD7crNzY3vQ0q Kq2xbVfTJorFzNSZ1x6VlkHp2UrjyruDek2sjn/BsIvz2uGACLARIZrYS+681wPW MW4wizuVXQRfCqrJPDxLa+CnQwmbZ/Fc2wWq8H7tScI+F6h67JA= =5iR8 -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux into soc/drivers This pull request contains Broadcom SoC drivers updates for 6.18: - Andrea adds the missing MIPI DSI clock defines for the RP1 and then continues to implement the remaining clocks for the RP1 chip (ADC, I2S, Audio in/out, DMA, MIPI, PWM, SDIO, UART, encoder) - Akhilesh fixes a spelling typo in the bcm47xx_sprom driver - Brian converts the RP1 clock driver to use the new determine_rate() API * tag 'arm-soc/for-6.18/drivers' of https://github.com/Broadcom/stblinux: clk: rp1: convert from round_rate() to determine_rate() drivers: firmware: bcm47xx_sprom: fix spelling clk: rp1: Implement remaining clock tree dt-bindings: clock: rp1: Add missing MIPI DSI defines Link: https://lore.kernel.org/r/20250910171910.666401-4-florian.fainelli@broadcom.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-15 15:51:46 +02:00
Arnd Bergmann	431ab7953c	dt-bindings: Changes for v6.18-rc1 ... Support for the Tegra264 generation of I2C is documented as well as some older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices. Contained are also some additions to existing bindings for Tegra114 and a fix for the power supply feeding VI/CSI. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmjGXQgACgkQ3SOs138+ s6GLdBAApTnTZi8zBPYkQF2/j2Ua/qkH93E1Oos9Ng8PgP0n/ObS2I/qqLABsnur Q7EDesxKsDMI9VsLEazl2Pp0HCIPoqCRnlSWVkCp+G3JJ+RMeP+fFtEycTqZiiu6 eIx9iQbAujXCdsIzYCx6cq21yyWoBnqTD/pkB7jqA1zpQazgnCHxjBJbCfC+wecY 6B/ygsr6kaKJwH2ISPBGm7tVuunQZR3ZJEWfo//LVqPcG26xEYmyrvvE7k3UvGIP Njntp1x4trFTf6WcGalNyvcVn2dQWxc54gBQbi5oL4TfBfEO3Eb+tRcaIQa4zGyu RKTn3ZwvO9AnqBQx6Jnwyh9lu3LJPIp/BaNkztz9JXTPl64wo2OQ4nvqzwvCr8ws fvrOFfgolKBarxjupfiKFITcB1pAgtN0WeHg64pd+D7JxJ4T6A3818VswQLsltrO 1JyPYVLvzsaHjOPmLckXiv42Y3FX7um6x0nu8ZgNEEWCIpbedc97gR+cFv7TkFue MENuesWqyGZ+5iI2zXDe/V6hQAcHAZvJgxEvnJ0YDbcK07hKlEKyen91Q6OgIG5D lOfj3M0IxnFjKgKnChjVfGAY8rgq0Dt04hWdpsR8G9cmle7tWvSQfTRoDrCbf/Nv VP2mB+A3D9PNZHO5ooqIAXCUIbmRnAVmrOUHUC0EFWYa06ZBHBM= =w8Ms -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIFn0ACgkQmmx57+YA GNlyDA/9H3YR2fM91GmzvLLJMsmb19g/NKlg7NS0DkCtmd6k41xK7Rs0IZOjZbqi rwI09Ns55B1TP1YNHzLEE00FOo5VXW8LLxjaGqi9IKHZyhlArXigo6SC7Gtzw343 S/plUjZRXJh11z0KHs+BSuimmGrmBh7esd1pRKj5SRE3GmISY0WzC0OUXp2mcVnM ZqXA1VgnNcDiAQ1IcTK3s2cvGmllKA1bOgXM1SxJiiFyvzcNpadpFXypla4YWUNa oMh9Ey/H5gQ6SZ/ije5b85UgAN/G09O3LoPaVeP3KzerPGhjo//la0/YglMdmT0m 3IU0SChnlRth+xgKME3Gg7cCyaA5I5o91imtr4XdQVo8AZoJa5XrII3RgzGG5obb 48Qe801koOTxQHfmOQ1GRO6+L4PZLQrNRQPsTYHdV6vpRjmoU9h4foox7ELpKT8s 7TWNhsfkQu+jkB99iN0F1zQmIRJGAhovOAG6RRD+W3M5tEUonH/7e0cBJBu55vUk eQMWxs04aIuxHukZ45WgjPcGnOTPBFsDqARLR5t3jYgC8vaOCkGZNaPLLbIyOEJB 1FhuQIJwhwHgVCS4ejDa6vt57WXyIXq7YNORBnabaHrJrsdrJ4fEAZo33i2mKrl1 M32HOMB1YbfP5Mf5KNWRs6g5wn9LOqzbSEBGh52y3mYfDvWgHrw= =TNku -----END PGP SIGNATURE----- Merge tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt dt-bindings: Changes for v6.18-rc1 Support for the Tegra264 generation of I2C is documented as well as some older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices. Contained are also some additions to existing bindings for Tegra114 and a fix for the power supply feeding VI/CSI. * tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: arm: tegra: Add ASUS TF101G and SL101 dt-bindings: reset: Add Tegra114 CAR header dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101) dt-bindings: clock: tegra30: Add IDs for CSI pad clocks dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C Link: https://lore.kernel.org/r/20250914063927.89981-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-15 15:37:01 +02:00
Arnd Bergmann	a3ef7cad8b	Qualcomm Arm64 DeviceTree updates for v6.18 ... Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude 7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the Lemans EVK. The SDM845 Cheza development boards are removed, as they are not longer in use. For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO buses are added and the internal GE PHY. IPQ5424 gets CPU frequency scaling and a missing UART. The SA8775P SoC is remaned Lemans, to reduce confusion about the chip name. The IoT memory map introduced and made the default, GDSP FastRPC and GPR nodes are added. Touch keys are enabled on the BQ Aquaris X5 Plus. On QCM2290 the video accelerator is enabled, so is HS timing modes for eMMC. The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi PCIe controller is introduced. On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is eMMC support and generic packer router (GPR). On the Monaco Ride board, the eMMC controller is enabled. On QRB220 RB1, the venus video accelerator is enabled. For SC7280 the first PCIe controller and PHY is introduced. SoundWire, LPASS, and USB offload support is added, the codecs and sound card is then described on the QCM6490 IDP. The MDSS core reset is introduced, to clear bootloader configuration on SC7280-based devices. On Fairphone5, USB audio offload is added. AudioReach support on SC7280 (QCS6490) is introduced and used to enable sound on the RB3Gen2 board. The video clock controller is added to SC8180X. On SC8280XP the GPI DMA controllers are described and enabled. Display and GPU is enabled for the Fairphone 3 and charging is enabled on the Google Pixel 3a. The routing for the second USB connector on the Lenovo Yoga C630 is described. On SM6150 ADSP and CDSP FastRPC is introduced, as is the video encoder/decoder (venus). On SM6350 RPMh statistics is enabled, the USB audio offload DAI is introduced and on Fairphone4 the USB audio offload support is enabled. On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery functionality. On SM8650 ACD levels are added for the GPU. Camera and video clock controllers power-domains are updated on SM8450, SM8550, and SM8650, now that support for multiple power-domains is accepted. SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes. The DWC3 glue and core nodes are flattened on a number of platforms. USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a variety of platforms, now that the QMP PHY driver supports this. Platform specific RPMh PD constants are replaced with generic constants wherever possible. On X Elite the PM8010 is disabled by default, removing boot splats on a variety of boards without this PMIC, the video clock controller is added. For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is marked as valid for the external DisplayPorts. The fingerprint reader found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled. The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support. 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The SDM845 Cheza development boards are removed, as they are not longer in use. For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO buses are added and the internal GE PHY. IPQ5424 gets CPU frequency scaling and a missing UART. The SA8775P SoC is remaned Lemans, to reduce confusion about the chip name. The IoT memory map introduced and made the default, GDSP FastRPC and GPR nodes are added. Touch keys are enabled on the BQ Aquaris X5 Plus. On QCM2290 the video accelerator is enabled, so is HS timing modes for eMMC. The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi PCIe controller is introduced. On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is eMMC support and generic packer router (GPR). On the Monaco Ride board, the eMMC controller is enabled. On QRB220 RB1, the venus video accelerator is enabled. For SC7280 the first PCIe controller and PHY is introduced. SoundWire, LPASS, and USB offload support is added, the codecs and sound card is then described on the QCM6490 IDP. The MDSS core reset is introduced, to clear bootloader configuration on SC7280-based devices. On Fairphone5, USB audio offload is added. AudioReach support on SC7280 (QCS6490) is introduced and used to enable sound on the RB3Gen2 board. The video clock controller is added to SC8180X. On SC8280XP the GPI DMA controllers are described and enabled. Display and GPU is enabled for the Fairphone 3 and charging is enabled on the Google Pixel 3a. The routing for the second USB connector on the Lenovo Yoga C630 is described. On SM6150 ADSP and CDSP FastRPC is introduced, as is the video encoder/decoder (venus). On SM6350 RPMh statistics is enabled, the USB audio offload DAI is introduced and on Fairphone4 the USB audio offload support is enabled. On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery functionality. On SM8650 ACD levels are added for the GPU. Camera and video clock controllers power-domains are updated on SM8450, SM8550, and SM8650, now that support for multiple power-domains is accepted. SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes. The DWC3 glue and core nodes are flattened on a number of platforms. USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a variety of platforms, now that the QMP PHY driver supports this. Platform specific RPMh PD constants are replaced with generic constants wherever possible. On X Elite the PM8010 is disabled by default, removing boot splats on a variety of boards without this PMIC, the video clock controller is added. For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is marked as valid for the external DisplayPorts. The fingerprint reader found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled. The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support. GPU support is added for the X Plus SoC. * tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits) arm64: dts: qcom: x1e80100: Update GPU OPP table arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC arm64: dts: qcom: add initial support for Samsung Galaxy S20 dt-bindings: arm: qcom: document x1q board binding arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi arm64: dts: qcom: lemans-evk: Add sound card arm64: dts: qcom: lemans: Add gpr node arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec arm64: dts: qcom: sm6150: add venus node to devicetree arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT arm64: dts: qcom: qrb2210-rb1: Enable Venus arm64: dts: qcom: qcm2290: Add Venus video node arm64: dts: qcom: monaco-evk: Add sound card arm64: dts: qcom: qcs8300: Add gpr node arm64: dts: qcom: qcs8300: Add Monaco EVK board dt-bindings: arm: qcom: Add Monaco EVK support arm64: dts: qcom: qcm6490-idp: Add sound card arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec arm64: dts: qcom: qcs6490-rb3gen2: Add sound card ... Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>	2025-09-15 15:26:24 +02:00
Chen-Yu Tsai	0f610e650d	dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller ... There are four clock controllers in the A523 SoC. The existing binding already covers two of them that are critical for basic operation. The remaining ones are the MCU clock controller and CPU PLL clock controller. Add a description for the MCU CCU. This unit controls and provides clocks to the MCU (RISC-V) subsystem and peripherals meant to operate under low power conditions. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>	2025-09-13 13:49:09 +08:00
Chen-Yu Tsai	e9671ddd82	dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock ... The main clock controller on the A523/T527 has the NPU's module clock. It was missing from the original submission, likely because that was based on the A523 user manual; the A523 is marketed without the NPU. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>	2025-09-13 13:49:08 +08:00
Geert Uytterhoeven	9bb55594ef	Renesas RZ/G3E USB3.0 Core Clock DT Binding Definitions ... USB3.0 core clock DT binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaMMSmgAKCRCKwlD9ZEnx cJB8AP4nPlMcqXBlXtMQuVHpghrH5UxKlTYeXlSWUJXhOf71hgEA9vc/PCVU+Vez QEMiNHrOINDlfXhIN8QAOvQdOtF/gAo= =Oxy/ -----END PGP SIGNATURE----- Merge tag 'renesas-r9a09g047-dt-binding-defs-tag4' into renesas-clk-for-v6.18 Renesas RZ/G3E USB3.0 Core Clock DT Binding Definitions USB3.0 core clock DT binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.	2025-09-12 09:53:27 +02:00
Biju Das	a24cd110e6	dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks ... Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings header file. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20250909180803.140939-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2025-09-11 20:17:28 +02:00
Svyatoslav Ryhel	7526e6db47	dt-bindings: reset: Add Tegra114 CAR header ... The way that resets are handled on these Tegra devices is that there is a set of peripheral clocks & resets which are paired up. This is because they are laid out in banks within the CAR (clock and reset) controller. In most cases we're referring to those resets, so you'll often see a clock ID used in conjection with the same reset ID for a given IP block. In addition to those peripheral resets, there are a number of extra resets that don't have a corresponding clock and which are exposed in registers outside of the peripheral banks, but still part of the CAR. To support those "special" registers, the TEGRA*_RESET() is used to denote resets outside of the regular peripheral resets. Essentially it defines the offset within the CAR at which special resets start. In the above case, Tegra114 has 5 banks with 32 peripheral resets each. The first special reset, TEGRA114_RESET(0), therefore gets ID 5 * 32 + 0 = 160. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>	2025-09-11 18:28:35 +02:00
Svyatoslav Ryhel	fc02f529a8	dt-bindings: clock: tegra30: Add IDs for CSI pad clocks ... Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers. Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into clk-tegra30 source. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>	2025-09-11 18:03:10 +02:00
Aaron Kling	5f5598d945	dt-bindings: memory: tegra210: Add memory client IDs ... Each memory client has unique hardware ID, add these IDs. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-09-10 11:40:38 +02:00
Hans Verkuil	e8c8d961d8	media: include: update Hans Verkuil's email address ... Replace hverkuil@xs4all.nl by hverkuil@kernel.org. Signed-off-by: Hans Verkuil <hverkuil@kernel.org> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>	2025-09-09 15:58:56 +02:00
Ryan Chen	ed7240444e	dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles ... Add compatible strings for the four SCU interrupt controller instances on the AST2700 SoC (scu-ic0 to 3), following the multi-instance model used on AST2600. Also define interrupt indices in the binding header. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/all/20250908011812.1033858-4-ryan_chen@aspeedtech.com	2025-09-09 12:23:28 +02:00
Denzeel Oliva	43bd82eb33	dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units ... Add clock management unit bindings for PERIC0 and PERIC1 blocks which provide clocks for USI, I2C and UART peripherals. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-09-07 11:10:55 +02:00
Denzeel Oliva	eb9bc16277	dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block ... Add the missing LHS_ACEL clock ID for the HSI0 block. This clock is required for proper USB operation, as without it, USB connections fail with errors like device descriptor read timeouts and address response issues. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250831-usb-v2-1-00b9c0559733@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2025-09-04 15:47:40 +02:00
Bjorn Andersson	154691e7c9	Merge branch '20250903-msm8937-v9-1-a097c91c5801@mainlining.org' into clk-for-6.18 ... Merge the MSM8937 global clock controller binding through a topic branch to allow merging the constants into the DeviceTree branch as well.	2025-09-04 08:38:00 -05:00
Barnabás Czémán	4d32c1f66a	dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller ... Add device tree bindings for the global clock controller on Qualcomm MSM8937 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20250903-msm8937-v9-1-a097c91c5801@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-04 08:37:53 -05:00
hongyu.chen1	9428fff44f	dt-bindings: power: add Amlogic S6 S7 S7D power domains ... Add devicetree binding document and related header file for Amlogic S6 S7 S7D secure power domains. Signed-off-by: hongyu.chen1 <hongyu.chen1@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250822-pm-s6-s7-s7d-v1-1-82e3f3aff327@amlogic.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>	2025-09-04 12:21:25 +02:00
Lad Prabhakar	0dcfb6fcdd	dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs ... Add clock definitions for Ethernet (ETCLK A-E) to both R9A09G077 and R9A09G087 SoCs. These definitions are required for describing Ethernet devices in DT. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250904071954.3176806-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2025-09-04 11:26:06 +02:00
Taniya Das	ee2d967030	dt-bindings: clock: qcom: document the Glymur Global Clock Controller ... Add device tree bindings for global clock controller on Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:15:43 -05:00
Taniya Das	ae5b84788e	dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller ... The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe and USB. Add this to the TCSR clock controller binding together with identifiers for the clocks. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-2-01b8c8681bcd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 18:14:44 -05:00
Taniya Das	781c118c3e	dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC ... Add the device tree bindings for the display clock controller which are required on Qualcomm Glymur SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com [bjorn: Dropped unnecessary include in DT example] Signed-off-by: Bjorn Andersson <andersson@kernel.org>	2025-09-03 17:13:16 -05:00