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Author SHA1 Message Date
Linus Torvalds
522ba450b5 There's a bunch of patches here across drivers/clk/ to migrate drivers to use 
struct clk_ops::determine_rate() instead of the round_rate() one so that we can
 remove the round_rate clk_op entirely. Brian has taken up that task which
 nobody else has wanted to do for close to a decade. Thanks Brian! This is all
 prerequisite work to get to the real task of improving the clk rate setting
 process. Once we have determine_rate() used everywhere, we'll be able to do
 things like chain the rate request structs in linked lists to order the rate
 setting operations or add more parameters without having to change every clk
 driver in existence. It's also nice to not have multiple ways to do something
 which just causes confusion for clk driver authors. Overall I'm glad this is
 getting done.
 
 Beyond this change we also have a tweak to the clk_lookup() function in the
 core framework to use hashing on the clk name instead of a clk tree walk with
 string comparisons. We _still_ rely on the clk name to be unique, because
 historically we've used globally unique strings to describe the clk tree
 topology. This tree walk becomes increasingly slow as more clks are added to
 the system. Searching from the roots for a duplicate is simple but pretty dumb
 and it wastes boot time so we're using a hash table as an improvement. Ideally
 we wouldn't rely on the strings to be unique at all, relegating them to simply
 debug information, but that is future work that will likely require some sort
 of Kconfig knob indicating strings aren't used for topology description.
 
 Outside of the core framework changes we have the usual new SoC support and
 fixes to clk drivers for things that were discovered once the clks were used by
 consumer drivers. Nothing in particular is jumping out at me in the "misc"
 pile, except maybe the Amlogic driver that has gone through a refactoring. That
 series got a fix from testing in -next though so it seems likely that things
 have been getting good test coverage for a couple weeks already.
 -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmjkoQAUHHN3Ym95ZEBj
 aHJvbWl1bS5vcmcACgkQrQKIl8bklSWfWBAA3cjpOX/qOBDPmYPvV+WgiTPcmnw+
 PaMiGNqIWctnJiuYYUNVCfBIvTk9i1vYSgEosHAOqjXQV+7Ee31420xn5RYr6Zen
 cfeD58SJwZ1JVidvxwWclC5pnfTVXBC3wlHILCFHhckaGOT2k3d0ryN2io2TYuRx
 t9JsoW73YW+bmOWoFDHPMp4ow5Q87aa8k3/srhIP67tw2mzJp8Wp+EG0t0PVFF7Z
 aboz+QPwyT2YOLFKJxm6nTLb9FRVq3QLSO3Ek0+0TYXfRqkfegvGR+M82P4Jq2Y3
 osmTsumWeI170iAETmx2Py+uUV8MmnvPFQ6mxrGoXYyOx9SclN+SC86cOsi+RsgD
 830CHupZ/TrN3+DGyX6WVx1j7XKCplKhFXrXiFbkPnj4nJwi5UgiJrjAjPy78+iX
 LyvKfeT9ooAAVBVRMyZIWGF3kuQf5qHFMps5fwJk/j3R9yMiI10SVhruhYij1qAi
 EEisj955xqdyZV2gq85E7zHbjySA0nvNABn3NVUQOKPYQqtpglqXKGJuXZ1//9pa
 fZM2a3fH7w4fwH1x06FKut9zf1AZUgyasJPtgyCT9dpN+pcoNmJfoH3T42MCItbm
 XKEYgnv/kQT+M+GokBUfg8bJY5uPnPLa/f6aAAIAKGZV0HXAqz2q73SDlW7KUQmr
 vhgA4MRH4Vqviic=
 =fjY4
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "There's a bunch of patches here across drivers/clk/ to migrate drivers
  to use struct clk_ops::determine_rate() instead of the round_rate()
  one so that we can remove the round_rate clk_op entirely. Brian has
  taken up that task which nobody else has wanted to do for close to a
  decade. Thanks Brian!

  This is all prerequisite work to get to the real task of improving the
  clk rate setting process. Once we have determine_rate() used
  everywhere, we'll be able to do things like chain the rate request
  structs in linked lists to order the rate setting operations or add
  more parameters without having to change every clk driver in
  existence. It's also nice to not have multiple ways to do something
  which just causes confusion for clk driver authors. Overall I'm glad
  this is getting done.

  Beyond this change we also have a tweak to the clk_lookup() function
  in the core framework to use hashing on the clk name instead of a clk
  tree walk with string comparisons. We _still_ rely on the clk name to
  be unique, because historically we've used globally unique strings to
  describe the clk tree topology. This tree walk becomes increasingly
  slow as more clks are added to the system. Searching from the roots
  for a duplicate is simple but pretty dumb and it wastes boot time so
  we're using a hash table as an improvement. Ideally we wouldn't rely
  on the strings to be unique at all, relegating them to simply debug
  information, but that is future work that will likely require some
  sort of Kconfig knob indicating strings aren't used for topology
  description.

  Outside of the core framework changes we have the usual new SoC
  support and fixes to clk drivers for things that were discovered once
  the clks were used by consumer drivers. Nothing in particular is
  jumping out at me in the "misc" pile, except maybe the Amlogic driver
  that has gone through a refactoring. That series got a fix from
  testing in -next though so it seems likely that things have been
  getting good test coverage for a couple weeks already"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits)
  clk: microchip: core: remove duplicate roclk_determine_rate()
  reset: aspeed: register AST2700 reset auxiliary bus device
  dt-bindings: clock: ast2700: modify soc0/1 clock define
  clk: tegra: do not overallocate memory for bpmp clocks
  clk: ep93xx: Use int type to store negative error codes
  clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
  clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
  clk: loongson2: Avoid hardcoding firmware name of the reference clock
  clk: loongson2: Allow zero divisors for dividers
  clk: loongson2: Support scale clocks with an alternative mode
  clk: loongson2: Allow specifying clock flags for gate clock
  dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
  clk: clocking-wizard: Fix output clock register offset for Versal platforms
  clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()
  clk: mmp: pxa1908: Instantiate power driver through auxiliary bus
  clk: s2mps11: add support for S2MPG10 PMIC clock
  dt-bindings: clock: samsung,s2mps11: add s2mpg10
  dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
  clk: stm32: introduce clocks for STM32MP21 platform
  dt-bindings: stm32: add STM32MP21 clocks and reset bindings
  ...
 2025-10-07 09:28:37 -07:00
Stephen Boyd
f35f83208c
Merge branches 'clk-aspeed' and 'clk-rockchip' into clk-next 
* clk-aspeed:
  reset: aspeed: register AST2700 reset auxiliary bus device
  dt-bindings: clock: ast2700: modify soc0/1 clock define

* clk-rockchip:
  clk: rockchip: rk3368: use clock ids for SCLK_MIPIDSI_24M
  dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M
 2025-10-06 13:00:50 -05:00
Stephen Boyd
8397c58ea7
Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next 
- Add Mediatek MT8196 clk drivers

* clk-marvell:
  clk: mmp: pxa1908: Instantiate power driver through auxiliary bus

* clk-xilinx:
  clk: clocking-wizard: Fix output clock register offset for Versal platforms
  clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()

* clk-mediatek: (31 commits)
  clk: mediatek: Add MT8196 vencsys clock support
  clk: mediatek: Add MT8196 vdecsys clock support
  clk: mediatek: Add MT8196 ovl1 clock support
  clk: mediatek: Add MT8196 ovl0 clock support
  clk: mediatek: Add MT8196 disp-ao clock support
  clk: mediatek: Add MT8196 disp1 clock support
  clk: mediatek: Add MT8196 disp0 clock support
  clk: mediatek: Add MT8196 mfg clock support
  clk: mediatek: Add MT8196 mdpsys clock support
  clk: mediatek: Add MT8196 mcu clock support
  clk: mediatek: Add MT8196 I2C clock support
  clk: mediatek: Add MT8196 pextpsys clock support
  clk: mediatek: Add MT8196 ufssys clock support
  clk: mediatek: Add MT8196 peripheral clock support
  clk: mediatek: Add MT8196 vlpckgen clock support
  clk: mediatek: Add MT8196 topckgen2 clock support
  clk: mediatek: Add MT8196 topckgen clock support
  clk: mediatek: Add MT8196 apmixedsys clock support
  dt-bindings: clock: mediatek: Describe MT8196 clock controllers
  clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
  ...

* clk-loongson:
  clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
  clk: loongson2: Avoid hardcoding firmware name of the reference clock
  clk: loongson2: Allow zero divisors for dividers
  clk: loongson2: Support scale clocks with an alternative mode
  clk: loongson2: Allow specifying clock flags for gate clock
  dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
 2025-10-06 13:00:22 -05:00
Stephen Boyd
b91217d912
Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next 
- Speed up clk_core_lookup() by using a hashtable

* clk-microchip:
  ARM: at91: remove default values for PMC_PLL_ACR
  clk: at91: add ACR in all PLL settings
  clk: at91: sam9x7: Add peripheral clock id for pmecc
  clk: at91: clk-master: Add check for divide by 3
  clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
  ARM: at91: pm: save and restore ACR during PLL disable/enable

* clk-lookup:
  clk: Use hashtable for global clk lookups
  clk: Sort include statements

* clk-st:
  dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
  clk: stm32: introduce clocks for STM32MP21 platform
  dt-bindings: stm32: add STM32MP21 clocks and reset bindings
 2025-10-06 13:00:12 -05:00
Stephen Boyd
f0fd248204
Merge branches 'clk-scmi', 'clk-qcom' and 'clk-broadcom' into clk-next 
* clk-scmi:
  clk: scmi: Add duty cycle ops only when duty cycle is supported

* clk-qcom: (27 commits)
  clk: qcom: gcc-sc8280xp: drop obsolete PCIe GDSC comment
  clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclk
  clk: qcom: dispcc-glymur: Constify 'struct qcom_cc_desc'
  clk: qcom: gcc: Add support for Global Clock controller found on MSM8937
  dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller
  clk: qcom: Select the intended config in QCS_DISPCC_615
  clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register()
  clk: qcom: alpha-pll: convert from round_rate() to determine_rate()
  clk: qcom: milos: Constify 'struct qcom_cc_desc'
  clk: qcom: gcc: Add support for Global Clock Controller
  dt-bindings: clock: qcom: document the Glymur Global Clock Controller
  clk: qcom: clk-alpha-pll: Add support for Taycan EKO_T PLL
  clk: qcom: rpmh: Add support for Glymur rpmh clocks
  clk: qcom: Add TCSR clock driver for Glymur SoC
  dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller
  dt-bindings: clock: qcom-rpmhcc: Add support for Glymur SoCs
  clk: qcom: dispcc-glymur: Add support for Display Clock Controller
  dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC
  clk: qcom: gcc-sdm660: Add missing LPASS/CDSP vote clocks
  dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs
  ...

* clk-broadcom:
  clk: bcm: rpi: Maximize V3D clock
  clk: bcm: rpi: Turn firmware clock on/off when preparing/unpreparing
  clk: bcm: rpi: Add missing logs if firmware fails
 2025-10-06 12:57:03 -05:00
Stephen Boyd
c1e102f349
Merge branches 'clk-imx', 'clk-allwinner' and 'clk-ti' into clk-next 
* clk-imx:
  clk: imx95-blk-ctl: Save/restore registers when RPM routines are called
  clk: imx95-blk-ctl: Save platform data in imx95_blk_ctl structure

* clk-allwinner:
  clk: sunxi-ng: add support for the A523/T527 MCU CCU
  clk: sunxi-ng: div: support power-of-two dividers
  clk: sunxi-ng: sun55i-a523-ccu: Add missing NPU module clock
  dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
  dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock
  clk: sunxi-ng: sun6i-rtc: Add A523 specifics

* clk-ti:
  clk: keystone: sci-clk: use devm_kmemdup_array()
  clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabled
 2025-10-06 12:56:54 -05:00
Stephen Boyd
3aae991cc2
Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next 
* clk-samsung:
  clk: s2mps11: add support for S2MPG10 PMIC clock
  dt-bindings: clock: samsung,s2mps11: add s2mpg10
  clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
  dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
  clk: samsung: exynos990: Add missing USB clock registers to HSI0
  clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
  dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
  clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
  clk: samsung: Add clock PLL support for ARTPEC-8 SoC
  dt-bindings: clock: Add ARTPEC-8 clock controller
  clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
  dt-bindings: clock: exynos990: Extend clocks IDs
  clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
  clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
  clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
  clk: samsung: pll: convert from round_rate() to determine_rate()
  clk: samsung: cpu: convert from round_rate() to determine_rate()
  clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
  dt-bindings: clock: Add CAM_CSI clock macro for FSD

* clk-tegra:
  clk: tegra: dfll: Add CVB tables for Tegra114
  clk: tegra: Add DFLL DVCO reset control for Tegra114
  dt-bindings: arm: tegra: Add ASUS TF101G and SL101
  dt-bindings: reset: Add Tegra114 CAR header
  dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
  dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
  dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
  dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C

* clk-amlogic:
  clk: amlogic: fix recent code refactoring
  clk: amlogic: c3-peripherals: use helper for basic composite clocks
  clk: amlogic: align s4 and c3 pwm clock descriptions
  clk: amlogic: add composite clock helpers
  clk: amlogic: use the common pclk definition
  clk: amlogic: introduce a common pclk definition
  clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
  clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
  clk: amlogic: move PCLK definition to clkc-utils
  clk: amlogic: aoclk: use clkc-utils syscon probe
  clk: amlogic: use probe helper in mmio based controllers
  clk: amlogic: add probe helper for mmio based controllers
  clk: amlogic: drop meson-clkcee
  clk: amlogic: naming consistency alignment
 2025-10-06 12:56:46 -05:00
Stephen Boyd
ec7336475d
Merge branches 'clk-bindings', 'clk-cleanup', 'clk-renesas', 'clk-thead' and 'clk-spacemit' into clk-next 
* clk-bindings:
  dt-bindings: clock: mediatek: Add power-domains property
  dt-bindings: clock: silabs,si5341: Add missing properties
  dt-bindings: clock: adi,axi-clkgen: add clock-output-names property
  dt-bindings: clock: Remove unused fujitsu,mb86s70-crg11 binding
  dt-bindings: clock: Convert silabs,si570 to DT schema
  dt-bindings: clock: Convert silabs,si5341 to DT schema
  dt-bindings: clock: Convert silabs,si514/544 to DT schema

* clk-cleanup:
  clk: tegra: do not overallocate memory for bpmp clocks
  clk: ep93xx: Use int type to store negative error codes
  dt-bindings: clock: st: flexgen: remove deprecated compatibles
  clk: st: flexgen: remove unused compatible
  clk: clk-axi-clkgen: remove unneeded semicolon
  clk: tegra: Remove redundant semicolons
  clk: npcm: select CONFIG_AUXILIARY_BUS
  clk: remove unneeded 'fast_io' parameter in regmap_config

* clk-renesas: (27 commits)
  clk: renesas: r9a09g05[67]: Reduce differences
  clk: renesas: r9a09g047: Add USB3.0 clocks/resets
  clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()
  clk: renesas: r9a09g056: Add clock and reset entries for I3C
  clk: renesas: r9a09g057: Add clock and reset entries for I3C
  dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks
  clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks
  clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()
  clk: renesas: rzv2h: Re-assert reset on deassert timeout
  clk: renesas: rzg2l: Re-assert reset on deassert timeout
  clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()
  dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs
  clk: renesas: r9a09g047: Add GPT clocks and resets
  clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5
  clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()
  clk: renesas: rzg2l: convert from round_rate() to determine_rate()
  clk: renesas: r9a07g04[34]: Use tabs instead of spaces
  clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL
  clk: renesas: r9a07g044: Add MSTOP for RZ/G2L
  clk: renesas: r9a08g045: Add MSTOP for GPIO
  ...

* clk-thead:
  clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
  clk: thead: support changing DPU pixel clock rate
  clk: thead: add support for enabling/disabling PLLs
  clk: thead: Correct parent for DPU pixel clocks
  clk: thead: th1520-ap: fix parent of padctrl0 clock
  clk: thead: th1520-ap: describe gate clocks with clk_gate

* clk-spacemit:
  clk: spacemit: fix i2s clock
  clk: spacemit: introduce pre-div for ddn clock
  dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock
  clk: spacemit: ccu_pll: convert from round_rate() to determine_rate()
  clk: spacemit: ccu_mix: convert from round_rate() to determine_rate()
  clk: spacemit: ccu_ddn: convert from round_rate() to determine_rate()
  clk: spacemit: fix sspax_clk
  dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA
 2025-10-06 12:56:23 -05:00
Linus Torvalds
d955299b5c soc: build fix for 6.18 
One commit for the dt bindings was missing from the dt branch, this
 one is already pending in the clk tree that contains the corresponding
 device driver.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmje970ACgkQYKtH/8kJ
 UieWdQ/9EKbkRWleVJ9Cuz4oX1vOv6TKISkboqb4b7ZFh56AKV/PeVanAiy+wsaI
 tnVuiIi8aVBiPxddi4xVY4+RaRp0ZjaOEDYhxvJ1huc1p7i0I4viHo0G4MYflgbM
 Db+yjqaSGMfpKEcWJSmtVt1qZF89t/8ZE0vlPxQ0Z+wAqTEX3b6zofI1UnAiFtGH
 vgvXcW6798n+czaZulE98tC+oAWlrbyruVh0SC8q7UfchCrCFsJQYSkw9GecmoaR
 RS48mM+JHdKxgHsNXR5qbWkktHcsvC8TJ8Jscxqn71cJYB1TldGEdBAEpfxlVkYD
 rWbCr6mr6XHg0N/5yVF0n5VwLESGJeUhRsFMiBUHfq9HgWred6iwP/pu6LQGWaKE
 fKUDlM/ukTzuyVaG1Ipxr9wbecpIHlETmaVSBZMrBHYj0hSeDvV5qVkKHORYX/QN
 OdtIcIsoez7VReqhnHIBy/MNRbLrZZCkEscX6H2i41d7pXDmFdBZZIGTN7W9kuNx
 DEvPVJtXznLxTIOawftoB1AG/PBUaa8zLZ6w/7DmFXx4rRSztyBmYV14bE86JTwF
 y0Hux3DHaAYtj4qI25awwzMLdNyMDc7BQry9fF/5wdZYBzAHbbv1OEZ/J+Fm6YNn
 q4ERE7NpB8TVG1DAFuKrzI4OsFxHzurco2snso5yY8OYvDn/BMs=
 =DlPR
 -----END PGP SIGNATURE-----

Merge tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC build fix from Arnd Bergmann:
 "One commit for the dt bindings was missing from the dt branch, this
  one is already pending in the clk tree that contains the corresponding
  device driver"

* tag 'soc-fixes-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  dt-bindings: clock: Add ARTPEC-8 clock controller
 2025-10-03 19:36:39 -07:00
Linus Torvalds
38057e3236 soc: driver updates for 6.18 
Lots of platform specific updates for Qualcomm SoCs, including a
 new TEE subsystem driver for the Qualcomm QTEE firmware interface.
 
 Added support for the Apple A11 SoC in drivers that are shared with the
 M1/M2 series, among more updates for those.
 
 Smaller platform specific driver updates for Renesas, ASpeed, Broadcom,
 Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs.
 
 Driver updates in the cache controller, memory controller and reset
 controller subsystems.
 
 SCMI firmware updates to add more features and improve robustness.
 This includes support for having multiple SCMI providers in a single
 system.
 
 TEE subsystem support for protected DMA-bufs, allowing hardware to
 access memory areas that managed by the kernel but remain inaccessible
 from the CPU in EL1/EL0.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdpaoACgkQmmx57+YA
 GNnBXA//QgmFXYGG7QfB825mt0orKZxpfpLcwvqO7hkWgbXtl7Gokw2lGYN6bwLu
 zvY4MQ/bVoZ8R5uTVmuaSHBRsttSen8mBf+V0vzsBM/DRRVxvIN/7TESrY3J7Dtx
 J5syHKIBiUtdkDebWWC6jIElczIBItsd03Ln4Xjjt8Vas5YOO4n44zFrPo+FwlN/
 I6D2K86AiNZTtUCDMtB6VfJ6YtjYBWcWnJm7FXw/vE8FAXdZUnNWnZ8hbdQ5GaME
 JZGepUhONaOMUoGNZNaDGw511RdPhYzPjj9rCsIx2qdsRO9/4tJ8ccpW2aUMYh8c
 nA6w8Hj8jCwco6aYYrDUDV9uRtURDrmyJgTJBNLU05e/L+MuJ3IZNlzHFWlsxIAE
 vhyTdmg/P04ClQyixCl67IH/66F/0smX9C+1761LrD7GTdfR92KPl5W6q+DPBg/x
 yf+s2p3+f7ItV5XobKOrbf3w0xazeDb5o/EK8BufMx9vSe9bpzJ0gOf0CmNXEpyZ
 owAhbh6wXX1YwPcyA9LHv6gthyJwc/3fLu49ggMZP2rU01ccKOYn9H0cr7C8NVmy
 wEpJR0lp5aSw2oRkPkxB6sFmUohcpr8/OXGGJuvCXkYsUY1BEup4lewvbIWK4WoE
 c84kbbaHsjgFhe3IRlQw3G4KLYQT3jRtF7fH+gPx556BcI6K+lg=
 =mcZR
 -----END PGP SIGNATURE-----

Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
 "Lots of platform specific updates for Qualcomm SoCs, including a new
  TEE subsystem driver for the Qualcomm QTEE firmware interface.

  Added support for the Apple A11 SoC in drivers that are shared with
  the M1/M2 series, among more updates for those.

  Smaller platform specific driver updates for Renesas, ASpeed,
  Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
  SoCs.

  Driver updates in the cache controller, memory controller and reset
  controller subsystems.

  SCMI firmware updates to add more features and improve robustness.
  This includes support for having multiple SCMI providers in a single
  system.

  TEE subsystem support for protected DMA-bufs, allowing hardware to
  access memory areas that managed by the kernel but remain inaccessible
  from the CPU in EL1/EL0"

* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
  soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
  soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
  soc: fsl: qe: Change GPIO driver to a proper platform driver
  tee: fix register_shm_helper()
  pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
  dt-bindings: spmi: Add Apple A11 and T2 compatible
  serial: qcom-geni: Load UART qup Firmware from linux side
  spi: geni-qcom: Load spi qup Firmware from linux side
  i2c: qcom-geni: Load i2c qup Firmware from linux side
  soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
  soc: qcom: geni-se: Cleanup register defines and update copyright
  dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
  Documentation: tee: Add Qualcomm TEE driver
  tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
  tee: qcom: add primordial object
  tee: add Qualcomm TEE driver
  tee: increase TEE_MAX_ARG_SIZE to 4096
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
  tee: add close_context to TEE driver operation
  ...
 2025-10-01 17:32:51 -07:00
Arnd Bergmann
17752efeca Allwinner Device Tree changes for 6.18 
This tag contains two DT binding header changes that are shared with
 the clk tree.
 
 In this cycle we gained support for the MCU PRCM clock and reset
 controller on the A523/A527/T527 family of SoCs, the NPU which is a
 Vivante GC9000 IP block, and the NPU clock that was missing. The other
 PRCM clock controller gained default bus clock rate settings. These
 were not configured in the upstream U-boot bootloader, leading to them
 running at slower rates. The assigned rates are from the user manual.
 
 There is also a new board, the NetCube Systems Nagami SoM and two of
 its carrier boards.
 
 The A523 family development boards now have their internal RTC clocks
 configured correctly, so that the RTC does not drift wildly. The missing
 functions for the AXP717 on these boards are added. Missing reset GPIOs
 and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its
 LEDs described and usable.
 
 An overlay for the Orange Pi Zero interface (addon) board was added.
 This can be used with the Orange Pi Zero and Zero Plus 2. Default audio
 routing for these two boards (to be used with the addon) were added to
 complement the overlay.
 -----BEGIN PGP SIGNATURE-----
 
 iQJCBAABCgAsFiEE2nN1m/hhnkhOWjtHOJpUIZwPJDAFAmjK7T8OHHdlbnNAY3Np
 ZS5vcmcACgkQOJpUIZwPJDAs/A//dN+3oLNSH1Ua72LdQgOBdmW9V5NmTXQNZUob
 pKrWnLN5ouZ8bID6o7uQWPngDWGSD0YnDTnsvWWNKS+HPk+JHFDClE1L3+/hLqsQ
 aXYMr0YdwS0HaiIm3/wCvIH45CIUgPTWnX6uVE9yxsJ8ERwEhO2n08oAcl5wB+x8
 ry43T62Xf2u5RpIoxPfKvilMWXewg09LFOzBw9Bp/O0jE5sBYUEDzne5KTtCDg6y
 /g7n3oD5025v5F6xRWE4NkAXQavayNjPLehXjwxg+WX4OcitRXO3JW3CEv3OvOpQ
 selj3ueY/PEH6DJxRCHYZeIE63bwH1sMLl6Qj/IWnajO1dHNhADCvCswCGtBU/R+
 bJJBaCbjqwYfJ1/8L3Sv6/zwqptl2rNw5aHOfR0AloaIxIqYVWy2LARkI5ba3Ke8
 oq+BAlXNkK3MtOGVXGumqoZzOzQEHc0on/WkUMch652zNlRwzviBS6hzZkkreTSH
 Vk6+Ioy3xbReEq/CnozjUFEOtqiT9jwMFFEBlgpZBcQY/tHTvyrduRKfQWEK9I0f
 WZwAskmJ56euhr0TZOeA5OfsN/lIISNm8z4wtXCZr9wmAm39xSiFkIIpT/YECUtJ
 1wOT0ZbqH7Dcwem9HjL1rlGRPPzdEHNdmFDplQ0mQWSZI9lSpkVq7z7PgNlj41Y4
 /aM1/t0=
 =3psf
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjTAHQACgkQmmx57+YA
 GNlbBg/+J2hd4556leePHdJFGU043Dm/OB/e3GRyNBGt0z4ynWyG8+NcJpiRKeGa
 Mx5kUGJtSPT9jdXNvdw5cm2RUEoJC/wG8aRnYq04V/sg2L82+MuzrYKHf7NXyWWK
 wjTr6kULZCfLho/MIg1ejgGGEf7XBaH3bNm0gLwr51j/22JijAHnrxWR5xSE29TX
 zLT09eLrgrXmfE7e2DX4CUfuqEBKHzHhYKBLDz/TzHgqXy/1R9BL9C30PhHmawyO
 zOr8a/mmwNGQF54NCikTg8JMFowi3LJlcGnVrxdSQoPYYMKxo6tOgKfh5Dd+VUuM
 QVRiceadcOAsFrlOYukiopw5rEkhvhjK8U+/xMXC0p/0VZXTS4VrbCYSSouV/Q60
 KtPpBLlMhXXQfPd4AkGeYictK+BwFFKVs4ZIMGJQgMIHeu7SREYrg4cQSYz2aylu
 PdPl1Jij37ZPFE8Y9aa9mwjGMgtl+5/oHUBbEnhtqe42d2ImAGPoFXfbgV3i1vDv
 ioWRrT4ieQ9L88oz3yZC/+f5/1ScKiu1XtLENW7OABiMy9mDALxIpvH+w0u0mQzM
 5rE4Juw/6TA6d2kw2PI6UoQ6+kF1I8pZ6xXtlJohwT2z1/a7qc/xnPokulFujr7P
 OEJe4MG16AXCiE4F5jL0DkoWIdSLB+6LJW81UDJ3Z+tb6sp4VoY=
 =7iP3
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt

Allwinner Device Tree changes for 6.18

This tag contains two DT binding header changes that are shared with
the clk tree.

In this cycle we gained support for the MCU PRCM clock and reset
controller on the A523/A527/T527 family of SoCs, the NPU which is a
Vivante GC9000 IP block, and the NPU clock that was missing. The other
PRCM clock controller gained default bus clock rate settings. These
were not configured in the upstream U-boot bootloader, leading to them
running at slower rates. The assigned rates are from the user manual.

There is also a new board, the NetCube Systems Nagami SoM and two of
its carrier boards.

The A523 family development boards now have their internal RTC clocks
configured correctly, so that the RTC does not drift wildly. The missing
functions for the AXP717 on these boards are added. Missing reset GPIOs
and delays for Ethernet PHYs are added. Last, the Cubie A5E now has its
LEDs described and usable.

An overlay for the Orange Pi Zero interface (addon) board was added.
This can be used with the Orange Pi Zero and Zero Plus 2. Default audio
routing for these two boards (to be used with the addon) were added to
complement the overlay.

* tag 'sunxi-dt-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: sun55i: Complete AXP717A sub-functions
  arm64: dts: allwinner: t527: orangepi-4a: hook up external 32k crystal
  arm64: dts: allwinner: t527: avaota-a1: hook up external 32k crystal
  arm64: dts: allwinner: a527: cubie-a5e: Drop external 32.768 KHz crystal
  arm64: dts: sun55i: a523: Assign standard clock rates to PRCM bus clocks
  ARM: dts: sunxi: add support for NetCube Systems Nagami Keypad Carrier
  ARM: dts: sunxi: add support for NetCube Systems Nagami Basic Carrier
  ARM: dts: sunxi: add support for NetCube Systems Nagami SoM
  riscv: dts: allwinner: d1s-t113: Add pinctrl's required by NetCube Systems Nagami SoM
  dt-bindings: arm: sunxi: Add NetCube Systems Nagami SoM and carrier board bindings
  ARM: dts: allwinner: Add Orange Pi Zero Interface Board overlay
  ARM: dts: allwinner: orangepi-zero-plus2: Add default audio routing
  ARM: dts: allwinner: orangepi-zero: Add default audio routing
  arm64: dts: allwinner: a523: Add NPU device node
  arm64: dts: allwinner: a523: Add MCU PRCM CCU node
  dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller
  dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock
  arm64: dts: allwinner: t527: avaota-a1: Add ethernet PHY reset setting
  arm64: dts: allwinner: a527: cubie-a5e: Add ethernet PHY reset setting
  arm64: dts: allwinner: a527: cubie-a5e: Add LEDs

Link: https://lore.kernel.org/r/aMrtuZg8HlR--TAt@wens.tw
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2025-09-23 22:17:56 +02:00
Ryan Chen
8ea304cff0
dt-bindings: clock: ast2700: modify soc0/1 clock define 
-add SOC0_CLK_AHBMUX:
add SOC0_CLK_AHBMUX for ahb clock source divide.
mpll->
      ahb_mux -> div_table -> clk_ahb
hpll->

-new add clock:
 SOC0_CLK_MPHYSRC: UFS MPHY clock source.
 SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source.
 SOC1_CLK_I3C: I3C clock source.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-09-21 13:14:04 -07:00
Yao Zi
793e6b7480
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible 
Document the clock controller shipped in Loongson-2K0300 SoC, which
generates various clock signals for SoC peripherals. Differing from
previous generations of SoCs, LS2K0300 requires a 120MHz external clock
input.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Yanteng Si <siyanteng@cqsoftware.com.cn>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-09-21 12:48:30 -07:00
Gabriel Fernandez
49f6c8b74d
dt-bindings: stm32: add STM32MP21 clocks and reset bindings 
Adds clock and reset binding entries for STM32MP21 SoC family.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-09-21 10:31:55 -07:00
Laura Nao
dd240e95f1
dt-bindings: clock: mediatek: Describe MT8196 clock controllers 
Introduce binding documentation for system clocks, functional clocks,
and PEXTP0/1 and UFS reset controllers on MediaTek MT8196.

This binding also includes a handle to the hardware voter, a
fixed-function MCU designed to aggregate votes from the application
processor and other remote processors to manage clocks and power
domains.

The HWV on MT8196/MT6991 is incomplete and requires software to manually
enable power supplies, parent clocks, and FENC, as well as write to both
the HWV MMIO and the controller registers.
Because of these constraints, the HWV cannot be modeled using generic
clock, power domain, or interconnect APIs. Instead, a custom phandle is
exceptionally used to provide direct, syscon-like register access to
drivers.

Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-09-21 09:35:59 -07:00
AngeloGioacchino Del Regno
64e7df08ed
dt-bindings: clock: mt7622: Add AFE_MRGIF clock 
Add the missing AFE Merge Interface clock to MT7622 to make use of
it in the audio subsystem.

While at it, also remove the useless CLK_AUDIO_NR_CLK definition.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-09-21 09:31:43 -07:00
Troy Mitchell
8be1f29904
dt-bindings: clock: spacemit: introduce i2s pre-clock to fix i2s clock 
Previously, the K1 clock driver did not include the parent clocks of
the I2S sysclk.

Introduce pre-clock to fix I2S clock.

Otherwise, the I2S clock may not work as expected.

This patch adds their definitions to allow proper registration
in the driver and usage in the device tree.

Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-09-19 22:54:40 -07:00
Arnd Bergmann
431ab7953c dt-bindings: Changes for v6.18-rc1 
Support for the Tegra264 generation of I2C is documented as well as some
 older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices.
 
 Contained are also some additions to existing bindings for Tegra114 and
 a fix for the power supply feeding VI/CSI.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmjGXQgACgkQ3SOs138+
 s6GLdBAApTnTZi8zBPYkQF2/j2Ua/qkH93E1Oos9Ng8PgP0n/ObS2I/qqLABsnur
 Q7EDesxKsDMI9VsLEazl2Pp0HCIPoqCRnlSWVkCp+G3JJ+RMeP+fFtEycTqZiiu6
 eIx9iQbAujXCdsIzYCx6cq21yyWoBnqTD/pkB7jqA1zpQazgnCHxjBJbCfC+wecY
 6B/ygsr6kaKJwH2ISPBGm7tVuunQZR3ZJEWfo//LVqPcG26xEYmyrvvE7k3UvGIP
 Njntp1x4trFTf6WcGalNyvcVn2dQWxc54gBQbi5oL4TfBfEO3Eb+tRcaIQa4zGyu
 RKTn3ZwvO9AnqBQx6Jnwyh9lu3LJPIp/BaNkztz9JXTPl64wo2OQ4nvqzwvCr8ws
 fvrOFfgolKBarxjupfiKFITcB1pAgtN0WeHg64pd+D7JxJ4T6A3818VswQLsltrO
 1JyPYVLvzsaHjOPmLckXiv42Y3FX7um6x0nu8ZgNEEWCIpbedc97gR+cFv7TkFue
 MENuesWqyGZ+5iI2zXDe/V6hQAcHAZvJgxEvnJ0YDbcK07hKlEKyen91Q6OgIG5D
 lOfj3M0IxnFjKgKnChjVfGAY8rgq0Dt04hWdpsR8G9cmle7tWvSQfTRoDrCbf/Nv
 VP2mB+A3D9PNZHO5ooqIAXCUIbmRnAVmrOUHUC0EFWYa06ZBHBM=
 =w8Ms
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIFn0ACgkQmmx57+YA
 GNlyDA/9H3YR2fM91GmzvLLJMsmb19g/NKlg7NS0DkCtmd6k41xK7Rs0IZOjZbqi
 rwI09Ns55B1TP1YNHzLEE00FOo5VXW8LLxjaGqi9IKHZyhlArXigo6SC7Gtzw343
 S/plUjZRXJh11z0KHs+BSuimmGrmBh7esd1pRKj5SRE3GmISY0WzC0OUXp2mcVnM
 ZqXA1VgnNcDiAQ1IcTK3s2cvGmllKA1bOgXM1SxJiiFyvzcNpadpFXypla4YWUNa
 oMh9Ey/H5gQ6SZ/ije5b85UgAN/G09O3LoPaVeP3KzerPGhjo//la0/YglMdmT0m
 3IU0SChnlRth+xgKME3Gg7cCyaA5I5o91imtr4XdQVo8AZoJa5XrII3RgzGG5obb
 48Qe801koOTxQHfmOQ1GRO6+L4PZLQrNRQPsTYHdV6vpRjmoU9h4foox7ELpKT8s
 7TWNhsfkQu+jkB99iN0F1zQmIRJGAhovOAG6RRD+W3M5tEUonH/7e0cBJBu55vUk
 eQMWxs04aIuxHukZ45WgjPcGnOTPBFsDqARLR5t3jYgC8vaOCkGZNaPLLbIyOEJB
 1FhuQIJwhwHgVCS4ejDa6vt57WXyIXq7YNORBnabaHrJrsdrJ4fEAZo33i2mKrl1
 M32HOMB1YbfP5Mf5KNWRs6g5wn9LOqzbSEBGh52y3mYfDvWgHrw=
 =TNku
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt

dt-bindings: Changes for v6.18-rc1

Support for the Tegra264 generation of I2C is documented as well as some
older Tegra devices, such as the Xiaomi Mi Pad and the ASUS 101 devices.

Contained are also some additions to existing bindings for Tegra114 and
a fix for the power supply feeding VI/CSI.

* tag 'tegra-for-6.18-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: arm: tegra: Add ASUS TF101G and SL101
  dt-bindings: reset: Add Tegra114 CAR header
  dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
  dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
  dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
  dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C

Link: https://lore.kernel.org/r/20250914063927.89981-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2025-09-15 15:37:01 +02:00
Arnd Bergmann
a3ef7cad8b Qualcomm Arm64 DeviceTree updates for v6.18 
Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
 7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
 Lemans EVK.
 
 The SDM845 Cheza development boards are removed, as they are not longer
 in use.
 
 For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
 buses are added and the internal GE PHY.
 
 IPQ5424 gets CPU frequency scaling and a missing UART.
 
 The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
 name. The IoT memory map introduced and made the default, GDSP FastRPC
 and GPR nodes are added.
 
 Touch keys are enabled on the BQ Aquaris X5 Plus.
 
 On QCM2290 the video accelerator is enabled, so is HS timing modes for
 eMMC.
 
 The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
 PCIe controller is introduced.
 
 On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
 eMMC support and generic packer router (GPR).
 
 On the Monaco Ride board, the eMMC controller is enabled.
 
 On QRB220 RB1, the venus video accelerator is enabled.
 
 For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
 LPASS, and USB offload support is added, the codecs and sound card is
 then described on the QCM6490 IDP. The MDSS core reset is introduced, to
 clear bootloader configuration on SC7280-based devices.
 On Fairphone5, USB audio offload is added.
 
 AudioReach support on SC7280 (QCS6490) is introduced and used to
 enable sound on the RB3Gen2 board.
 
 The video clock controller is added to SC8180X.
 
 On SC8280XP the GPI DMA controllers are described and enabled.
 
 Display and GPU is enabled for the Fairphone 3 and charging is enabled
 on the Google Pixel 3a.
 
 The routing for the second USB connector on the Lenovo Yoga C630 is
 described.
 
 On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
 encoder/decoder (venus).
 
 On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
 introduced and on Fairphone4 the USB audio offload support is enabled.
 
 On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
 functionality.
 
 On SM8650 ACD levels are added for the GPU.
 
 Camera and video clock controllers power-domains are updated on SM8450,
 SM8550, and SM8650, now that support for multiple power-domains is
 accepted.
 
 SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.
 
 The DWC3 glue and core nodes are flattened on a number of platforms.
 
 USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
 variety of platforms, now that the QMP PHY driver supports this.
 
 Platform specific RPMh PD constants are replaced with generic constants
 wherever possible.
 
 On X Elite the PM8010 is disabled by default, removing boot splats
 on a variety of boards without this PMIC, the video clock controller is
 added.
 
 For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
 marked as valid for the external DisplayPorts. The fingerprint reader
 found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
 The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.
 
 GPU support is added for the X Plus SoC.
 -----BEGIN PGP SIGNATURE-----
 
 iQJJBAABCAAzFiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAmjDXKwVHGFuZGVyc3Nv
 bkBrZXJuZWwub3JnAAoJEAsfOT8Nma3FLkkQALtHsCR/bDdGYDywR1STfQsajGk1
 tpS1zEC95wNrWoKfJoTywgCPmuPrDswgmnCbiVywreOoe9eqpVB/2xs8g6d7E/OW
 XtpUteBPA1KZ1LA/Flh/osB8ELIzenWRm2oa/GIcGFqB5WdVN6aysQA4cmryy73V
 c4girsq8DnQGobiMoyQBL/fkoI9ncWqXzPCE+9bu4hCkkF20bgPb95hsq+vrUe3y
 rIr9NV6UChjJ+4OidoiDLGcDKTtIjDmcvjd9pqFs3ReFgI8zTlFNiXhoudFULX3R
 dNECrRIA4v2RWe72AMj8zwokYo3Woc6j4UiiZkz61JELNM4bHg20zKvhUqnkbikg
 vE3fFQpncsAbBMb5iMBFdMXw6BEQpP/K360y0pHyy+5otDrYcNCno1tvSdSp0+sv
 nkpFf+RiP4TiCW6ARioHO3tQQb50PwFu+IkustgXfiEYZNN6okyaHTairZH7DOZF
 auDGXgcCS9AuQF7N1+YuvbB7p+vmGIm4tzF+LCfeRlxc2QPQ9uMy6d1qIpHfAF+X
 fm+GDmGv5XAfir9bS56CkruW33SQ9fl7XCdKbyh/4L7Rj0x8cGjKEDyuQ5W8raPI
 iB72LSRDxPaq6NZvQSXWoOrRQ5O51AAkwRa7QkoPAbO6KancMIb98VH7EoHrxYNC
 JrWbuLEU2SQ+gz9O
 =CEIF
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjIFAAACgkQmmx57+YA
 GNkxIg/7BwEzoj05zhu2fF6Bbw5slscr3hrKjdruKihS1/Z2ZPsgJDAKwL329L7n
 VQ3gAzIG6kP+KeBFGGsC3t0FZHf26Lk1UzsLbJvn8ExXY32Lfars8WdUqMyctS0n
 X8p0e73r5qM1qqlKg0ULi0wKOlSA9T8ySSUsNYKp6zoThqJmx0t4h9tYzwMllTHR
 j+2ImB2eND2mugsaeo/Yzv9KgrnTzjHFmQ03arB8n/9BFW4e/gRxeXwtd8dSY/Jj
 4C/SyVy/1OZddJhBavYtSY8NBFrdvG7S38KWe5yKW3W4/+i6A0BU7PUs13k/fYAy
 tHIxDZisbausmm+XZ1hVrkyNmgzsqdCjIS0htuBPk9pzHYX/iBLwJTYH4RP0SRhE
 PTiSiV9TtIvDL/wnmuYOhG+hhxrieiZJqFbEJsj7fP4wMQZjkTSphBkFpB8tXnkD
 ottgVtzEZ6o5tvmIQ779I1xbVZAqQnp6osde6yrBlgTk3vhD+D5Pa6GfxUDuzyx9
 XJXtFxbPt16Gu+x7uG6Qn0+X8EVElvtmCDCl0fct91ki5H7XTNWhOBtkqssjB2Pe
 7PVX83ncOfMWIOpEGeUIYWXWQAnfF/KvLtrpd3DZUBkamKMv9+nrI//2FaRxbVaM
 cDRfEcbhMZQnBrPd3mOcoy3hWNn3rWbqVdS+RtS8RsD0SaTRVTA=
 =cf7V
 -----END PGP SIGNATURE-----

Merge tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm Arm64 DeviceTree updates for v6.18

Add support for Lenovo Thinkbook 16, Dell Inspiron 7441, Dell Latitude
7455, Samsung Galaxy S20, Billion Capture+, the Monaco EVK and the
Lemans EVK.

The SDM845 Cheza development boards are removed, as they are not longer
in use.

For IPQ5018 crypto, tsens, rng, SPI NAND support is dded, the two MDIO
buses are added and the internal GE PHY.

IPQ5424 gets CPU frequency scaling and a missing UART.

The SA8775P SoC is remaned Lemans, to reduce confusion about the chip
name. The IoT memory map introduced and made the default, GDSP FastRPC
and GPR nodes are added.

Touch keys are enabled on the BQ Aquaris X5 Plus.

On QCM2290 the video accelerator is enabled, so is HS timing modes for
eMMC.

The QCS615 platform is renamed SM6150. CPU frequency scaling and the WiFi
PCIe controller is introduced.

On Monaco (QCS8300) scaling of L3 and DDR bandwidth is introduced. So is
eMMC support and generic packer router (GPR).

On the Monaco Ride board, the eMMC controller is enabled.

On QRB220 RB1, the venus video accelerator is enabled.

For SC7280 the first PCIe controller and PHY is introduced. SoundWire,
LPASS, and USB offload support is added, the codecs and sound card is
then described on the QCM6490 IDP. The MDSS core reset is introduced, to
clear bootloader configuration on SC7280-based devices.
On Fairphone5, USB audio offload is added.

AudioReach support on SC7280 (QCS6490) is introduced and used to
enable sound on the RB3Gen2 board.

The video clock controller is added to SC8180X.

On SC8280XP the GPI DMA controllers are described and enabled.

Display and GPU is enabled for the Fairphone 3 and charging is enabled
on the Google Pixel 3a.

The routing for the second USB connector on the Lenovo Yoga C630 is
described.

On SM6150 ADSP and CDSP FastRPC is introduced, as is the video
encoder/decoder (venus).

On SM6350 RPMh statistics is enabled, the USB audio offload DAI is
introduced and on Fairphone4 the USB audio offload support is enabled.

On SM8450 QRD the PMIC GLINK is described, to add USB Type-C and battery
functionality.

On SM8650 ACD levels are added for the GPU.

Camera and video clock controllers power-domains are updated on SM8450,
SM8550, and SM8650, now that support for multiple power-domains is
accepted.

SM8750 gains bwmon support for dynamic bus scaling, and PCIe nodes.

The DWC3 glue and core nodes are flattened on a number of platforms.

USB Type-C DisplayPort support is extended to 4 lanes (from 2) on a
variety of platforms, now that the QMP PHY driver supports this.

Platform specific RPMh PD constants are replaced with generic constants
wherever possible.

On X Elite the PM8010 is disabled by default, removing boot splats
on a variety of boards without this PMIC, the video clock controller is
added.

For the X Elite and X Plus CRDs, and the Lenovo Thinkpad T14s, HBR3 is
marked as valid for the external DisplayPorts. The fingerprint reader
found on the CRDs are enabled. The PCIe x8 slot on the QCP is enabled.
The two Microsoft Surface Laptop 7 gains WiFi and Bluetooth support.

GPU support is added for the X Plus SoC.

* tag 'qcom-arm64-for-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits)
  arm64: dts: qcom: x1e80100: Update GPU OPP table
  arm64: dts: qcom: sm8650: Drop redundant status from PMK8550 RTC
  arm64: dts: qcom: add initial support for Samsung Galaxy S20
  dt-bindings: arm: qcom: document x1q board binding
  arm64: dts: qcom: sm8250-samsung-r8q: Move common parts to dtsi
  arm64: dts: qcom: lemans-evk: Add sound card
  arm64: dts: qcom: lemans: Add gpr node
  arm64: dts: qcom: x1e78100-t14s-oled: Add eDP panel
  arm64: dts: qcom: qcs615-ride: enable venus node to initialize video codec
  arm64: dts: qcom: sm6150: add venus node to devicetree
  arm64: dts: qcom: x1e80100-romulus: Add WCN7850 Wi-Fi/BT
  arm64: dts: qcom: qrb2210-rb1: Enable Venus
  arm64: dts: qcom: qcm2290: Add Venus video node
  arm64: dts: qcom: monaco-evk: Add sound card
  arm64: dts: qcom: qcs8300: Add gpr node
  arm64: dts: qcom: qcs8300: Add Monaco EVK board
  dt-bindings: arm: qcom: Add Monaco EVK support
  arm64: dts: qcom: qcm6490-idp: Add sound card
  arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and WCD9370 headset codec
  arm64: dts: qcom: qcs6490-rb3gen2: Add sound card
  ...

Link: https://lore.kernel.org/r/20250911233600.3033675-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2025-09-15 15:26:24 +02:00
Chen-Yu Tsai
0f610e650d dt-bindings: clock: sun55i-a523-ccu: Add A523 MCU CCU clock controller 
There are four clock controllers in the A523 SoC. The existing binding
already covers two of them that are critical for basic operation. The
remaining ones are the MCU clock controller and CPU PLL clock
controller.

Add a description for the MCU CCU. This unit controls and provides
clocks to the MCU (RISC-V) subsystem and peripherals meant to operate
under low power conditions.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-3-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2025-09-13 13:49:09 +08:00
Chen-Yu Tsai
e9671ddd82 dt-bindings: clock: sun55i-a523-ccu: Add missing NPU module clock 
The main clock controller on the A523/T527 has the NPU's module clock.
It was missing from the original submission, likely because that was
based on the A523 user manual; the A523 is marketed without the NPU.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250911174710.3149589-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2025-09-13 13:49:08 +08:00
Geert Uytterhoeven
9bb55594ef Renesas RZ/G3E USB3.0 Core Clock DT Binding Definitions 
USB3.0 core clock DT binding definitions for the Renesas RZ/G3E
 (R9A09G047) SoC, shared by driver and DT source files.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYKAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCaMMSmgAKCRCKwlD9ZEnx
 cJB8AP4nPlMcqXBlXtMQuVHpghrH5UxKlTYeXlSWUJXhOf71hgEA9vc/PCVU+Vez
 QEMiNHrOINDlfXhIN8QAOvQdOtF/gAo=
 =Oxy/
 -----END PGP SIGNATURE-----

Merge tag 'renesas-r9a09g047-dt-binding-defs-tag4' into renesas-clk-for-v6.18

Renesas RZ/G3E USB3.0 Core Clock DT Binding Definitions

USB3.0 core clock DT binding definitions for the Renesas RZ/G3E
(R9A09G047) SoC, shared by driver and DT source files.
 2025-09-12 09:53:27 +02:00
Biju Das
a24cd110e6 dt-bindings: clock: renesas,r9a09g047-cpg: Add USB3.0 core clocks 
Add definitions for USB3.0 core clocks in the R9A09G047 CPG DT bindings
header file.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20250909180803.140939-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-11 20:17:28 +02:00
Svyatoslav Ryhel
fc02f529a8 dt-bindings: clock: tegra30: Add IDs for CSI pad clocks 
Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
 2025-09-11 18:03:10 +02:00
Denzeel Oliva
43bd82eb33 dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units 
Add clock management unit bindings for PERIC0 and PERIC1 blocks
which provide clocks for USI, I2C and UART peripherals.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-09-07 11:10:55 +02:00
Denzeel Oliva
eb9bc16277 dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block 
Add the missing LHS_ACEL clock ID for the HSI0 block. This clock is
required for proper USB operation, as without it, USB connections fail
with errors like device descriptor read timeouts and address response
issues.

Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250831-usb-v2-1-00b9c0559733@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-09-04 15:47:40 +02:00
Bjorn Andersson
154691e7c9 Merge branch '20250903-msm8937-v9-1-a097c91c5801@mainlining.org' into clk-for-6.18 
Merge the MSM8937 global clock controller binding through a topic branch
to allow merging the constants into the DeviceTree branch as well.
 2025-09-04 08:38:00 -05:00
Barnabás Czémán
4d32c1f66a dt-bindings: clock: qcom: Add MSM8937 Global Clock Controller 
Add device tree bindings for the global clock controller on Qualcomm
MSM8937 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20250903-msm8937-v9-1-a097c91c5801@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-09-04 08:37:53 -05:00
Lad Prabhakar
0dcfb6fcdd dt-bindings: clock: renesas,r9a09g077/87: Add Ethernet clock IDs 
Add clock definitions for Ethernet (ETCLK A-E) to both R9A09G077 and
R9A09G087 SoCs. These definitions are required for describing Ethernet
devices in DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250904071954.3176806-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-09-04 11:26:06 +02:00
Taniya Das
ee2d967030 dt-bindings: clock: qcom: document the Glymur Global Clock Controller 
Add device tree bindings for global clock controller on Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-6-01b8c8681bcd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-09-03 18:15:43 -05:00
Taniya Das
ae5b84788e dt-bindings: clock: qcom: Document the Glymur SoC TCSR Clock Controller 
The Glymur SoC TCSR block provides CLKREF clocks for EDP, PCIe and USB.
Add this to the TCSR clock controller binding together with identifiers
for the clocks.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250825-glymur-clock-controller-v5-v5-2-01b8c8681bcd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-09-03 18:14:44 -05:00
Taniya Das
781c118c3e dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC 
Add the device tree bindings for the display clock controller which are
required on Qualcomm Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250829-glymur-disp-clock-controllers-v1-1-0ce6fabd837c@oss.qualcomm.com
[bjorn: Dropped unnecessary include in DT example]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-09-03 17:13:16 -05:00
Andrea della Porta
07bab7b81d dt-bindings: clock: rp1: Add missing MIPI DSI defines 
Declare the positional index for the RP1 MIPI clocks.

Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/c20066500908db854aa4816b40e956296bab526a.1750714412.git.andrea.porta@suse.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
 2025-09-03 13:47:58 -07:00
WeiHao Li
4a76a0a889 dt-bindings: clock: rk3368: Add SCLK_MIPIDSI_24M 
Add a clock id for mipi dsi reference clock, mipi dsi node used it.

Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250831104855.45883-4-cn.liweihao@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
 2025-09-03 14:17:44 +02:00
Krzysztof Kozlowski
aac0892cae Merge branch 'for-v6.18/dt-bindings-clk' into next/clk 2025-08-31 15:22:23 +02:00
Hakyeong Kim
91f98de423 dt-bindings: clock: Add ARTPEC-8 clock controller 
Add dt-schema for Axis ARTPEC-8 SoC clock controller.

The Clock Management Unit (CMU) has a top-level block CMU_CMU
which generates clocks for other blocks.

Add device-tree binding definitions for following CMU blocks:
- CMU_CMU
- CMU_BUS
- CMU_CORE
- CMU_CPUCL
- CMU_FSYS
- CMU_IMEM
- CMU_PERI

Signed-off-by: Hakyeong Kim <hgkim05@coasia.com>
Signed-off-by: SeonGu Kang <ksk4725@coasia.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ravi Patel <ravi.patel@samsung.com>
Link: https://lore.kernel.org/r/20250825114436.46882-2-ravi.patel@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-08-31 15:22:10 +02:00
Denzeel Oliva
76f1e2ee54 dt-bindings: clock: exynos990: Extend clocks IDs 
Add missing clock definitions for DPU and CMUREF.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com>
Link: https://lore.kernel.org/r/20250830-fix-cmu-top-v5-4-7c62f608309e@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-08-31 12:54:05 +02:00
Troy Mitchell
7d50d9bf1c
dt-bindings: clock: spacemit: CLK_SSPA_I2S_BCLK for SSPA 
In order to use the virtual clock SSPAx_I2S_BCLK in the device tree and
register it in the driver, this patch introduces the macro definition.

Fixes: 1b72c59db0add ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Link: https://lore.kernel.org/r/20250811-k1-clk-i2s-v5-1-ebadd06e1e91@linux.spacemit.com
Signed-off-by: Yixun Lan <dlan@gentoo.org>
 2025-08-24 15:42:28 +08:00
Bjorn Andersson
9a834bfe4b Merge branch '20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-1-c5a8af040093@yandex.ru' into clk-for-6.18 
Merge the addition of a few missing clock defines for the SDM660 global
clock controller, in order to allow them to be used in the DeviceTree
branch as well.
 2025-08-23 20:39:28 -05:00
Nickolay Goppen
ab6d91d141 dt-bindings: clock: gcc-sdm660: Add LPASS/CDSP vote clocks/GDSCs 
Add defines for the missing clocks, which are required to power up the
related remote processors.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Nickolay Goppen <setotau@yandex.ru>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250815-gcc-sdm660-vote-clocks-and-gdscs-v1-1-c5a8af040093@yandex.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-23 20:39:21 -05:00
Inbaraj E
5576d80980 dt-bindings: clock: Add CAM_CSI clock macro for FSD 
CAM_CSI block has ACLK, PCLK and PLL clocks. PCLK id is already
assigned. To use PCLK and PLL clock in driver add id macro for CAM_CSI_PLL
and CAM_CSI_PCLK.

Signed-off-by: Inbaraj E <inbaraj.e@samsung.com>
Link: https://lore.kernel.org/r/20250814140943.22531-2-inbaraj.e@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2025-08-18 10:46:32 +02:00
Bjorn Andersson
e320c42bf6 Merge branch '20250811090954.2854440-2-quic_varada@quicinc.com' into HEAD 
Merge the IPQ5424 application subsystem clock binding, in order to get
access to the necessary clock constants for CPUfreq.
 2025-08-12 12:01:13 -05:00
Bjorn Andersson
ccdba33f5c Merge branch '20250811-sc7280-mdss-reset-v1-1-83ceff1d48de@oss.qualcomm.com' into clk-for-6.18 
Merge the addition of reset constants to the SC7280 display clock
controller binding through a topic branch to allow it to be included in
the DeviceTree branch as well.
 2025-08-12 09:58:37 -05:00
Bjorn Andersson
039a504cda dt-bindings: clock: dispcc-sc7280: Add display resets 
Like other platforms the sc7280 display clock controller provides a
couple of resets, add the defines to allow referring to them.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250811-sc7280-mdss-reset-v1-1-83ceff1d48de@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-12 09:58:29 -05:00
Sricharan Ramabadhran
c17ccefb61 dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller 
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
The RCG and PLL have a separate register space from the GCC.
Also the L3 cache has a separate pll and needs to be scaled along
with the CPU.

Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
[ Added interconnect related changes ]
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-08-11 10:05:20 -05:00
Lad Prabhakar
8a5a0294f4 dt-bindings: clock: renesas,r9a09g077/87: Add USB_CLK clock ID 
Add the USB clock (USB_CLK) definition for the Renesas RZ/T2H
(R9A09G077) and RZ/N2H (R9A09G087) SoCs.  USB_CLK is used as the
reference clock for USB PHY layer.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250804202643.3967484-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2025-08-11 15:47:03 +02:00
Linus Torvalds
2d945dde7f This is the usual collection of primarily clk driver updates. The big part of 
the diff is all the new Qualcomm clk drivers added for a few SoCs they're
 working on. The other two vendors with significant work this cycle are Renesas
 and Amlogic. Renesas adds a bunch of clks to existing drivers and supports some
 new SoCs while Amlogic is starting a significant refactoring to simplify their
 code.
 
 The core framework gained a pair of helpers to get the 'struct device' or
 'struct device_node' associated with a 'struct clk_hw'. Some associated KUnit
 tests were added for these simple helpers as well. Beyond that core change
 there are lots of little fixes throughout the clk drivers for the stuff we see
 every day, wrong clk driver data that affects tree topology or supported
 frequencies, etc. They're not found until the clks are actually used by some
 consumer device driver.
 
 New Drivers:
  - Global, display, gpu, video, camera, tcsr, and rpmh clock controller for the
    Qualcomm Milos SoC
  - Camera, display, GPU, and video clock controllers for Qualcomm QCS615
  - Video clock controller driver for Qualcomm SM6350
  - Camera clock controller driver for Qualcomm SC8180X
  - I3C clocks and resets on Renesas RZ/G3E
  - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
    Renesas RZ/V2H(P) and RZ/V2N
  - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
  - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
  - Ethernet clocks and resets on Renesas RZ/G3E
  - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
    (R9A09G087) SoCs
  - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
  - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
    RZ/V2N
 
 Updates:
  - Support atomic PWMs in the PWM clk driver
  - clk_hw_get_dev() and clk_hw_get_of_node() helpers
  - Replace round_rate() with determine_rate() in various clk drivers
  - Convert clk DT bindings to DT schema format for DT validation
  - Various clk driver cleanups and refactorings from static analysis tools and
    possibly real humans
  - A lot of little fixes here and there to things like clk tree topology,
    missing frequencies, flagging clks as critical, etc. The full details are in
    the commits and sub-tree merge logs
 -----BEGIN PGP SIGNATURE-----
 
 iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmiLljkUHHN3Ym95ZEBj
 aHJvbWl1bS5vcmcACgkQrQKIl8bklSVR1BAAm5hnFdYvNX/AYK+bNNbb/YkbveGr
 wxrZFjd/1QEZii7UBBOENLjvbrxT4N93TGuwuHOy+iz53X4mWg1BST0RENtmks9v
 rys7suEkDVA7KoDEbcvbUhLbLObEQvr3sxurl2mvq563y02hkJ+rt3kDqdCn/MFK
 fUfqZ79oPLaMULy3XwFyrEQEcxqQTX7i+j1atCB4TPmBSu3R5WMsCS+IVKPCuxCF
 qcan5hCXakv4gBE/jF9x/u28j0m9v16uB2O/7sH3uDzHo/FxShBmC53Bj2Mtaf2w
 lSKhEngCAMItU2LtruO2szpsmoy9EZTIqzELr5GJGXFDQDHiTzcigRtD5MCWjdG1
 aapgWs47Yslh0M+d8Im81hu1YaLGDuoY7QiOVMN/htn0nPEozU1farKJbD3/gj9U
 C6648EXYa/dqDBRRHeqLi4n1RK0Fzb15VvsanKn1nLy+cOvzNI4bpJjEJlUQjZMN
 8MzvzBgLNsydDQC5I8JAPPK2Fcdpk3KpchphZrXLZY8iRco5kvx1mRjh90Lvr8N8
 rmpUC6p1BdEIGhL+NAh7qCz9DOKfsaFr13tHpqD/PItzfHIyd7mss+7GSD6WCa/b
 MduE9172Uq0mY8ZnWe0vV7/+s9GE7oTsxdMC6oF5yTXRIpog7evkUqNyXhpNTxgS
 C2DLCDhaqpHI28c=
 =S+dB
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This is the usual collection of primarily clk driver updates.

  The big part of the diff is all the new Qualcomm clk drivers added for
  a few SoCs they're working on. The other two vendors with significant
  work this cycle are Renesas and Amlogic. Renesas adds a bunch of clks
  to existing drivers and supports some new SoCs while Amlogic is
  starting a significant refactoring to simplify their code.

  The core framework gained a pair of helpers to get the 'struct device'
  or 'struct device_node' associated with a 'struct clk_hw'. Some
  associated KUnit tests were added for these simple helpers as well.

  Beyond that core change there are lots of little fixes throughout the
  clk drivers for the stuff we see every day, wrong clk driver data that
  affects tree topology or supported frequencies, etc. They're not found
  until the clks are actually used by some consumer device driver.

  New Drivers:
   - Global, display, gpu, video, camera, tcsr, and rpmh clock
     controller for the Qualcomm Milos SoC
   - Camera, display, GPU, and video clock controllers for Qualcomm
     QCS615
   - Video clock controller driver for Qualcomm SM6350
   - Camera clock controller driver for Qualcomm SC8180X
   - I3C clocks and resets on Renesas RZ/G3E
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/V2H(P) and RZ/V2N
   - SPI (RSPI) clocks and resets on Renesas RZ/V2H(P)
   - SDHI and I2C clocks on Renesas RZ/T2H and RZ/N2H
   - Ethernet clocks and resets on Renesas RZ/G3E
   - Initial support for the Renesas RZ/T2H (R9A09G077) and RZ/N2H
     (R9A09G087) SoCs
   - Ethernet clocks and resets on Renesas RZ/V2H and RZ/V2N
   - Timer, I2C, watchdog, GPU, and USB2.0 clocks and resets on Renesas
     RZ/V2N

  Updates:
   - Support atomic PWMs in the PWM clk driver
   - clk_hw_get_dev() and clk_hw_get_of_node() helpers
   - Replace round_rate() with determine_rate() in various clk drivers
   - Convert clk DT bindings to DT schema format for DT validation
   - Various clk driver cleanups and refactorings from static analysis
     tools and possibly real humans
   - A lot of little fixes here and there to things like clk tree
     topology, missing frequencies, flagging clks as critical, etc"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (216 commits)
  clk: clocking-wizard: Fix the round rate handling for versal
  clk: Fix typos
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  clk: tegra: periph: Make tegra_clk_periph_ops static
  clk: tegra: periph: Fix error handling and resolve unsigned compare warning
  clk: imx: scu: convert from round_rate() to determine_rate()
  clk: imx: pllv4: convert from round_rate() to determine_rate()
  clk: imx: pllv3: convert from round_rate() to determine_rate()
  clk: imx: pllv2: convert from round_rate() to determine_rate()
  clk: imx: pll14xx: convert from round_rate() to determine_rate()
  clk: imx: pfd: convert from round_rate() to determine_rate()
  clk: imx: frac-pll: convert from round_rate() to determine_rate()
  clk: imx: fracn-gppll: convert from round_rate() to determine_rate()
  clk: imx: fixup-div: convert from round_rate() to determine_rate()
  clk: imx: cpu: convert from round_rate() to determine_rate()
  clk: imx: busy: convert from round_rate() to determine_rate()
  clk: imx: composite-93: remove round_rate() in favor of determine_rate()
  clk: imx: composite-8m: remove round_rate() in favor of determine_rate()
  clk: qcom: Remove redundant pm_runtime_mark_last_busy() calls
  clk: imx: Remove redundant pm_runtime_mark_last_busy() calls
  ...
 2025-07-31 13:36:27 -07:00
Stephen Boyd
64c21f253a
Merge branch 'clk-fixes' into clk-next 
Resolve conflicts with i.MX95 changes 88768d6f8c13 ("clk:
imx95-blk-ctl: Rename lvds and displaymix csr blk") in clk-imx
and aacc875a448d ("clk: imx: Fix an out-of-bounds access in
dispmix_csr_clk_dev_data") in clk-fixes.

* clk-fixes:
  clk: sunxi-ng: v3s: Fix TCON clock parents
  clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name
  clk: sunxi-ng: v3s: Fix CSI SCLK clock name
  dt-bindings: clock: mediatek: Add #reset-cells property for MT8188
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
  clk: scmi: Handle case where child clocks are initialized before their parents
  clk: sunxi-ng: a523: Mark MBUS clock as critical
 2025-07-31 09:10:06 -07:00
Linus Torvalds
8be4d31cb8 Networking changes for 6.17. 
Core & protocols
 ----------------
 
  - Wrap datapath globals into net_aligned_data, to avoid false sharing.
 
  - Preserve MSG_ZEROCOPY in forwarding (e.g. out of a container).
 
  - Add SO_INQ and SCM_INQ support to AF_UNIX.
 
  - Add SIOCINQ support to AF_VSOCK.
 
  - Add TCP_MAXSEG sockopt to MPTCP.
 
  - Add IPv6 force_forwarding sysctl to enable forwarding per interface.
 
  - Make TCP validation of whether packet fully fits in the receive
    window and the rcv_buf more strict. With increased use of HW
    aggregation a single "packet" can be multiple 100s of kB.
 
  - Add MSG_MORE flag to optimize large TCP transmissions via sockmap,
    improves latency up to 33% for sockmap users.
 
  - Convert TCP send queue handling from tasklet to BH workque.
 
  - Improve BPF iteration over TCP sockets to see each socket exactly once.
 
  - Remove obsolete and unused TCP RFC3517/RFC6675 loss recovery code.
 
  - Support enabling kernel threads for NAPI processing on per-NAPI
    instance basis rather than a whole device. Fully stop the kernel NAPI
    thread when threaded NAPI gets disabled. Previously thread would stick
    around until ifdown due to tricky synchronization.
 
  - Allow multicast routing to take effect on locally-generated packets.
 
  - Add output interface argument for End.X in segment routing.
 
  - MCTP: add support for gateway routing, improve bind() handling.
 
  - Don't require rtnl_lock when fetching an IPv6 neighbor over Netlink.
 
  - Add a new neighbor flag ("extern_valid"), which cedes refresh
    responsibilities to userspace. This is needed for EVPN multi-homing
    where a neighbor entry for a multi-homed host needs to be synced
    across all the VTEPs among which the host is multi-homed.
 
  - Support NUD_PERMANENT for proxy neighbor entries.
 
  - Add a new queuing discipline for IETF RFC9332 DualQ Coupled AQM.
 
  - Add sequence numbers to netconsole messages. Unregister netconsole's
    console when all net targets are removed. Code refactoring.
    Add a number of selftests.
 
  - Align IPSec inbound SA lookup to RFC 4301. Only SPI and protocol
    should be used for an inbound SA lookup.
 
  - Support inspecting ref_tracker state via DebugFS.
 
  - Don't force bonding advertisement frames tx to ~333 ms boundaries.
    Add broadcast_neighbor option to send ARP/ND on all bonded links.
 
  - Allow providing upcall pid for the 'execute' command in openvswitch.
 
  - Remove DCCP support from Netfilter's conntrack.
 
  - Disallow multiple packet duplications in the queuing layer.
 
  - Prevent use of deprecated iptables code on PREEMPT_RT.
 
 Driver API
 ----------
 
  - Support RSS and hashing configuration over ethtool Netlink.
 
  - Add dedicated ethtool callbacks for getting and setting hashing fields.
 
  - Add support for power budget evaluation strategy in PSE /
    Power-over-Ethernet. Generate Netlink events for overcurrent etc.
 
  - Support DPLL phase offset monitoring across all device inputs.
    Support providing clock reference and SYNC over separate DPLL
    inputs.
 
  - Support traffic classes in devlink rate API for bandwidth management.
 
  - Remove rtnl_lock dependency from UDP tunnel port configuration.
 
 Device drivers
 --------------
 
  - Add a new Broadcom driver for 800G Ethernet (bnge).
 
  - Add a standalone driver for Microchip ZL3073x DPLL.
 
  - Remove IBM's NETIUCV device driver.
 
  - Ethernet high-speed NICs:
    - Broadcom (bnxt):
     - support zero-copy Tx of DMABUF memory
     - take page size into account for page pool recycling rings
    - Intel (100G, ice, idpf):
      - idpf: XDP and AF_XDP support preparations
      - idpf: add flow steering
      - add link_down_events statistic
      - clean up the TSPLL code
      - preparations for live VM migration
    - nVidia/Mellanox:
     - support zero-copy Rx/Tx interfaces (DMABUF and io_uring)
     - optimize context memory usage for matchers
     - expose serial numbers in devlink info
     - support PCIe congestion metrics
    - Meta (fbnic):
      - add 25G, 50G, and 100G link modes to phylink
      - support dumping FW logs
    - Marvell/Cavium:
      - support for CN20K generation of the Octeon chips
    - Amazon:
      - add HW clock (without timestamping, just hypervisor time access)
 
  - Ethernet virtual:
    - VirtIO net:
      - support segmentation of UDP-tunnel-encapsulated packets
    - Google (gve):
      - support packet timestamping and clock synchronization
    - Microsoft vNIC:
      - add handler for device-originated servicing events
      - allow dynamic MSI-X vector allocation
      - support Tx bandwidth clamping
 
  - Ethernet NICs consumer, and embedded:
    - AMD:
      - amd-xgbe: hardware timestamping and PTP clock support
    - Broadcom integrated MACs (bcmgenet, bcmasp):
      - use napi_complete_done() return value to support NAPI polling
      - add support for re-starting auto-negotiation
    - Broadcom switches (b53):
      - support BCM5325 switches
      - add bcm63xx EPHY power control
    - Synopsys (stmmac):
      - lots of code refactoring and cleanups
    - TI:
      - icssg-prueth: read firmware-names from device tree
      - icssg: PRP offload support
    - Microchip:
      - lan78xx: convert to PHYLINK for improved PHY and MAC management
      - ksz: add KSZ8463 switch support
    - Intel:
      - support similar queue priority scheme in multi-queue and
        time-sensitive networking (taprio)
      - support packet pre-emption in both
    - RealTek (r8169):
      - enable EEE at 5Gbps on RTL8126
    - Airoha:
      - add PPPoE offload support
      - MDIO bus controller for Airoha AN7583
 
  - Ethernet PHYs:
    - support for the IPQ5018 internal GE PHY
    - micrel KSZ9477 switch-integrated PHYs:
      - add MDI/MDI-X control support
      - add RX error counters
      - add cable test support
      - add Signal Quality Indicator (SQI) reporting
    - dp83tg720: improve reset handling and reduce link recovery time
    - support bcm54811 (and its MII-Lite interface type)
    - air_en8811h: support resume/suspend
    - support PHY counters for QCA807x and QCA808x
    - support WoL for QCA807x
 
  - CAN drivers:
    - rcar_canfd: support for Transceiver Delay Compensation
    - kvaser: report FW versions via devlink dev info
 
  - WiFi:
    - extended regulatory info support (6 GHz)
    - add statistics and beacon monitor for Multi-Link Operation (MLO)
    - support S1G aggregation, improve S1G support
    - add Radio Measurement action fields
    - support per-radio RTS threshold
    - some work around how FIPS affects wifi, which was wrong (RC4 is used
      by TKIP, not only WEP)
    - improvements for unsolicited probe response handling
 
  - WiFi drivers:
    - RealTek (rtw88):
      - IBSS mode for SDIO devices
    - RealTek (rtw89):
      - BT coexistence for MLO/WiFi7
      - concurrent station + P2P support
      - support for USB devices RTL8851BU/RTL8852BU
    - Intel (iwlwifi):
      - use embedded PNVM in (to be released) FW images to fix
        compatibility issues
      - many cleanups (unused FW APIs, PCIe code, WoWLAN)
      - some FIPS interoperability
    - MediaTek (mt76):
      - firmware recovery improvements
      - more MLO work
    - Qualcomm/Atheros (ath12k):
      - fix scan on multi-radio devices
      - more EHT/Wi-Fi 7 features
      - encapsulation/decapsulation offload
    - Broadcom (brcm80211):
      - support SDIO 43751 device
 
  - Bluetooth:
    - hci_event: add support for handling LE BIG Sync Lost event
    - ISO: add socket option to report packet seqnum via CMSG
    - ISO: support SCM_TIMESTAMPING for ISO TS
 
  - Bluetooth drivers:
    - intel_pcie: support Function Level Reset
    - nxpuart: add support for 4M baudrate
    - nxpuart: implement powerup sequence, reset, FW dump, and FW loading
 
 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE6jPA+I1ugmIBA4hXMUZtbf5SIrsFAmiFgLgACgkQMUZtbf5S
 IrvafxAAnQRwYBoIG+piCILx6z5pRvBGHkmEQ4AQgSCFuq2eO3ubwMFIqEybfma1
 5+QFjUZAV3OgGgKRBS2KGWxtSzdiF+/JGV1VOIN67sX3Mm0a2QgjA4n5CgKL0FPr
 o6BEzjX5XwG1zvGcBNQ5BZ19xUUKjoZQgTtnea8sZ57Fsp5RtRgmYRqoewNvNk/n
 uImh0NFsDVb0UeOpSzC34VD9l1dJvLGdui4zJAjno/vpvmT1DkXjoK419J/r52SS
 X+5WgsfJ6DkjHqVN1tIhhK34yWqBOcwGFZJgEnWHMkFIl2FqRfFKMHyqtfLlVnLA
 mnIpSyz8Sq2AHtx0TlgZ3At/Ri8p5+yYJgHOXcDKyABa8y8Zf4wrycmr6cV9JLuL
 z54nLEVnJuvfDVDVJjsLYdJXyhMpZFq6+uAItdxKaw8Ugp/QqG4QtoRj+XIHz4ZW
 z6OohkCiCzTwEISFK+pSTxPS30eOxq43kCspcvuLiwCCStJBRkRb5GdZA4dm7LA+
 1Od4ADAkHjyrFtBqTyyC2scX8UJ33DlAIpAYyIeS6w9Cj9EXxtp1z33IAAAZ03MW
 jJwIaJuc8bK2fWKMmiG7ucIXjPo4t//KiWlpkwwqLhPbjZgfDAcxq1AC2TLoqHBL
 y4EOgKpHDCMAghSyiFIAn2JprGcEt8dp+11B0JRXIn4Pm/eYDH8=
 =lqbe
 -----END PGP SIGNATURE-----

Merge tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next

Pull networking updates from Jakub Kicinski:
 "Core & protocols:

   - Wrap datapath globals into net_aligned_data, to avoid false sharing

   - Preserve MSG_ZEROCOPY in forwarding (e.g. out of a container)

   - Add SO_INQ and SCM_INQ support to AF_UNIX

   - Add SIOCINQ support to AF_VSOCK

   - Add TCP_MAXSEG sockopt to MPTCP

   - Add IPv6 force_forwarding sysctl to enable forwarding per interface

   - Make TCP validation of whether packet fully fits in the receive
     window and the rcv_buf more strict. With increased use of HW
     aggregation a single "packet" can be multiple 100s of kB

   - Add MSG_MORE flag to optimize large TCP transmissions via sockmap,
     improves latency up to 33% for sockmap users

   - Convert TCP send queue handling from tasklet to BH workque

   - Improve BPF iteration over TCP sockets to see each socket exactly
     once

   - Remove obsolete and unused TCP RFC3517/RFC6675 loss recovery code

   - Support enabling kernel threads for NAPI processing on per-NAPI
     instance basis rather than a whole device. Fully stop the kernel
     NAPI thread when threaded NAPI gets disabled. Previously thread
     would stick around until ifdown due to tricky synchronization

   - Allow multicast routing to take effect on locally-generated packets

   - Add output interface argument for End.X in segment routing

   - MCTP: add support for gateway routing, improve bind() handling

   - Don't require rtnl_lock when fetching an IPv6 neighbor over Netlink

   - Add a new neighbor flag ("extern_valid"), which cedes refresh
     responsibilities to userspace. This is needed for EVPN multi-homing
     where a neighbor entry for a multi-homed host needs to be synced
     across all the VTEPs among which the host is multi-homed

   - Support NUD_PERMANENT for proxy neighbor entries

   - Add a new queuing discipline for IETF RFC9332 DualQ Coupled AQM

   - Add sequence numbers to netconsole messages. Unregister
     netconsole's console when all net targets are removed. Code
     refactoring. Add a number of selftests

   - Align IPSec inbound SA lookup to RFC 4301. Only SPI and protocol
     should be used for an inbound SA lookup

   - Support inspecting ref_tracker state via DebugFS

   - Don't force bonding advertisement frames tx to ~333 ms boundaries.
     Add broadcast_neighbor option to send ARP/ND on all bonded links

   - Allow providing upcall pid for the 'execute' command in openvswitch

   - Remove DCCP support from Netfilter's conntrack

   - Disallow multiple packet duplications in the queuing layer

   - Prevent use of deprecated iptables code on PREEMPT_RT

  Driver API:

   - Support RSS and hashing configuration over ethtool Netlink

   - Add dedicated ethtool callbacks for getting and setting hashing
     fields

   - Add support for power budget evaluation strategy in PSE /
     Power-over-Ethernet. Generate Netlink events for overcurrent etc

   - Support DPLL phase offset monitoring across all device inputs.
     Support providing clock reference and SYNC over separate DPLL
     inputs

   - Support traffic classes in devlink rate API for bandwidth
     management

   - Remove rtnl_lock dependency from UDP tunnel port configuration

  Device drivers:

   - Add a new Broadcom driver for 800G Ethernet (bnge)

   - Add a standalone driver for Microchip ZL3073x DPLL

   - Remove IBM's NETIUCV device driver

   - Ethernet high-speed NICs:
      - Broadcom (bnxt):
         - support zero-copy Tx of DMABUF memory
         - take page size into account for page pool recycling rings
      - Intel (100G, ice, idpf):
         - idpf: XDP and AF_XDP support preparations
         - idpf: add flow steering
         - add link_down_events statistic
         - clean up the TSPLL code
         - preparations for live VM migration
      - nVidia/Mellanox:
         - support zero-copy Rx/Tx interfaces (DMABUF and io_uring)
         - optimize context memory usage for matchers
         - expose serial numbers in devlink info
         - support PCIe congestion metrics
      - Meta (fbnic):
         - add 25G, 50G, and 100G link modes to phylink
         - support dumping FW logs
      - Marvell/Cavium:
         - support for CN20K generation of the Octeon chips
      - Amazon:
         - add HW clock (without timestamping, just hypervisor time access)

   - Ethernet virtual:
      - VirtIO net:
         - support segmentation of UDP-tunnel-encapsulated packets
      - Google (gve):
         - support packet timestamping and clock synchronization
      - Microsoft vNIC:
         - add handler for device-originated servicing events
         - allow dynamic MSI-X vector allocation
         - support Tx bandwidth clamping

   - Ethernet NICs consumer, and embedded:
      - AMD:
         - amd-xgbe: hardware timestamping and PTP clock support
      - Broadcom integrated MACs (bcmgenet, bcmasp):
         - use napi_complete_done() return value to support NAPI polling
         - add support for re-starting auto-negotiation
      - Broadcom switches (b53):
         - support BCM5325 switches
         - add bcm63xx EPHY power control
      - Synopsys (stmmac):
         - lots of code refactoring and cleanups
      - TI:
         - icssg-prueth: read firmware-names from device tree
         - icssg: PRP offload support
      - Microchip:
         - lan78xx: convert to PHYLINK for improved PHY and MAC management
         - ksz: add KSZ8463 switch support
      - Intel:
         - support similar queue priority scheme in multi-queue and
           time-sensitive networking (taprio)
         - support packet pre-emption in both
      - RealTek (r8169):
         - enable EEE at 5Gbps on RTL8126
      - Airoha:
         - add PPPoE offload support
         - MDIO bus controller for Airoha AN7583

   - Ethernet PHYs:
      - support for the IPQ5018 internal GE PHY
      - micrel KSZ9477 switch-integrated PHYs:
         - add MDI/MDI-X control support
         - add RX error counters
         - add cable test support
         - add Signal Quality Indicator (SQI) reporting
      - dp83tg720: improve reset handling and reduce link recovery time
      - support bcm54811 (and its MII-Lite interface type)
      - air_en8811h: support resume/suspend
      - support PHY counters for QCA807x and QCA808x
      - support WoL for QCA807x

   - CAN drivers:
      - rcar_canfd: support for Transceiver Delay Compensation
      - kvaser: report FW versions via devlink dev info

   - WiFi:
      - extended regulatory info support (6 GHz)
      - add statistics and beacon monitor for Multi-Link Operation (MLO)
      - support S1G aggregation, improve S1G support
      - add Radio Measurement action fields
      - support per-radio RTS threshold
      - some work around how FIPS affects wifi, which was wrong (RC4 is
        used by TKIP, not only WEP)
      - improvements for unsolicited probe response handling

   - WiFi drivers:
      - RealTek (rtw88):
         - IBSS mode for SDIO devices
      - RealTek (rtw89):
         - BT coexistence for MLO/WiFi7
         - concurrent station + P2P support
         - support for USB devices RTL8851BU/RTL8852BU
      - Intel (iwlwifi):
         - use embedded PNVM in (to be released) FW images to fix
           compatibility issues
         - many cleanups (unused FW APIs, PCIe code, WoWLAN)
         - some FIPS interoperability
      - MediaTek (mt76):
         - firmware recovery improvements
         - more MLO work
      - Qualcomm/Atheros (ath12k):
         - fix scan on multi-radio devices
         - more EHT/Wi-Fi 7 features
         - encapsulation/decapsulation offload
      - Broadcom (brcm80211):
         - support SDIO 43751 device

   - Bluetooth:
      - hci_event: add support for handling LE BIG Sync Lost event
      - ISO: add socket option to report packet seqnum via CMSG
      - ISO: support SCM_TIMESTAMPING for ISO TS

   - Bluetooth drivers:
      - intel_pcie: support Function Level Reset
      - nxpuart: add support for 4M baudrate
      - nxpuart: implement powerup sequence, reset, FW dump, and FW loading"

* tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next: (1742 commits)
  dpll: zl3073x: Fix build failure
  selftests: bpf: fix legacy netfilter options
  ipv6: annotate data-races around rt->fib6_nsiblings
  ipv6: fix possible infinite loop in fib6_info_uses_dev()
  ipv6: prevent infinite loop in rt6_nlmsg_size()
  ipv6: add a retry logic in net6_rt_notify()
  vrf: Drop existing dst reference in vrf_ip6_input_dst
  net/sched: taprio: align entry index attr validation with mqprio
  net: fsl_pq_mdio: use dev_err_probe
  selftests: rtnetlink.sh: remove esp4_offload after test
  vsock: remove unnecessary null check in vsock_getname()
  igb: xsk: solve negative overflow of nb_pkts in zerocopy mode
  stmmac: xsk: fix negative overflow of budget in zerocopy mode
  dt-bindings: ieee802154: Convert at86rf230.txt yaml format
  net: dsa: microchip: Disable PTP function of KSZ8463
  net: dsa: microchip: Setup fiber ports for KSZ8463
  net: dsa: microchip: Write switch MAC address differently for KSZ8463
  net: dsa: microchip: Use different registers for KSZ8463
  net: dsa: microchip: Add KSZ8463 switch support to KSZ DSA driver
  dt-bindings: net: dsa: microchip: Add KSZ8463 switch support
  ...
 2025-07-30 08:58:55 -07:00
Stephen Boyd
c30cc9ffc1
Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next 
* clk-rockchip:
  clk: rockchip: rk3568: Add PLL rate for 132MHz

* clk-thead:
  clk: thead: th1520-ap: Describe mux clocks with clk_mux
  clk: thead: th1520-ap: Correctly refer the parent of osc_12m
  clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSED

* clk-microchip:
  clk: at91: sam9x7: update pll clk ranges

* clk-imx:
  MAINTAINERS: Update i.MX Clock Entry
  clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
  clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
  clk: imx95-blk-ctl: Fix synchronous abort
  dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data

* clk-qcom: (65 commits)
  dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
  dt-bindings: clock: qcom: Remove double colon from description
  clk: qcom: Add Video Clock controller (VIDEOCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Video Clock Controller
  clk: qcom: Add Graphics Clock controller (GPUCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos GPU Clock Controller
  clk: qcom: Add Display Clock controller (DISPCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Display Clock Controller
  clk: qcom: Add Camera Clock controller (CAMCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Camera Clock Controller
  clk: qcom: Add Global Clock controller (GCC) driver for Milos
  dt-bindings: clock: qcom: document the Milos Global Clock Controller
  clk: qcom: common: Add support to register rcg dfs in qcom_cc_really_probe
  clk: qcom: gcc-x1e80100: Add missing video resets
  dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
  clk: qcom: videocc-sm8550: Add separate frequency tables for X1E80100
  clk: qcom: videocc-sm8550: Allow building without SM8550/SM8560 GCC
  ...
 2025-07-29 15:19:17 -07:00