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Linus Torvalds
86bcf7be1e RISC-V updates for the v6.18 merge window (part two) 
Second set of RISC-V updates for the v6.18 merge window, consisting
 of:
 
 - Support for the RISC-V-standardized RPMI interface.
 
   RPMI is a platform management communication mechanism between OSes
   running on application processors, and a remote platform management
   processor.  Similar to ARM SCMI, TI SCI, etc.  This includes irqchip,
   mailbox, and clk changes.
 
 - Support for the RISC-V-standardized MPXY SBI extension.
 
   MPXY is a RISC-V-specific standard implementing a shared memory
   mailbox between S-mode operating systems (e.g., Linux) and M-mode
   firmware (e.g., OpenSBI).  It is part of this PR since one of its
   use cases is to enable M-mode firmware to act as a single RPMI client
   for all RPMI activity on a core (including S-mode RPMI activity).
   Includes a mailbox driver.
 
 - Some ACPI-related updates to enable the use of RPMI and MPXY.
 
 - The addition of Linux-wide memcpy_{from,to}_le32() static inline
   functions, for RPMI use.
 
 - An ACPI Kconfig change to enable boot logos on any ACPI-using
   architecture (including RISC-V)
 
 - A RISC-V defconfig change to add GPIO keyboard and event device
   support, for front panel shutdown or reboot buttons
 
 This PR also includes a recent, one-line Kconfig patch from Geert to
 keep non-RISC-V users from being asked about building the RPMI virtual
 clock driver when !COMPILE_TEST.  THere's nothing preventing
 non-RISC-V SoCs from implementing RPMI, but until some users show up,
 let's not annoy others with it.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAmjfNccACgkQx4+xDQu9
 KkugVBAAsa9Oc6iEV1rwj1clWDrvz/bFJRxr/oH3PX0yJ4JJcZaBTydeW3fyJTJ8
 CzmRClGJ18YWjapJXYhMp1AS/VfsULu2AVfUzZUqHTjVZyxgt8xFgygpI+BHIyUN
 vD26iKJz/JvnytRmUi7mMtS0O48nTzdMiiOmu4Ved68YMJCRJKFZw8+rWVcAzrwb
 FHZlIE5Fcb1PRaUDg/45Baj0nEr+NRGKDLsR1rbocbmCmRMnz3ufPTcXk128+3gC
 VB1rQplcMBf2RpCl7p4LW2N746hcbg/RogfpjFy7KLlnEH+Xoh2nCxcWHaiEgR9q
 6JPsYBeekA54ZZsdoNBg1i5rGk3j/G1XGaV1bo7HDLTvShSByhaYrhAedQZEbw//
 xC3Eb7EQ6rNYUUjXiX0y5nhvl+nVlu/FmcsZmcP30ppOV4MQasTZ0zqfso23xhjL
 2e06PwTqsmXDeDNDQ4ruBKrpu8tkA7ZZvjCMq1rvSWjTPObzuGBe/ENrdBUOBb2E
 6UUeAGCZpQm1IxTcKHHxaIDT5ami745kqaBrXanIMKPX1JdCs7ahUqqWzC0LEgSy
 qB/T12bYg5O/yKXdXJuAuTHFb3TOPn6l8aNxRJve+uFwv4r1XXptdal9Yg2xoBWo
 EoGktm8KAp5Ndn5BntXI4xG4Ia3HOsj9YA7y4Iep4EO94JZk3Fk=
 =Ys1m
 -----END PGP SIGNATURE-----

Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull more RISC-V updates from Paul Walmsley:

 - Support for the RISC-V-standardized RPMI interface.

   RPMI is a platform management communication mechanism between OSes
   running on application processors, and a remote platform management
   processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip,
   mailbox, and clk changes.

 - Support for the RISC-V-standardized MPXY SBI extension.

   MPXY is a RISC-V-specific standard implementing a shared memory
   mailbox between S-mode operating systems (e.g., Linux) and M-mode
   firmware (e.g., OpenSBI). It is part of this PR since one of its use
   cases is to enable M-mode firmware to act as a single RPMI client for
   all RPMI activity on a core (including S-mode RPMI activity).
   Includes a mailbox driver.

 - Some ACPI-related updates to enable the use of RPMI and MPXY.

 - The addition of Linux-wide memcpy_{from,to}_le32() static inline
   functions, for RPMI use.

 - An ACPI Kconfig change to enable boot logos on any ACPI-using
   architecture (including RISC-V)

 - A RISC-V defconfig change to add GPIO keyboard and event device
   support, for front panel shutdown or reboot buttons

* tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits)
  clk: COMMON_CLK_RPMI should depend on RISCV
  ACPI: support BGRT table on RISC-V
  MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers
  RISC-V: Enable GPIO keyboard and event device in RV64 defconfig
  irqchip/riscv-rpmi-sysmsi: Add ACPI support
  mailbox/riscv-sbi-mpxy: Add ACPI support
  irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode()
  ACPI: RISC-V: Add RPMI System MSI to GSI mapping
  ACPI: RISC-V: Add support to update gsi range
  ACPI: RISC-V: Create interrupt controller list in sorted order
  ACPI: scan: Update honor list for RPMI System MSI
  ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args()
  ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop
  irqchip: Add driver for the RPMI system MSI service group
  dt-bindings: Add RPMI system MSI interrupt controller bindings
  dt-bindings: Add RPMI system MSI message proxy bindings
  clk: Add clock driver for the RISC-V RPMI clock service group
  dt-bindings: clock: Add RPMI clock service controller bindings
  dt-bindings: clock: Add RPMI clock service message proxy bindings
  mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
  ...
 2025-10-04 10:36:22 -07:00
Linus Torvalds
38057e3236 soc: driver updates for 6.18 
Lots of platform specific updates for Qualcomm SoCs, including a
 new TEE subsystem driver for the Qualcomm QTEE firmware interface.
 
 Added support for the Apple A11 SoC in drivers that are shared with the
 M1/M2 series, among more updates for those.
 
 Smaller platform specific driver updates for Renesas, ASpeed, Broadcom,
 Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs.
 
 Driver updates in the cache controller, memory controller and reset
 controller subsystems.
 
 SCMI firmware updates to add more features and improve robustness.
 This includes support for having multiple SCMI providers in a single
 system.
 
 TEE subsystem support for protected DMA-bufs, allowing hardware to
 access memory areas that managed by the kernel but remain inaccessible
 from the CPU in EL1/EL0.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdpaoACgkQmmx57+YA
 GNnBXA//QgmFXYGG7QfB825mt0orKZxpfpLcwvqO7hkWgbXtl7Gokw2lGYN6bwLu
 zvY4MQ/bVoZ8R5uTVmuaSHBRsttSen8mBf+V0vzsBM/DRRVxvIN/7TESrY3J7Dtx
 J5syHKIBiUtdkDebWWC6jIElczIBItsd03Ln4Xjjt8Vas5YOO4n44zFrPo+FwlN/
 I6D2K86AiNZTtUCDMtB6VfJ6YtjYBWcWnJm7FXw/vE8FAXdZUnNWnZ8hbdQ5GaME
 JZGepUhONaOMUoGNZNaDGw511RdPhYzPjj9rCsIx2qdsRO9/4tJ8ccpW2aUMYh8c
 nA6w8Hj8jCwco6aYYrDUDV9uRtURDrmyJgTJBNLU05e/L+MuJ3IZNlzHFWlsxIAE
 vhyTdmg/P04ClQyixCl67IH/66F/0smX9C+1761LrD7GTdfR92KPl5W6q+DPBg/x
 yf+s2p3+f7ItV5XobKOrbf3w0xazeDb5o/EK8BufMx9vSe9bpzJ0gOf0CmNXEpyZ
 owAhbh6wXX1YwPcyA9LHv6gthyJwc/3fLu49ggMZP2rU01ccKOYn9H0cr7C8NVmy
 wEpJR0lp5aSw2oRkPkxB6sFmUohcpr8/OXGGJuvCXkYsUY1BEup4lewvbIWK4WoE
 c84kbbaHsjgFhe3IRlQw3G4KLYQT3jRtF7fH+gPx556BcI6K+lg=
 =mcZR
 -----END PGP SIGNATURE-----

Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC driver updates from Arnd Bergmann:
 "Lots of platform specific updates for Qualcomm SoCs, including a new
  TEE subsystem driver for the Qualcomm QTEE firmware interface.

  Added support for the Apple A11 SoC in drivers that are shared with
  the M1/M2 series, among more updates for those.

  Smaller platform specific driver updates for Renesas, ASpeed,
  Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
  SoCs.

  Driver updates in the cache controller, memory controller and reset
  controller subsystems.

  SCMI firmware updates to add more features and improve robustness.
  This includes support for having multiple SCMI providers in a single
  system.

  TEE subsystem support for protected DMA-bufs, allowing hardware to
  access memory areas that managed by the kernel but remain inaccessible
  from the CPU in EL1/EL0"

* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
  soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
  soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
  soc: fsl: qe: Change GPIO driver to a proper platform driver
  tee: fix register_shm_helper()
  pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
  dt-bindings: spmi: Add Apple A11 and T2 compatible
  serial: qcom-geni: Load UART qup Firmware from linux side
  spi: geni-qcom: Load spi qup Firmware from linux side
  i2c: qcom-geni: Load i2c qup Firmware from linux side
  soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
  soc: qcom: geni-se: Cleanup register defines and update copyright
  dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
  Documentation: tee: Add Qualcomm TEE driver
  tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
  tee: qcom: add primordial object
  tee: add Qualcomm TEE driver
  tee: increase TEE_MAX_ARG_SIZE to 4096
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
  tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
  tee: add close_context to TEE driver operation
  ...
 2025-10-01 17:32:51 -07:00
Linus Torvalds
a8253f8077 soc: new SoC support for 6.18 
Pinkesh Vaghela adds support for the ESWIN EIC7700 SoC, as
 described in [1]:
 
  "Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
   P550 CPU cluster and the first development board that uses it, the
   SiFive HiFive Premier P550.
 
   This patch series adds initial device tree and also adds ESWIN
   architecture support.
 
   Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier
   P550 board using U-Boot 2024.01 and OpenSBI 1.4."
 
 [1] https://lore.kernel.org/linux-riscv/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmjdpqUACgkQmmx57+YA
 GNlh3g//QmkkOnHUZvbUNNhf3WMulaVFA7K8pX6DB+ZI8WJSY3asJsKKUfgx5EhO
 Dml85lMYI4RUtia6TkSQ9RgG7ECmrcn07RWEqUR5MNeAYh2+lcVHn6dEO6vSmllG
 yxXH1AcqRm1CP9nKnz8g5yRcrndfPVKGl8oIENlyfnGoBmrdPanKElXvx6krzexw
 J8h/BJo29TntCqUCDsw9/N+5xA9lUVHS7v7alF01M10w48nDaEg8l/X7QxUhxhKl
 Knd9o8abNzxt2au8AunS91rJhZCxm17Gnwsg3R3ij+Ws+Dgao3aWpYRVRIE2ND7m
 6YhWIK+IeuMI48dnZ+QzKbNhwvF/RLUOt3P8zNGyRxDGh8azLUCp3BXtt8FSrJ2n
 /mSCrQyB2BnQHJs4cD6I2+shHWVpMJ9mf0lmQZBINamTkXFqIoIisGih/YDdX9x3
 5BDG4D9mNFAP+qzLcrHq0WNGfHZHbhk06sw0YEv6AhgRgeKqRIjbWUn+8l7EnQts
 8E8vZc+Ztd61hxLP3XD5Ads01kDz5nAU/7IJ6l+0r7qp+S6GxjKkaPXsvrdSscTn
 bACIgw5hsFr5t9rleyTcyS5XeqGwt778jA4mjC8PFLmXKqf0vpuCAOCSFjk7euea
 pMJjeyH6khA0VXCDvgolCF+O3STVY3RtqefEwJaOmBtQaycmNZ8=
 =DONh
 -----END PGP SIGNATURE-----

Merge tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull new SoC support from Arnd Bergmann:
 "Pinkesh Vaghela adds support for the ESWIN EIC7700 SoC consisting of
  SiFive Quad-Core P550 CPU cluster and the first development board that
  uses it, the SiFive HiFive Premier P550 [1].

  This adds initial device tree and also adds ESWIN architecture
  support.

  Boot-tested using intiramfs with Linux v6.17-rc3 on HiFive Premier
  P550 board using U-Boot 2024.01 and OpenSBI 1.4"

Link: https://lore.kernel.org/linux-riscv/20250825132427.1618089-1-pinkesh.vaghela@einfochips.com/ [1]

* tag 'soc-newsoc-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  riscv: dts: eswin: add HiFive Premier P550 board device tree
  riscv: dts: add initial support for EIC7700 SoC
  dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
  dt-bindings: riscv: Add SiFive HiFive Premier P550 board
  riscv: Add Kconfig option for ESWIN platforms
  dt-bindings: riscv: Add SiFive P550 CPU compatible
 2025-10-01 17:10:27 -07:00
Linus Torvalds
9792d660a4 Devicetree updates for v6.18: 
DT core:
 - Update dtc to upstream version v1.7.2-35-g52f07dcca47c
 
 - Add stub for of_get_next_child_with_prefix()
 
 - Convert of_msi_map_id() callers to of_msi_xlate()
 
 DT bindings:
 - Convert Megachips stdpxxxx-ge-b850v3-fw DP bridges, NVIDIA Tegra GPUs,
   SUN Sparc RNG, aspeed,ast2400-sdram-edac, Marvell arm32 SoCs, Marvell
   Berlin SoCs, apm,xgene-edac, marvell,armada-ap806-thermal,
   marvell,armada370-thermal, marvell,armada-3700-wdt, nuvoton,npcm-wdt,
   brcm,iproc-flexrm-mbox, brcm,iproc-pdc-mbox,
   marvell,armada-3700-rwtm-mailbox, rockchip,rk3368-mailbox,
   eckelmann,siox-gpio, aspeed,ast2400-gfx, apm,xgene-pmu,
   hisilicon,mbigen-v2, cavium,thunder-88xx,
   aspeed,ast2400-cf-fsi-master,
   fsi-master-gpio, and mediatek,mt8173-vpu bindings to DT schema format
 
 - Add bindings for synaptics,synaptics_i2c touchscreen controller,
   innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
   vf610 reboot controller
 
 - Add new Arm Cortex-A320/A520AE/A720AE and
   C1-Nano/Pro/Premium/Ultra CPUs. Add missing Applied Micro CPU
   compatibles. Add pu-supply and fsl,soc-operating-points properties for
   CPU nodes.
 
 - Add QCom Glymur PDC and tegra264-agic interrupt controllers
 
 - Add samsung,exynos8890-mali GPU to Arm Mali Midgard
 
 - Drop Samsung S3C2410 display related bindings
 
 - Allow separate DP lane and AUX connections in dp-connector
 
 - Add some missing, undocumented vendor prefixes
 
 - Add missing '#address-cells' properties in interrupt controller
   bindings which dtc now warns about
 
 - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
   fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
   bindings which are already covered by existing schemas.
 
 - Various binding fixes for Mediatek platforms in mailbox, regulator,
   pinctrl, timer, and display
 
 - Drop work-around for yamllint quoting of values containing ','
 
 - Various spelling, typo, grammar, and duplicated words fixes in DT
   bindings and docs
 
 - Add binding guidelines for defining properties at top level of
   schemas, lack of node name ABI, and usage of simple-mfd
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmjatrgACgkQ+vtdtY28
 YcMyOBAAlZW1GqpFbfh0TBGL3HTOdBgEqBdBvoVigkzQxpIpgGHBfQiyY2z5WUru
 TzgQ2fK+hBHRx/7KsizpxHNWX5LWX9pUbVmJsDqBMlIAqtNnJGqKDjXibCYdtonf
 IsK8Ow48LHfVPcGPixaFhbvoxIL7hg8b+4OgVPjUN3Bbj6Tsh+bi+SzH0bJhWmLD
 842jqUeymxeeYZBW4lKvjWKK6QWU+zwtCeuZfzMC/iOn9YB8x8FqGhFG951aSA8g
 kgdi36tOyYAmGj6kbTTOlUFrmHC5qQbXQUv8evhz7h4pw0xPXPkg0Foe7WfJBFq3
 CnfHuhmFadwfUI6K4WAK/TfM9QEi9fm+Nu0sv/q4s6YHlfGGuA9AVgRRWLhC9aAr
 CDp73jF4/aXWmUe5MZZiee1aHSbl9DzdDx+UEpjX3V8I2DiRyFXTuy9p5shkmH7D
 mUX+GdRf4cF+uxwWz4/G4XTHkFMgpoUJBoz8Hwn10JG1//+Na1FBrPHx2jeRyTpb
 HLXf7G8MIrpVUT2FkurVFV1QSWB9VB3Lm9wwT7KbAaEA82n8OYI7sM/ZABFOEMCD
 /ZnwdOjq3izUcrejwr6iP436gHBvwId1IyVQFtY+dDcgS1neZ9LMqsvcDS2GAW30
 P8wkt5ogiu0zIc6ysgKMCW9VV3Fh9ZcplMhylTqDrpV+A0O+QbQ=
 =pcE2
 -----END PGP SIGNATURE-----

Merge tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Update dtc to upstream version v1.7.2-35-g52f07dcca47c

   - Add stub for of_get_next_child_with_prefix()

   - Convert of_msi_map_id() callers to of_msi_xlate()

 DT bindings:

   - Convert multiple text board bindings to DT schema format

   - Add bindings for synaptics,synaptics_i2c touchscreen controller,
     innolux,n133hse-ea1 and nlt,nl12880bc20-spwg-24 displays, and NXP
     vf610 reboot controller

   - Add new Arm Cortex-A320/A520AE/A720AE and C1-Nano/Pro/Premium/Ultra
     CPUs. Add missing Applied Micro CPU compatibles. Add pu-supply and
     fsl,soc-operating-points properties for CPU nodes.

   - Add QCom Glymur PDC and tegra264-agic interrupt controllers

   - Add samsung,exynos8890-mali GPU to Arm Mali Midgard

   - Drop Samsung S3C2410 display related bindings

   - Allow separate DP lane and AUX connections in dp-connector

   - Add some missing, undocumented vendor prefixes

   - Add missing '#address-cells' properties in interrupt controller
     bindings which dtc now warns about

   - Drop duplicate socfpga-sdram-edac.txt, moxa,moxart-watchdog.txt,
     fsl/mpic.txt, ti,opa362.txt, and cavium-thunder2.txt legacy text
     bindings which are already covered by existing schemas.

   - Various binding fixes for Mediatek platforms in mailbox, regulator,
     pinctrl, timer, and display

   - Drop work-around for yamllint quoting of values containing ','

   - Various spelling, typo, grammar, and duplicated words fixes in DT
     bindings and docs

   - Add binding guidelines for defining properties at top level of
     schemas, lack of node name ABI, and usage of simple-mfd"

* tag 'devicetree-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (81 commits)
  dt-bindings: arm: altera: Drop socfpga-sdram-edac.txt
  dt-bindings: gpu: Convert nvidia,gk20a to DT schema
  dt-bindings: rng: sparc_sun_oracle_rng: convert to DT schema
  dt-bindings: vendor-prefixes: update regex for properties without a prefix
  dt-bindings: display: bridge: convert megachips-stdpxxxx-ge-b850v3-fw.txt to yaml
  scripts: dt_to_config: fix grammar and a typo in --help text
  dt-bindings: fix spelling, typos, grammar, duplicated words
  docs: dt: fix grammar and spelling
  of: base: Add of_get_next_child_with_prefix() stub
  dt-bindings: trivial-devices: Add compatible string synaptics,synaptics_i2c
  dt-bindings: soc: mediatek: pwrap: Add power-domains property
  dt-bindings: pinctrl: mt65xx: Allow gpio-line-names
  dt-bindings: media: Convert MediaTek mt8173-vpu bindings to DT schema
  dt-bindings: arm: mediatek: Support mt8183-audiosys variant
  dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
  dt-bindings: regulator: mediatek,mt6331: Add missing compatible
  dt-bindings: regulator: mediatek,mt6331: Fix various regulator names
  dt-bindings: regulator: mediatek,mt6332-regulator: Add missing compatible
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing base reg
  dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
  ...
 2025-10-01 16:58:24 -07:00
Linus Torvalds
b4918003cf MFD for v6.18 
This round of updates contains a fair amount of new device support, a couple of fixes and
 some refactoring.  The most notable additions include new drivers for Loongson's Security
 Engine, RNG and TPM, new drivers for TI's TPS6594 Power Button and BQ257xx Charger ICs.
 
 The rest of the set provides a return value check fix and a refactoring to use a more modern
 GPIO API for the VEXPRESS sysreg driver, the removal of a deprecated IRQ ACK function from the
 MC13xxx RTC driver and a new DT binding for the aforementioned TI BQ257xx charger.
 
 New Support & Features
 - Add a suite of drivers for the Loongson Security Engine, including the core controller, a
   Random Number Generator (RNG) and Trusted Platform Module (TPM) support.
 - Introduce support for the TI TPS6594 PMIC's power button, including the input driver, MFD
   cell registration, and a system power-off handler.
 - Add comprehensive support for the TI BQ257xx series of charger ICs, including the core MFD
   driver and a power supply driver for the charger functionality.
 
 Improvements & Fixes
 - Check the return value of devm_gpiochip_add_data() in the VEXPRESS sysreg driver to prevent
   potential silent failures.
 
 Cleanups & Refactoring
 - Add a MAINTAINERS entry for the new Loongson Security Engine drivers.
 - Convert the VEXPRESS sysreg driver to use the modern generic GPIO chip API.
 
 Removals
 - Remove the deprecated and unused mc13xxx_irq_ack() function from the MC13xxx RTC, input and
   touchscreen drivers.
 
 Device Tree Bindings Updates
 - Add device tree bindings for the TI BQ25703A charger.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEdrbJNaO+IJqU8IdIUa+KL4f8d2EFAmjdMogACgkQUa+KL4f8
 d2FYEA/+J3U3bzH0JdjGVscQD1vLq+PjT0MsYoNLHSNG55H0Q9FhEv2SVmnRG8LR
 DPvYXqpLHcHTGpPdCK7RX6FhSmXMFqXiWFbn9/lQE/+MX41U0B9E7rbRVCH8m+Vw
 TAOvR86DEcTZFq3BEPDfjc4Q0ZPHKpyo/HOW739frmwC/a66K6G70vKmO+LJlqMk
 asBAZUfRs14iaZte8LDKfcYcvC4NrJqtLD9lxPiuGxapMCGvJ+uReo+44A0F+wb8
 UNq+cwdFK2rqPAur5ehe8C6s9IsANF4+OmAbbmqxfkbroiSYR7I2SeUhgxU/b8Om
 9v+NqfC7Xsb8lcTJ/c0qCW8NfBtOlqer1lEHGTU91fTCAhACb4j7OuJtnTusp9Nk
 W9Z9QcfOv/Mt7I/SUw9n8SQdHgPt9tQa6iqcGrYGp3enm8BISeb2jTTgrkDcCkKb
 UTH8xVmxFgda08RCmPDPvrK0ebQ6gQzdq4g5vN3or1tFIKQHplorbvaAQtCBK02h
 8ef33KrQ4HLV/NjijYrnFhrhj0WYBwmRb8vr43t4wvUdvlOSuK+VswKGIMhQabT3
 uU+YjtCt19siOIx47XZVpj1gKTr24OoK2B+U8zy5oHj7abrRNkseZ8NMeu0vGzCn
 p+ThEq+dxGD0mskaufdbJhejjumgCFaYNElWNHJQUGhMxHM5vQE=
 =h21C
 -----END PGP SIGNATURE-----

Merge tag 'mfd-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "This round of updates contains a fair amount of new device support, a
  couple of fixes and some refactoring. The most notable additions
  include new drivers for Loongson's Security Engine, RNG and TPM, new
  drivers for TI's TPS6594 Power Button and BQ257xx Charger ICs.

  The rest of the set provides a return value check fix and a
  refactoring to use a more modern GPIO API for the VEXPRESS sysreg
  driver, the removal of a deprecated IRQ ACK function from the MC13xxx
  RTC driver and a new DT binding for the aforementioned TI BQ257xx
  charger.

  New Support & Features:
   - Add a suite of drivers for the Loongson Security Engine, including
     the core controller, a Random Number Generator (RNG) and Trusted
     Platform Module (TPM) support.
   - Introduce support for the TI TPS6594 PMIC's power button, including
     the input driver, MFD cell registration, and a system power-off
     handler.
   - Add comprehensive support for the TI BQ257xx series of charger ICs,
     including the core MFD driver and a power supply driver for the
     charger functionality.

  Improvements & Fixes:
   - Check the return value of devm_gpiochip_add_data() in the VEXPRESS
     sysreg driver to prevent potential silent failures.

  Cleanups & Refactoring:
   - Add a MAINTAINERS entry for the new Loongson Security Engine
     drivers.
   - Convert the VEXPRESS sysreg driver to use the modern generic GPIO
     chip API.

  Removals:
   - Remove the deprecated and unused mc13xxx_irq_ack() function from
     the MC13xxx RTC, input and touchscreen drivers.

  Device Tree Bindings Updates:
   - Add device tree bindings for the TI BQ25703A charger"

* tag 'mfd-next-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (69 commits)
  mfd: simple-mfd-i2c: Add compatible string for LX2160ARDB
  mfd: simple-mfd-i2c: Keep compatible strings in alphabetical order
  dt-bindings: mfd: twl: Add missing sub-nodes for TWL4030 & TWL603x
  dt-bindings: watchdog: Add SMARC-sAM67 support
  dt-bindings: mfd: tps6594: Allow gpio-line-names
  mfd: intel-lpss: Add Intel Wildcat Lake LPSS PCI IDs
  mfd: 88pm886: Add GPADC cell
  mfd: vexpress-sysreg: Use more common syntax for compound literals
  mfd: rz-mtu3: Fix MTU5 NFCR register offset
  mfd: max77705: Setup the core driver as an interrupt controller
  mfd: cs42l43: Remove IRQ masking in suspend
  mfd: cs42l43: Move IRQ enable/disable to encompass force suspend
  mfd: ls2kbmc: Add Loongson-2K BMC reset function support
  mfd: ls2kbmc: Introduce Loongson-2K BMC core driver
  mfd: bd71828, bd71815: Prepare for power-supply support
  dt-bindings: mfd: aspeed: Add AST2700 SCU compatibles
  dt-bindings: mfd: Convert aspeed,ast2400-p2a-ctrl to DT schema
  dt-bindings: mfd: fsl,mc13xxx: Add buttons node
  dt-bindings: mfd: fsl,mc13xxx: Convert txt to DT schema
  mfd: macsmc: Add "apple,t8103-smc" compatible
  ...
 2025-10-01 12:04:12 -07:00
Krzysztof Kozlowski
3d6a17fccc dt-bindings: mfd: Move embedded controllers to own directory 
Move several embedded controller bindings (like ChromeOS EC, Gateworks
System Controller and Kontron sl28cpld Board Management) to new
subdirectory "embedded-controller" matching their purpose.

An embedded controller (EC) is a discrete component that contains a
microcontroller (i.e. a small CPU running a small firmware without
operating system) mounted into a larger computer system running
a fully fledged operating system that needs to utilize the embedded
controller as part of its operation.

So far the EC bindings were split between "mfd" and "platform"
directory.  MFD name comes from Linux, not hardware, and "platform" is a
bit too generic.

Rename Gateworks GSC and Huawei Gaokun filenames to match compatible, as
preferred for bindings.

Acked-by: Michael Walle <mwalle@kernel.org> # for sl28cpld
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Mark Brown <broonie@kernel.org>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250825081201.9775-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
 2025-10-01 10:28:27 +01:00
Pankaj Patil
4379fbb9b0 dt-bindings: interrupt-controller: qcom,pdc: Document Glymur PDC 
Document compatible for the Power Domain Controller(PDC)
block on Glymur.PDC acts as interrupt controller in
SoC states where GIC is non-operational.

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-09-26 14:50:43 -05:00
sheetal
c502ca1ea1 dt-bindings: interrupt-controller: arm,gic: Add tegra264-agic 
Add nvidia,tegra264-agic to the arm,gic binding for tegra264 audio
interrupt controller support.

Signed-off-by: sheetal <sheetal@nvidia.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-09-26 14:50:43 -05:00
Anup Patel
3e6cf38486 dt-bindings: Add RPMI system MSI interrupt controller bindings 
Add device tree bindings for the RPMI system MSI service group
based interrupt controller for the supervisor software.

The RPMI system MSI service group is defined by the RISC-V
platform management interface (RPMI) specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-13-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
 2025-09-25 14:31:54 -06:00
Anup Patel
a72ab2514b dt-bindings: Add RPMI system MSI message proxy bindings 
Add device tree bindings for the RPMI system MSI service group
based message proxy implemented by the SBI implementation (machine
mode firmware or hypervisor).

The RPMI system MSI service group is defined by the RISC-V
platform management interface (RPMI) specification.

Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-12-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
 2025-09-25 14:31:50 -06:00
Darshan Prajapati
21b5a7ace6
dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC 
Add compatible string for ESWIN EIC7700 PLIC.

Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250825132427.1618089-5-pinkesh.vaghela@einfochips.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2025-09-25 08:29:06 +02:00
Janne Grunau
0b95df9004 dt-bindings: interrupt-controller: apple,aic2: Add apple,t6020-aic compatible 
The Apple M2 Pro/Max/Ultra SoCs use AIC2 as interrupt controller. This
is the final SoC added as compatible as Apple M3 and later use AIC3.
Apple's A15 uses AIC2 as well but has no official support for alternate
operating systems.

Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Janne Grunau <j@jannau.net>
 2025-09-14 21:49:24 +02:00
Ryan Chen
ed7240444e dt-bindings: interrupt-controller: aspeed: Add AST2700 SCU IC compatibles 
Add compatible strings for the four SCU interrupt controller instances
on the AST2700 SoC (scu-ic0 to 3), following the multi-instance model used
on AST2600.

Also define interrupt indices in the binding header.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/all/20250908011812.1033858-4-ryan_chen@aspeedtech.com
 2025-09-09 12:23:28 +02:00
Krzysztof Kozlowski
8a72549c5b dt-bindings: interrupt-controller: marvell,cp110-icu: Document address-cells 
The CP110 ICU children are interrupt controllers and can be referenced
in interrupt-map properties (e.g. in
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi), thus the nodes should
have address-cells property.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20250823163258.49648-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-09-03 09:01:26 -05:00
Rob Herring (Arm)
326d251981 dt-bindings: powerpc: Drop duplicate fsl/mpic.txt 
The chrp,open-pic binding schema already supports the "fsl,mpic"
compatible. Add a couple of missing properties and support for 4
"#interrupt-cells" to the chrp,open-pic binding, so fsl/mpic.txt can be
removed.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250814135157.2747346-2-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-08-15 16:40:12 -05:00
Rob Herring (Arm)
01ce6aa56c dt-bindings: interrupt-controller: Convert hisilicon,mbigen-v2 to DT schema 
Convert the HiSilicon MBIGEN binding to DT schema format. It's a
straight-forward conversion.

Link: https://lore.kernel.org/r/20250812203327.730393-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-08-14 13:24:37 -05:00
Linus Torvalds
260f6f4fda drm for 6.17-rc1 
non-drm:
 rust:
 - make ETIMEDOUT available
 - add size constants up to SZ_2G
 - add DMA coherent allocation bindings
 mtd:
 - driver for Intel GPU non-volatile storage
 i2c
 - designware quirk for Intel xe
 
 core:
 - atomic helpers: tune enable/disable sequences
 - add task info to wedge API
 - refactor EDID quirks
 - connector: move HDR sink to drm_display_info
 - fourcc: half-float and 32-bit float formats
 - mode_config: pass format info to simplify
 
 dma-buf:
 - heaps: Give CMA heap a stable name
 
 ci:
 - add device tree validation and kunit
 
 displayport:
 - change AUX DPCD access probe address
 - add quirk for DPCD probe
 - add panel replay definitions
 - backlight control helpers
 
 fbdev:
 - make CONFIG_FIRMWARE_EDID available on all arches
 
 fence:
 - fix UAF issues
 
 format-helper:
 - improve tests
 
 gpusvm:
 - introduce devmem only flag for allocation
 - add timeslicing support to GPU SVM
 
 ttm:
 - improve eviction
 
 sched:
 - tracing improvements
 - kunit improvements
 - memory leak fixes
 - reset handling improvements
 
 color mgmt:
 - add hardware gamma LUT handling helpers
 
 bridge:
 - add destroy hook
 - switch to reference counted drm_bridge allocations
 - tc358767: convert to devm_drm_bridge_alloc
 - improve CEC handling
 
 panel:
 - switch to reference counter drm_panel allocations
 - fwnode panel lookup
 - Huiling hl055fhv028c support
 - Raspberry Pi 7" 720x1280 support
 - edp: KDC KD116N3730A05, N160JCE-ELL CMN, N116BCJ-EAK
 - simple: AUO P238HAN01
 - st7701: Winstar wf40eswaa6mnn0
 - visionox: rm69299-shift
 - Renesas R61307, Renesas R69328 support
 - DJN HX83112B
 
 hdmi:
 - add CEC handling
 - YUV420 output support
 
 xe:
 - WildCat Lake support
 - Enable PanthorLake by default
 - mark BMG as SRIOV capable
 - update firmware recommendations
 - Expose media OA units
 - aux-bux support for non-volatile memory
 - MTD intel-dg driver for non-volatile memory
 - Expose fan control and voltage regulator in sysfs
 - restructure migration for multi-device
 - Restore GuC submit UAF fix
 - make GEM shrinker drm managed
 - SRIOV VF Post-migration recovery of GGTT nodes
 - W/A additions/reworks
 - Prefetch support for svm ranges
 - Don't allocate managed BO for each policy change
 - HWMON fixes for BMG
 - Create LRC BO without VM
 - PCI ID updates
 - make SLPC debugfs files optional
 - rework eviction rejection of bound external BOs
 - consolidate PAT programming logic for pre/post Xe2
 - init changes for flicker-free boot
 - Enable GuC Dynamic Inhibit Context switch
 
 i915:
 - drm_panic support for i915/xe
 - initial flip queue off by default for LNL/PNL
 - Wildcat Lake Display support
 - Support for DSC fractional link bpp
 - Support for simultaneous Panel Replay and Adaptive sync
 - Support for PTL+ double buffer LUT
 - initial PIPEDMC event handling
 - drm_panel_follower support
 - DPLL interface renames
 - allocate struct intel_display dynamically
 - flip queue preperation
 - abstract DRAM detection better
 - avoid GuC scheduling stalls
 - remove DG1 force probe requirement
 - fix MEI interrupt handler on RT kernels
 - use backlight control helpers for eDP
 - more shared display code refactoring
 
 amdgpu:
 - add userq slot to INFO ioctl
 - SR-IOV hibernation support
 - Suspend improvements
 - Backlight improvements
 - Use scaling for non-native eDP modes
 - cleaner shader updates for GC 9.x
 - Remove fence slab
 - SDMA fw checks for userq support
 - RAS updates
 - DMCUB updates
 - DP tunneling fixes
 - Display idle D3 support
 - Per queue reset improvements
 - initial smartmux support
 
 amdkfd:
 - enable KFD on loongarch
 - mtype fix for ext coherent system memory
 
 radeon:
 - CS validation additional GL extensions
 - drop console lock during suspend/resume
 - bump driver version
 
 msm:
 - VM BIND support
 - CI: infrastructure updates
 - UBWC single source of truth
 - decouple GPU and KMS support
 - DP: rework I/O accessors
 - DPU: SM8750 support
 - DSI: SM8750 support
 - GPU: X1-45 support and speedbin support for X1-85
 - MDSS: SM8750 support
 
 nova:
 - register! macro improvements
 - DMA object abstraction
 - VBIOS parser + fwsec lookup
 - sysmem flush page support
 - falcon: generic falcon boot code and HAL
 - FWSEC-FRTS: fb setup and load/execute
 
 ivpu:
 - Add Wildcat Lake support
 - Add turbo flag
 
 ast:
 - improve hardware generations implementation
 
 imx:
 - IMX8qxq Display Controller support
 
 lima:
 - Rockchip RK3528 GPU support
 
 nouveau:
 - fence handling cleanup
 
 panfrost:
 - MT8370 support
 - bo labeling
 - 64-bit register access
 
 qaic:
 - add RAS support
 
 rockchip:
 - convert inno_hdmi to a bridge
 
 rz-du:
 - add RZ/V2H(P) support
 - MIPI-DSI DCS support
 
 sitronix:
 - ST7567 support
 
 sun4i:
 - add H616 support
 
 tidss:
 - add TI AM62L support
 - AM65x OLDI bridge support
 
 bochs:
 - drm panic support
 
 vkms:
 - YUV and R* format support
 - use faux device
 
 vmwgfx:
 - fence improvements
 
 hyperv:
 - move out of simple
 - add drm_panic support
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmiJM/0ACgkQDHTzWXnE
 hr6MpA/+JJKGdSdrE95QkaMcOZh/3e3areGXZ0V/RrrJXdB4/DoAfQSHhF0H7m7y
 MhBGVLGNMXq7KHrz28p1MjLHrE1mwmvJ6hZ4J076ed4u9naoCD0m6k5w5wiue+KL
 HyPR54ADxN0BYmgV0l/B0wj42KsHyTO4x4hdqPJu02V9Dtmx6FCh2ujkOF3p9nbK
 GMwWDttl4KEKljD0IvQ9YIYJ66crYGx/XmZi7JoWRrS104K/h1u8qZuXBp5jVKTy
 OZRAVyLdmJqdTOLH7l599MBBcEd/bNV37/LVwF4T5iFunEKOAiyN0QY0OR+IeRVh
 ZfOv2/gp4UNyIfyahQ7LKLgEilNPGHoPitvDJPvBZxW2UjwXVNvA1QfdK5DAlVRS
 D5NoFRjlFFCz8/c2hQwlKJ9o7eVgH3/pK0mwR7SPGQTuqzLFCrAfCuzUvg/gV++6
 JFqmGKMHeCoxO2o4GMrwjFttStP41usxtV/D+grcbPteNO9UyKJS4C38n4eamJXM
 a9Sy9APuAb6F0w5+yMItEF7TQifgmhIbm5AZHlxE1KoDQV6TdiIf1Gou5LeDGoL6
 OACbXHJPL52tUnfCRpbfI4tE/IVyYsfL01JnvZ5cZZWItXfcIz76ykJri+E0G60g
 yRl/zkimHKO4B0l/HSzal5xROXr+3VzeWehEiz/ot1VriP5OesA=
 =n9MO
 -----END PGP SIGNATURE-----

Merge tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel

Pull drm updates from Dave Airlie:
 "Highlights:

   - Intel xe enable Panthor Lake, started adding WildCat Lake

   - amdgpu has a bunch of reset improvments along with the usual IP
     updates

   - msm got VM_BIND support which is important for vulkan sparse memory

   - more drm_panic users

   - gpusvm common code to handle a bunch of core SVM work outside
     drivers.

  Detail summary:

  Changes outside drm subdirectory:
   - 'shrink_shmem_memory()' for better shmem/hibernate interaction
   - Rust support infrastructure:
      - make ETIMEDOUT available
      - add size constants up to SZ_2G
      - add DMA coherent allocation bindings
   - mtd driver for Intel GPU non-volatile storage
   - i2c designware quirk for Intel xe

  core:
   - atomic helpers: tune enable/disable sequences
   - add task info to wedge API
   - refactor EDID quirks
   - connector: move HDR sink to drm_display_info
   - fourcc: half-float and 32-bit float formats
   - mode_config: pass format info to simplify

  dma-buf:
   - heaps: Give CMA heap a stable name

  ci:
   - add device tree validation and kunit

  displayport:
   - change AUX DPCD access probe address
   - add quirk for DPCD probe
   - add panel replay definitions
   - backlight control helpers

  fbdev:
   - make CONFIG_FIRMWARE_EDID available on all arches

  fence:
   - fix UAF issues

  format-helper:
   - improve tests

  gpusvm:
   - introduce devmem only flag for allocation
   - add timeslicing support to GPU SVM

  ttm:
   - improve eviction

  sched:
   - tracing improvements
   - kunit improvements
   - memory leak fixes
   - reset handling improvements

  color mgmt:
   - add hardware gamma LUT handling helpers

  bridge:
   - add destroy hook
   - switch to reference counted drm_bridge allocations
   - tc358767: convert to devm_drm_bridge_alloc
   - improve CEC handling

  panel:
   - switch to reference counter drm_panel allocations
   - fwnode panel lookup
   - Huiling hl055fhv028c support
   - Raspberry Pi 7" 720x1280 support
   - edp: KDC KD116N3730A05, N160JCE-ELL CMN, N116BCJ-EAK
   - simple: AUO P238HAN01
   - st7701: Winstar wf40eswaa6mnn0
   - visionox: rm69299-shift
   - Renesas R61307, Renesas R69328 support
   - DJN HX83112B

  hdmi:
   - add CEC handling
   - YUV420 output support

  xe:
   - WildCat Lake support
   - Enable PanthorLake by default
   - mark BMG as SRIOV capable
   - update firmware recommendations
   - Expose media OA units
   - aux-bux support for non-volatile memory
   - MTD intel-dg driver for non-volatile memory
   - Expose fan control and voltage regulator in sysfs
   - restructure migration for multi-device
   - Restore GuC submit UAF fix
   - make GEM shrinker drm managed
   - SRIOV VF Post-migration recovery of GGTT nodes
   - W/A additions/reworks
   - Prefetch support for svm ranges
   - Don't allocate managed BO for each policy change
   - HWMON fixes for BMG
   - Create LRC BO without VM
   - PCI ID updates
   - make SLPC debugfs files optional
   - rework eviction rejection of bound external BOs
   - consolidate PAT programming logic for pre/post Xe2
   - init changes for flicker-free boot
   - Enable GuC Dynamic Inhibit Context switch

  i915:
   - drm_panic support for i915/xe
   - initial flip queue off by default for LNL/PNL
   - Wildcat Lake Display support
   - Support for DSC fractional link bpp
   - Support for simultaneous Panel Replay and Adaptive sync
   - Support for PTL+ double buffer LUT
   - initial PIPEDMC event handling
   - drm_panel_follower support
   - DPLL interface renames
   - allocate struct intel_display dynamically
   - flip queue preperation
   - abstract DRAM detection better
   - avoid GuC scheduling stalls
   - remove DG1 force probe requirement
   - fix MEI interrupt handler on RT kernels
   - use backlight control helpers for eDP
   - more shared display code refactoring

  amdgpu:
   - add userq slot to INFO ioctl
   - SR-IOV hibernation support
   - Suspend improvements
   - Backlight improvements
   - Use scaling for non-native eDP modes
   - cleaner shader updates for GC 9.x
   - Remove fence slab
   - SDMA fw checks for userq support
   - RAS updates
   - DMCUB updates
   - DP tunneling fixes
   - Display idle D3 support
   - Per queue reset improvements
   - initial smartmux support

  amdkfd:
   - enable KFD on loongarch
   - mtype fix for ext coherent system memory

  radeon:
   - CS validation additional GL extensions
   - drop console lock during suspend/resume
   - bump driver version

  msm:
   - VM BIND support
   - CI: infrastructure updates
   - UBWC single source of truth
   - decouple GPU and KMS support
   - DP: rework I/O accessors
   - DPU: SM8750 support
   - DSI: SM8750 support
   - GPU: X1-45 support and speedbin support for X1-85
   - MDSS: SM8750 support

  nova:
   - register! macro improvements
   - DMA object abstraction
   - VBIOS parser + fwsec lookup
   - sysmem flush page support
   - falcon: generic falcon boot code and HAL
   - FWSEC-FRTS: fb setup and load/execute

  ivpu:
   - Add Wildcat Lake support
   - Add turbo flag

  ast:
   - improve hardware generations implementation

  imx:
   - IMX8qxq Display Controller support

  lima:
   - Rockchip RK3528 GPU support

  nouveau:
   - fence handling cleanup

  panfrost:
   - MT8370 support
   - bo labeling
   - 64-bit register access

  qaic:
   - add RAS support

  rockchip:
   - convert inno_hdmi to a bridge

  rz-du:
   - add RZ/V2H(P) support
   - MIPI-DSI DCS support

  sitronix:
   - ST7567 support

  sun4i:
   - add H616 support

  tidss:
   - add TI AM62L support
   - AM65x OLDI bridge support

  bochs:
   - drm panic support

  vkms:
   - YUV and R* format support
   - use faux device

  vmwgfx:
   - fence improvements

  hyperv:
   - move out of simple
   - add drm_panic support"

* tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel: (1479 commits)
  drm/tidss: oldi: convert to devm_drm_bridge_alloc() API
  drm/tidss: encoder: convert to devm_drm_bridge_alloc()
  drm/amdgpu: move reset support type checks into the caller
  drm/amdgpu/sdma7: re-emit unprocessed state on ring reset
  drm/amdgpu/sdma6: re-emit unprocessed state on ring reset
  drm/amdgpu/sdma5.2: re-emit unprocessed state on ring reset
  drm/amdgpu/sdma5: re-emit unprocessed state on ring reset
  drm/amdgpu/gfx12: re-emit unprocessed state on ring reset
  drm/amdgpu/gfx11: re-emit unprocessed state on ring reset
  drm/amdgpu/gfx10: re-emit unprocessed state on ring reset
  drm/amdgpu/gfx9.4.3: re-emit unprocessed state on kcq reset
  drm/amdgpu/gfx9: re-emit unprocessed state on kcq reset
  drm/amdgpu: Add WARN_ON to the resource clear function
  drm/amd/pm: Use cached metrics data on SMUv13.0.6
  drm/amd/pm: Use cached data for min/max clocks
  gpu: nova-core: fix bounds check in PmuLookupTableEntry::new
  drm/amdgpu: Replace HQD terminology with slots naming
  drm/amdgpu: Add user queue instance count in HW IP info
  drm/amd/amdgpu: Add helper functions for isp buffers
  drm/amd/amdgpu: Initialize swnode for ISP MFD device
  ...
 2025-07-30 19:26:49 -07:00
Linus Torvalds
63eb28bb14 ARM: 
- Host driver for GICv5, the next generation interrupt controller for
   arm64, including support for interrupt routing, MSIs, interrupt
   translation and wired interrupts.
 
 - Use FEAT_GCIE_LEGACY on GICv5 systems to virtualize GICv3 VMs on
   GICv5 hardware, leveraging the legacy VGIC interface.
 
 - Userspace control of the 'nASSGIcap' GICv3 feature, allowing
   userspace to disable support for SGIs w/o an active state on hardware
   that previously advertised it unconditionally.
 
 - Map supporting endpoints with cacheable memory attributes on systems
   with FEAT_S2FWB and DIC where KVM no longer needs to perform cache
   maintenance on the address range.
 
 - Nested support for FEAT_RAS and FEAT_DoubleFault2, allowing the guest
   hypervisor to inject external aborts into an L2 VM and take traps of
   masked external aborts to the hypervisor.
 
 - Convert more system register sanitization to the config-driven
   implementation.
 
 - Fixes to the visibility of EL2 registers, namely making VGICv3 system
   registers accessible through the VGIC device instead of the ONE_REG
   vCPU ioctls.
 
 - Various cleanups and minor fixes.
 
 LoongArch:
 
 - Add stat information for in-kernel irqchip
 
 - Add tracepoints for CPUCFG and CSR emulation exits
 
 - Enhance in-kernel irqchip emulation
 
 - Various cleanups.
 
 RISC-V:
 
 - Enable ring-based dirty memory tracking
 
 - Improve perf kvm stat to report interrupt events
 
 - Delegate illegal instruction trap to VS-mode
 
 - MMU improvements related to upcoming nested virtualization
 
 s390x
 
 - Fixes
 
 x86:
 
 - Add CONFIG_KVM_IOAPIC for x86 to allow disabling support for I/O APIC,
   PIC, and PIT emulation at compile time.
 
 - Share device posted IRQ code between SVM and VMX and
   harden it against bugs and runtime errors.
 
 - Use vcpu_idx, not vcpu_id, for GA log tag/metadata, to make lookups O(1)
   instead of O(n).
 
 - For MMIO stale data mitigation, track whether or not a vCPU has access to
   (host) MMIO based on whether the page tables have MMIO pfns mapped; using
   VFIO is prone to false negatives
 
 - Rework the MSR interception code so that the SVM and VMX APIs are more or
   less identical.
 
 - Recalculate all MSR intercepts from scratch on MSR filter changes,
   instead of maintaining shadow bitmaps.
 
 - Advertise support for LKGS (Load Kernel GS base), a new instruction
   that's loosely related to FRED, but is supported and enumerated
   independently.
 
 - Fix a user-triggerable WARN that syzkaller found by setting the vCPU
   in INIT_RECEIVED state (aka wait-for-SIPI), and then putting the vCPU
   into VMX Root Mode (post-VMXON).  Trying to detect every possible path
   leading to architecturally forbidden states is hard and even risks
   breaking userspace (if it goes from valid to valid state but passes
   through invalid states), so just wait until KVM_RUN to detect that
   the vCPU state isn't allowed.
 
 - Add KVM_X86_DISABLE_EXITS_APERFMPERF to allow disabling interception of
   APERF/MPERF reads, so that a "properly" configured VM can access
   APERF/MPERF.  This has many caveats (APERF/MPERF cannot be zeroed
   on vCPU creation or saved/restored on suspend and resume, or preserved
   over thread migration let alone VM migration) but can be useful whenever
   you're interested in letting Linux guests see the effective physical CPU
   frequency in /proc/cpuinfo.
 
 - Reject KVM_SET_TSC_KHZ for vm file descriptors if vCPUs have been
   created, as there's no known use case for changing the default
   frequency for other VM types and it goes counter to the very reason
   why the ioctl was added to the vm file descriptor.  And also, there
   would be no way to make it work for confidential VMs with a "secure"
   TSC, so kill two birds with one stone.
 
 - Dynamically allocation the shadow MMU's hashed page list, and defer
   allocating the hashed list until it's actually needed (the TDP MMU
   doesn't use the list).
 
 - Extract many of KVM's helpers for accessing architectural local APIC
   state to common x86 so that they can be shared by guest-side code for
   Secure AVIC.
 
 - Various cleanups and fixes.
 
 x86 (Intel):
 
 - Preserve the host's DEBUGCTL.FREEZE_IN_SMM when running the guest.
   Failure to honor FREEZE_IN_SMM can leak host state into guests.
 
 - Explicitly check vmcs12.GUEST_DEBUGCTL on nested VM-Enter to prevent
   L1 from running L2 with features that KVM doesn't support, e.g. BTF.
 
 x86 (AMD):
 
 - WARN and reject loading kvm-amd.ko instead of panicking the kernel if the
   nested SVM MSRPM offsets tracker can't handle an MSR (which is pretty
   much a static condition and therefore should never happen, but still).
 
 - Fix a variety of flaws and bugs in the AVIC device posted IRQ code.
 
 - Inhibit AVIC if a vCPU's ID is too big (relative to what hardware
   supports) instead of rejecting vCPU creation.
 
 - Extend enable_ipiv module param support to SVM, by simply leaving
   IsRunning clear in the vCPU's physical ID table entry.
 
 - Disable IPI virtualization, via enable_ipiv, if the CPU is affected by
   erratum #1235, to allow (safely) enabling AVIC on such CPUs.
 
 - Request GA Log interrupts if and only if the target vCPU is blocking,
   i.e. only if KVM needs a notification in order to wake the vCPU.
 
 - Intercept SPEC_CTRL on AMD if the MSR shouldn't exist according to the
   vCPU's CPUID model.
 
 - Accept any SNP policy that is accepted by the firmware with respect to
   SMT and single-socket restrictions.  An incompatible policy doesn't put
   the kernel at risk in any way, so there's no reason for KVM to care.
 
 - Drop a superfluous WBINVD (on all CPUs!) when destroying a VM and
   use WBNOINVD instead of WBINVD when possible for SEV cache maintenance.
 
 - When reclaiming memory from an SEV guest, only do cache flushes on CPUs
   that have ever run a vCPU for the guest, i.e. don't flush the caches for
   CPUs that can't possibly have cache lines with dirty, encrypted data.
 
 Generic:
 
 - Rework irqbypass to track/match producers and consumers via an xarray
   instead of a linked list.  Using a linked list leads to O(n^2) insertion
   times, which is hugely problematic for use cases that create large
   numbers of VMs.  Such use cases typically don't actually use irqbypass,
   but eliminating the pointless registration is a future problem to
   solve as it likely requires new uAPI.
 
 - Track irqbypass's "token" as "struct eventfd_ctx *" instead of a "void *",
   to avoid making a simple concept unnecessarily difficult to understand.
 
 - Decouple device posted IRQs from VFIO device assignment, as binding a VM
   to a VFIO group is not a requirement for enabling device posted IRQs.
 
 - Clean up and document/comment the irqfd assignment code.
 
 - Disallow binding multiple irqfds to an eventfd with a priority waiter,
   i.e.  ensure an eventfd is bound to at most one irqfd through the entire
   host, and add a selftest to verify eventfd:irqfd bindings are globally
   unique.
 
 - Add a tracepoint for KVM_SET_MEMORY_ATTRIBUTES to help debug issues
   related to private <=> shared memory conversions.
 
 - Drop guest_memfd's .getattr() implementation as the VFS layer will call
   generic_fillattr() if inode_operations.getattr is NULL.
 
 - Fix issues with dirty ring harvesting where KVM doesn't bound the
   processing of entries in any way, which allows userspace to keep KVM
   in a tight loop indefinitely.
 
 - Kill off kvm_arch_{start,end}_assignment() and x86's associated tracking,
   now that KVM no longer uses assigned_device_count as a heuristic for
   either irqbypass usage or MDS mitigation.
 
 Selftests:
 
 - Fix a comment typo.
 
 - Verify KVM is loaded when getting any KVM module param so that attempting
   to run a selftest without kvm.ko loaded results in a SKIP message about
   KVM not being loaded/enabled (versus some random parameter not existing).
 
 - Skip tests that hit EACCES when attempting to access a file, and rpint
   a "Root required?" help message.  In most cases, the test just needs to
   be run with elevated permissions.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmiKXMgUHHBib256aW5p
 QHJlZGhhdC5jb20ACgkQv/vSX3jHroMhMQf/QDhC/CP1aGXph2whuyeD2NMqPKiU
 9KdnDNST+ftPwjg9QxZ9mTaa8zeVz/wly6XlxD9OQHy+opM1wcys3k0GZAFFEEQm
 YrThgURdzEZ3nwJZgb+m0t4wjJQtpiFIBwAf7qq6z1VrqQBEmHXJ/8QxGuqO+BNC
 j5q/X+q6KZwehKI6lgFBrrOKWFaxqhnRAYfW6rGBxRXxzTJuna37fvDpodQnNceN
 zOiq+avfriUMArTXTqOteJNKU0229HjiPSnjILLnFQ+B3akBlwNG0jk7TMaAKR6q
 IZWG1EIS9q1BAkGXaw6DE1y6d/YwtXCR5qgAIkiGwaPt5yj9Oj6kRN2Ytw==
 =j2At
 -----END PGP SIGNATURE-----

Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull kvm updates from Paolo Bonzini:
 "ARM:

   - Host driver for GICv5, the next generation interrupt controller for
     arm64, including support for interrupt routing, MSIs, interrupt
     translation and wired interrupts

   - Use FEAT_GCIE_LEGACY on GICv5 systems to virtualize GICv3 VMs on
     GICv5 hardware, leveraging the legacy VGIC interface

   - Userspace control of the 'nASSGIcap' GICv3 feature, allowing
     userspace to disable support for SGIs w/o an active state on
     hardware that previously advertised it unconditionally

   - Map supporting endpoints with cacheable memory attributes on
     systems with FEAT_S2FWB and DIC where KVM no longer needs to
     perform cache maintenance on the address range

   - Nested support for FEAT_RAS and FEAT_DoubleFault2, allowing the
     guest hypervisor to inject external aborts into an L2 VM and take
     traps of masked external aborts to the hypervisor

   - Convert more system register sanitization to the config-driven
     implementation

   - Fixes to the visibility of EL2 registers, namely making VGICv3
     system registers accessible through the VGIC device instead of the
     ONE_REG vCPU ioctls

   - Various cleanups and minor fixes

  LoongArch:

   - Add stat information for in-kernel irqchip

   - Add tracepoints for CPUCFG and CSR emulation exits

   - Enhance in-kernel irqchip emulation

   - Various cleanups

  RISC-V:

   - Enable ring-based dirty memory tracking

   - Improve perf kvm stat to report interrupt events

   - Delegate illegal instruction trap to VS-mode

   - MMU improvements related to upcoming nested virtualization

  s390x

   - Fixes

  x86:

   - Add CONFIG_KVM_IOAPIC for x86 to allow disabling support for I/O
     APIC, PIC, and PIT emulation at compile time

   - Share device posted IRQ code between SVM and VMX and harden it
     against bugs and runtime errors

   - Use vcpu_idx, not vcpu_id, for GA log tag/metadata, to make lookups
     O(1) instead of O(n)

   - For MMIO stale data mitigation, track whether or not a vCPU has
     access to (host) MMIO based on whether the page tables have MMIO
     pfns mapped; using VFIO is prone to false negatives

   - Rework the MSR interception code so that the SVM and VMX APIs are
     more or less identical

   - Recalculate all MSR intercepts from scratch on MSR filter changes,
     instead of maintaining shadow bitmaps

   - Advertise support for LKGS (Load Kernel GS base), a new instruction
     that's loosely related to FRED, but is supported and enumerated
     independently

   - Fix a user-triggerable WARN that syzkaller found by setting the
     vCPU in INIT_RECEIVED state (aka wait-for-SIPI), and then putting
     the vCPU into VMX Root Mode (post-VMXON). Trying to detect every
     possible path leading to architecturally forbidden states is hard
     and even risks breaking userspace (if it goes from valid to valid
     state but passes through invalid states), so just wait until
     KVM_RUN to detect that the vCPU state isn't allowed

   - Add KVM_X86_DISABLE_EXITS_APERFMPERF to allow disabling
     interception of APERF/MPERF reads, so that a "properly" configured
     VM can access APERF/MPERF. This has many caveats (APERF/MPERF
     cannot be zeroed on vCPU creation or saved/restored on suspend and
     resume, or preserved over thread migration let alone VM migration)
     but can be useful whenever you're interested in letting Linux
     guests see the effective physical CPU frequency in /proc/cpuinfo

   - Reject KVM_SET_TSC_KHZ for vm file descriptors if vCPUs have been
     created, as there's no known use case for changing the default
     frequency for other VM types and it goes counter to the very reason
     why the ioctl was added to the vm file descriptor. And also, there
     would be no way to make it work for confidential VMs with a
     "secure" TSC, so kill two birds with one stone

   - Dynamically allocation the shadow MMU's hashed page list, and defer
     allocating the hashed list until it's actually needed (the TDP MMU
     doesn't use the list)

   - Extract many of KVM's helpers for accessing architectural local
     APIC state to common x86 so that they can be shared by guest-side
     code for Secure AVIC

   - Various cleanups and fixes

  x86 (Intel):

   - Preserve the host's DEBUGCTL.FREEZE_IN_SMM when running the guest.
     Failure to honor FREEZE_IN_SMM can leak host state into guests

   - Explicitly check vmcs12.GUEST_DEBUGCTL on nested VM-Enter to
     prevent L1 from running L2 with features that KVM doesn't support,
     e.g. BTF

  x86 (AMD):

   - WARN and reject loading kvm-amd.ko instead of panicking the kernel
     if the nested SVM MSRPM offsets tracker can't handle an MSR (which
     is pretty much a static condition and therefore should never
     happen, but still)

   - Fix a variety of flaws and bugs in the AVIC device posted IRQ code

   - Inhibit AVIC if a vCPU's ID is too big (relative to what hardware
     supports) instead of rejecting vCPU creation

   - Extend enable_ipiv module param support to SVM, by simply leaving
     IsRunning clear in the vCPU's physical ID table entry

   - Disable IPI virtualization, via enable_ipiv, if the CPU is affected
     by erratum #1235, to allow (safely) enabling AVIC on such CPUs

   - Request GA Log interrupts if and only if the target vCPU is
     blocking, i.e. only if KVM needs a notification in order to wake
     the vCPU

   - Intercept SPEC_CTRL on AMD if the MSR shouldn't exist according to
     the vCPU's CPUID model

   - Accept any SNP policy that is accepted by the firmware with respect
     to SMT and single-socket restrictions. An incompatible policy
     doesn't put the kernel at risk in any way, so there's no reason for
     KVM to care

   - Drop a superfluous WBINVD (on all CPUs!) when destroying a VM and
     use WBNOINVD instead of WBINVD when possible for SEV cache
     maintenance

   - When reclaiming memory from an SEV guest, only do cache flushes on
     CPUs that have ever run a vCPU for the guest, i.e. don't flush the
     caches for CPUs that can't possibly have cache lines with dirty,
     encrypted data

  Generic:

   - Rework irqbypass to track/match producers and consumers via an
     xarray instead of a linked list. Using a linked list leads to
     O(n^2) insertion times, which is hugely problematic for use cases
     that create large numbers of VMs. Such use cases typically don't
     actually use irqbypass, but eliminating the pointless registration
     is a future problem to solve as it likely requires new uAPI

   - Track irqbypass's "token" as "struct eventfd_ctx *" instead of a
     "void *", to avoid making a simple concept unnecessarily difficult
     to understand

   - Decouple device posted IRQs from VFIO device assignment, as binding
     a VM to a VFIO group is not a requirement for enabling device
     posted IRQs

   - Clean up and document/comment the irqfd assignment code

   - Disallow binding multiple irqfds to an eventfd with a priority
     waiter, i.e. ensure an eventfd is bound to at most one irqfd
     through the entire host, and add a selftest to verify eventfd:irqfd
     bindings are globally unique

   - Add a tracepoint for KVM_SET_MEMORY_ATTRIBUTES to help debug issues
     related to private <=> shared memory conversions

   - Drop guest_memfd's .getattr() implementation as the VFS layer will
     call generic_fillattr() if inode_operations.getattr is NULL

   - Fix issues with dirty ring harvesting where KVM doesn't bound the
     processing of entries in any way, which allows userspace to keep
     KVM in a tight loop indefinitely

   - Kill off kvm_arch_{start,end}_assignment() and x86's associated
     tracking, now that KVM no longer uses assigned_device_count as a
     heuristic for either irqbypass usage or MDS mitigation

  Selftests:

   - Fix a comment typo

   - Verify KVM is loaded when getting any KVM module param so that
     attempting to run a selftest without kvm.ko loaded results in a
     SKIP message about KVM not being loaded/enabled (versus some random
     parameter not existing)

   - Skip tests that hit EACCES when attempting to access a file, and
     print a "Root required?" help message. In most cases, the test just
     needs to be run with elevated permissions"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (340 commits)
  Documentation: KVM: Use unordered list for pre-init VGIC registers
  RISC-V: KVM: Avoid re-acquiring memslot in kvm_riscv_gstage_map()
  RISC-V: KVM: Use find_vma_intersection() to search for intersecting VMAs
  RISC-V: perf/kvm: Add reporting of interrupt events
  RISC-V: KVM: Enable ring-based dirty memory tracking
  RISC-V: KVM: Fix inclusion of Smnpm in the guest ISA bitmap
  RISC-V: KVM: Delegate illegal instruction fault to VS mode
  RISC-V: KVM: Pass VMID as parameter to kvm_riscv_hfence_xyz() APIs
  RISC-V: KVM: Factor-out g-stage page table management
  RISC-V: KVM: Add vmid field to struct kvm_riscv_hfence
  RISC-V: KVM: Introduce struct kvm_gstage_mapping
  RISC-V: KVM: Factor-out MMU related declarations into separate headers
  RISC-V: KVM: Use ncsr_xyz() in kvm_riscv_vcpu_trap_redirect()
  RISC-V: KVM: Implement kvm_arch_flush_remote_tlbs_range()
  RISC-V: KVM: Don't flush TLB when PTE is unchanged
  RISC-V: KVM: Replace KVM_REQ_HFENCE_GVMA_VMID_ALL with KVM_REQ_TLB_FLUSH
  RISC-V: KVM: Rename and move kvm_riscv_local_tlb_sanitize()
  RISC-V: KVM: Drop the return value of kvm_riscv_vcpu_aia_init()
  RISC-V: KVM: Check kvm_riscv_vcpu_alloc_vector_context() return value
  KVM: arm64: selftests: Add FEAT_RAS EL2 registers to get-reg-list
  ...
 2025-07-30 17:14:01 -07:00
Linus Torvalds
0b29600a30 Updates for interrupt chip drivers: 
- Add support of forced affinity setting to yet offline CPUs for the
    MIPS-GIC to ensure that the affinity of per CPU interrupts can be set
    during the early bringup phase of a secondary CPU in the hotplug code
    before the CPU is set online and interrupts are enabled.\
 
  - Add support for the MIPS (RISC-V !?!?) P8700 SoC in the ACLINT_SSWI
    interrupt chip
 
  - Make the interrupt routing to RISV-V harts specification compliant so it
    supports arbitrary hart indices
 
  - Add a command line parameter and related handling to disable the generic
    RISCV IMSIC mechanism on platforms which use a trap-emulated IMSIC.
    Unfortunatly this is required because there is no mechanism available to
    discover this programatically.
 
  - Enable wakeup sources on the Renesas RZV2H driver
 
  - Convert interrupt chip drivers, which use a open coded variant of
    msi_create_parent_irq_domain() to use the new functionality
 
  - Convert interrupt chip drivers, which use the old style two level
    implementation of MSI support over to the MSI parent mechanism to
    prepare for removing at least one of the three PCI/MSI backend variants.
 
  - The usual cleanups and improvements all over the place
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmiGj60THHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoSh6D/9wY0G2dGz+EJeiDsldzB1n5jmf5I0k
 3XsI3o5j0Ma/Yy+nu9Re3fZq0+qzPFZZErxkBp5igCJbSoaIGheqOyXQDuQu/8tm
 s2t8Wx9k6er7Cywg9rU9pWKzJ6AFXFvcKOEvGG2q2+lFbJbIoGdAM93qPrOJhqeo
 a3NyhQv6kNl7xAjOVyEZmOlCZgCYotFwC0+K1TVQgGDGbwHWH3wad64gLTyyQQlK
 RvtbUBKfCBqqwLJ7Mww7Xclezjk/Hpgm/OppxBAglv5WyRd0e15u2dpdTdM9r4BC
 4wX5Old3ZgbqBQjdHGNlljthu4lO2S0PXU6j0EC8W2NiQjN+hPaKK/EPeerlAJCz
 UmxY0/E3HFNUk8ZHkiif3PGiOSvAbn0JwWi3+D6HuK1rlVTXNs07NIgUBk727Ty5
 S7r5JEuUA5s9dGta4pszxHGn/0Dqg/WvnMZGcbPNaV6POH47wNnPlO2mj14I1HLk
 SfG+deohJM34pVVq7fiqgGukLVPm6PfiJkXx90MK6l+BfE58uo7Oue9mm9pqT2dy
 b6K1gdNPRsZzG7AoAqkx3UrjQuD7maWIpDGb4VZeUW/34bthLygIDUY4OZhpdrUZ
 m33T8zv0PrmNuvnMdFt0RyoDTu8PC9rYS0XVvsIMqsMxJDE/URVGH2tCi5CVMiEg
 PbRWL56yGyT1NA==
 =5LGj
 -----END PGP SIGNATURE-----

Merge tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull interrupt chip driver updates from Thomas Gleixner:

 - Add support of forced affinity setting to yet offline CPUs for the
   MIPS-GIC to ensure that the affinity of per CPU interrupts can be set
   during the early bringup phase of a secondary CPU in the hotplug code
   before the CPU is set online and interrupts are enabled

 - Add support for the MIPS (RISC-V !?!?) P8700 SoC in the ACLINT_SSWI
   interrupt chip

 - Make the interrupt routing to RISV-V harts specification compliant so
   it supports arbitrary hart indices

 - Add a command line parameter and related handling to disable the
   generic RISCV IMSIC mechanism on platforms which use a trap-emulated
   IMSIC. Unfortunatly this is required because there is no mechanism
   available to discover this programatically.

 - Enable wakeup sources on the Renesas RZV2H driver

 - Convert interrupt chip drivers, which use a open coded variant of
   msi_create_parent_irq_domain() to use the new functionality

 - Convert interrupt chip drivers, which use the old style two level
   implementation of MSI support over to the MSI parent mechanism to
   prepare for removing at least one of the three PCI/MSI backend
   variants.

 - The usual cleanups and improvements all over the place

* tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (28 commits)
  irqchip/renesas-irqc: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  irqchip/renesas-intc-irqpin: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  irqchip/riscv-imsic: Add kernel parameter to disable IPIs
  irqchip/gic-v3: Fix GICD_CTLR register naming
  irqchip/ls-scfg-msi: Fix NULL dereference in error handling
  irqchip/ls-scfg-msi: Switch to use msi_create_parent_irq_domain()
  irqchip/armada-370-xp: Switch to msi_create_parent_irq_domain()
  irqchip/alpine-msi: Switch to msi_create_parent_irq_domain()
  irqchip/alpine-msi: Convert to __free
  irqchip/alpine-msi: Convert to lock guards
  irqchip/alpine-msi: Clean up whitespace style
  irqchip/sg2042-msi: Switch to msi_create_parent_irq_domain()
  irqchip/loongson-pch-msi.c: Switch to msi_create_parent_irq_domain()
  irqchip/imx-mu-msi: Convert to msi_create_parent_irq_domain() helper
  irqchip/riscv-imsic: Convert to msi_create_parent_irq_domain() helper
  irqchip/bcm2712-mip: Switch to msi_create_parent_irq_domain()
  irqdomain: Add device pointer to irq_domain_info and msi_domain_info
  irqchip/renesas-rzv2h: Remove unneeded includes
  irqchip/renesas-rzv2h: Enable SKIP_SET_WAKE and MASK_ON_SUSPEND
  irqchip/aslint-sswi: Resolve hart index
  ...
 2025-07-29 13:26:05 -07:00
Linus Torvalds
4df9c0a246 soc: new SoC support for 6.17 
These five newly supported chips come with both devicetree descriptions
 and the changes to wire them up to the build system for easier bisection.
 
 The chips in question are:
 
  - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
    in the product line that started with the Digital StrongARM SA1100
    based PDAs and continued with the Intel PXA2xx that dominated early
    smartphones. This one only made it only into a few products before the
    entire product line was cut in 2015.
 
  - The QiLai SoC is made by RISC-V core designer Andes Technologies
    and is in the 'Voyager' reference board in MicroATX form factor.
    It uses four in-order AX45MP cores, which is the midrange product
    from Andes.
 
  - CIX P1 is one of the few Arm chips designed for small workstations,
    and this one uses 12 Cortex-A720/A520 cores, making it also one
    of the only ARMv9.2 machines that one can but at the moment.
 
  - Axiado AX3000 is an embedded chip with relative small Cortex-A53
    CPU cores described as a "Trusted Control/Compute Unit" that can
    be used as a BMC in servers. In addition to the usual I/O, this one
    comes with 10GBit ethernet and and a 4TOPS NPU.
 
  - Sophgo SG2000 is an embedded chip that comes with both RISC-V
    and Arm cores that can run Linux. This was already supported for
    RISC-V but now it also works on Arm
 
 One more chip, the Black Sesame C1200 did not make it in tirm for the
 merge window.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiD8XAACgkQmmx57+YA
 GNm0bA//WyIvhNarlMHalDg8YY1z4Qn8yhkkF1jpc2l7zdSqu0FHYicMs4RcrcWD
 DPWpVRXxVeV20yecbkYDHDXsNDVRrkeifZcbAcjguJb1UqUAL/k5COOMMKZTxML2
 KOVjUz9vp3F8gS1vO946JFwLyj3kJz97oeBeg80ZggWaJ0JlTmwKXQqK2FobZ4QL
 Fz8QlVwoSijdgqFB93xMoSk2PZgaro0lttHCAbJPOd4GMGSbdh1r3pA0sSCwiw5C
 oeDgMMXoR0jseY8IzcA1aj0TtGLplaa77KxAxonRFM1ILJw+LsCJZQks8QC8Y6DC
 AxhxUbvfb88toXvrut9wL+436PANXbvifdw17OTZAr2hFLibyRM4zvjfNgqr/q8z
 4tqCDDsW5nfUeACUen1BIbyUk3kZEbqzlYQpuAVbGqd0X5haeHNVee3/rxi9jOVq
 NNOXlDTBa+cec26JQYj4aE0S7yqdBjKOPTeREaSId8uuKKlx/Rr6QpG/TOtaIxTp
 Jzrkf8KG5MA4hbs616MxjDkPeTyc4KR27naSeDUYWxQCx+33WzKF7bYcADou+u7x
 PelG/2Jt5r3b4qI5E0oC3jP1Hx9jY4nEGunnVcFkxqWqIk+LOFpvPD0OwplDDhQH
 35Zg4oTPb2fr37qdR6CbAdNoaQpgYvxRDAy0XZFAUR7MqMRtyf8=
 =pMk/
 -----END PGP SIGNATURE-----

Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull new SoC support from Arnd Bergmann:
 "These five newly supported chips come with both devicetree
  descriptions and the changes to wire them up to the build system for
  easier bisection.

  The chips in question are:

   - Marvell PXA1908 was the first 64-bit mobile phone chip from Marvell
     in the product line that started with the Digital StrongARM SA1100
     based PDAs and continued with the Intel PXA2xx that dominated early
     smartphones. This one only made it only into a few products before
     the entire product line was cut in 2015.

   - The QiLai SoC is made by RISC-V core designer Andes Technologies
     and is in the 'Voyager' reference board in MicroATX form factor. It
     uses four in-order AX45MP cores, which is the midrange product from
     Andes.

   - CIX P1 is one of the few Arm chips designed for small workstations,
     and this one uses 12 Cortex-A720/A520 cores, making it also one of
     the only ARMv9.2 machines that one can but at the moment.

   - Axiado AX3000 is an embedded chip with relative small Cortex-A53
     CPU cores described as a "Trusted Control/Compute Unit" that can be
     used as a BMC in servers. In addition to the usual I/O, this one
     comes with 10GBit ethernet and and a 4TOPS NPU.

   - Sophgo SG2000 is an embedded chip that comes with both RISC-V and
     Arm cores that can run Linux. This was already supported for RISC-V
     but now it also works on Arm

  One more chip, the Black Sesame C1200 did not make it in tirm for the
  merge window"

* tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits)
  arm64: defconfig: Enable rudimentary Sophgo SG2000 support
  arm64: Add SOPHGO SOC family Kconfig support
  arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
  arm64: dts: sophgo: Add Duo Module 01
  arm64: dts: sophgo: Add initial SG2000 SoC device tree
  MAINTAINERS: Add entry for Axiado
  arm64: defconfig: enable the Axiado family
  arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
  arm64: add Axiado SoC family
  dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
  dt-bindings: serial: cdns: add Axiado AX3000 UART controller
  dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
  dt-bindings: gpio: cdns: convert to YAML
  dt-bindings: arm: axiado: add AX3000 EVK compatible strings
  dt-bindings: vendor-prefixes: Add Axiado Corporation
  MAINTAINERS: Add CIX SoC maintainer entry
  arm64: dts: cix: Add sky1 base dts initial support
  dt-bindings: clock: cix: Add CIX sky1 scmi clock id
  arm64: defconfig: Enable CIX SoC
  mailbox: add CIX mailbox driver
  ...
 2025-07-29 11:17:24 -07:00
Linus Torvalds
115e74a29b soc: dt changes for 6.17 
There are a few new variants of existing chips:
 
  - mt6572 is an older mobile phone chip from mediatek that was
    extremely popular a decade ago but never got upstreamed until now.
 
  - exynos2200 is a recent high-end mobile phone chip used in a
    few Samsung phones like the Galaxy S22
 
  - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
    (R8A779H0) and used in automotive applications
 
  - Tegra264 is a new chip from NVIDIA, but support is fairly minimal
    for now, and not much information is public about it.
 
 There are five more chips in a separate branch, as those are new
 chip families that I merged along with the necessary infrastructure.
 
 New board support is not that exciting, with a total of 33 newly
 added machines here:
 
  - Evaluation platforms for the chips above, plus TI am62d2 and
    Sophgo sg2042.
 
  - Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
    plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
    imx95.
 
  - Two newly added ASPEED BMC based motherboards, and one that got
    removed
 
  - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
    msm8976 SoCs
 
  - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1
 
  - A set-top box based on Amlogic meson-gxm.
 
 Updates for existing machines are spread over all the above families.
 One notable change here is support for the RP1 I/O chip used in
 Raspberry Pi 5.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmiEp54ACgkQmmx57+YA
 GNmE+BAAvGeMkjz05rl3kSeNWCxm3WlQtrVAS3CGxXlmuB3GH4svAYO7ZFqnA1Lq
 oLKfvH9TXQgNTRlRV2bKSVCcgsvMdRukqvaNIp+9jOHKkdapgGUHr7XALZCITODp
 Ey2YPOKVi3aY2tEqUiuV09oLBFYBB5ldSuPG7SnFHNS0+IWlqqFDdQhrFXfBNf02
 Upzca6J96A6TRG7Rq+VD4127QLapNDLm1S2R+3PbEapz/v/XNxQEtigWl+E88N5L
 ju1pXu9f93w1EeQla6rN6S8RKI6Ed0kVt0I7mtwJ5KrPs9jzQwZZc5t7z+0HVyaK
 o5ldagj7nEVlth2Fc2+E67DnxB6Xe8BkTcNspnS6oWscqvyYo2WCjYOBQcTocU5m
 ej4urbS80z2bGbew9zp/ZCBJjmqOdXW/B8z9mokg1u/aktHmAiOWXnFZtws5+rBM
 It/GjP4b8MzS3JYq1oNSCUV2KpYF9hzfSg1Td7DEvyhhvSgeJyXNsc4OozZzTCv6
 bO3h1PBW6JBWVupRIAz7IrqseAsCabCMfIHduvtYWJieRzv24z1Dfv8p73v3iknN
 qpOOyGOvWdPH0u04LAbovYdJfGrR/IN04wOYGcH0uB/bufW5qCKBb9AEAvxvTaJR
 Jg1Q7ac/+TVJSFwBQJresw4WdFPHVKVwd2s382Q5hKtx3B5Cn4Y=
 =0VBL
 -----END PGP SIGNATURE-----

Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann:
 "There are a few new variants of existing chips:

   - mt6572 is an older mobile phone chip from mediatek that was
     extremely popular a decade ago but never got upstreamed until now

   - exynos2200 is a recent high-end mobile phone chip used in a few
     Samsung phones like the Galaxy S22

   - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
     (R8A779H0) and used in automotive applications

   - Tegra264 is a new chip from NVIDIA, but support is fairly minimal
     for now, and not much information is public about it

  There are five more chips in a separate branch, as those are new chip
  families that I merged along with the necessary infrastructure.

  New board support is not that exciting, with a total of 33 newly added
  machines here:

   - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
     sg2042

   - Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
     plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
     imx95

   - Two newly added ASPEED BMC based motherboards, and one that got
     removed

   - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
     msm8976 SoCs

   - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1

   - A set-top box based on Amlogic meson-gxm

  Updates for existing machines are spread over all the above families.
  One notable change here is support for the RP1 I/O chip used in
  Raspberry Pi 5"

* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
  riscv: dts: sophgo: fix mdio node name for CV180X
  riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
  dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
  riscv: dts: sophgo: add ethernet GMAC device for sg2042
  riscv: dts: sophgo: Enable ethernet device for Huashan Pi
  riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
  riscv: dts: sophgo: Add ethernet device for cv18xx
  riscv: dts: sophgo: sg2044: add pmu configuration
  riscv: dts: sophgo: sg2044: add ziccrse extension
  riscv: dts: sophgo: add zfh for sg2042
  riscv: dts: sophgo: add ziccrse for sg2042
  riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
  riscv: dts: sophgo: sg2044: add MSI device support for SG2044
  riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
  riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
  dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
  riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
  ...
 2025-07-29 11:04:52 -07:00
Frank Li
1693d18772 dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format 
Convert fsl,vf610-mscm-ir.txt to yaml format.

Additional changes:
- remove label at example dts.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250724190342.1321632-1-Frank.Li@nxp.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-07-25 14:55:12 -05:00
Frank Li
fa8c0b1c79 dt-bindings: interrupt-controller: Add fsl,icoll.yaml 
Add fsl,icoll.yaml for i.MX23 and i.MX28.

Also add a generic fallback compatible string "fsl,icoll" for legacy
devices, which have existed for over 15 years.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250724164624.1271661-1-Frank.Li@nxp.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-07-25 14:54:42 -05:00
Michal Simek
7ce3c2713b dt-bindings: interrupt-controller: Add missing Xilinx INTC binding 
Add missing description for AMD/Xilinx interrupt controller. The binding is
used by Microblaze before dt-binding even existed but never been
documented properly.

IP acts as primary interrupt controller on Microblaze systems or can be
used as secondary interrupt controller on ARM based systems like Zynq,
ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
Microblaze-V (Risc-V) systems.

Over the years IP exists in multiple variants based on attached bus as OPB,
PLB or AXI that's why generic filename is used.

Property xlnx,kind-of-intr is in hex because every bit position corresponds
to interrupt line. Controller support mixing edge or level interrupts
together and this is the property which distinguish them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/2b9d4a3a693f501d420da88b8418732ba9def877.1753354675.git.michal.simek@amd.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-07-25 14:54:16 -05:00
Ben Zong-You Xie
1f5ff8c363
dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller 
Add the DT binding documentation for Andes machine-level software
interrupt controller.

In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
second time with all interrupt sources tied to zero as the software
interrupt controller (PLICSW). PLICSW can generate machine-level software
interrupts through programming its registers.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-5-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2025-07-21 16:51:52 +02:00
Ben Zong-You Xie
6eeee4fb19
dt-bindings: interrupt-controller: add Andes QiLai PLIC 
Add a new compatible string for Andes QiLai PLIC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-4-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2025-07-21 16:51:52 +02:00
Rob Herring (Arm)
3f66b5b401 dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema 
Convert the Applied Micro X-Gene MSI controller binding to DT schema
format. MSI controllers go in interrupt-controller directory so move the
schema there.

Link: https://lore.kernel.org/r/20250710180757.2970583-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-07-14 23:05:20 -05:00
Max Shevchenko
9272cff87d
dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: add MT6572 
Add a compatible string for sysirq on the MT6572 SoC.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Max Shevchenko <wctrl@proton.me>
Link: https://lore.kernel.org/r/20250702-mt6572-v4-2-bde75b7ed445@proton.me
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 2025-07-11 10:31:42 +02:00
Lorenzo Pieralisi
7d7299bd07 dt-bindings: interrupt-controller: Add Arm GICv5 
The GICv5 interrupt controller architecture is composed of:

- one or more Interrupt Routing Service (IRS)
- zero or more Interrupt Translation Service (ITS)
- zero or more Interrupt Wire Bridge (IWB)

Describe a GICv5 implementation by specifying a top level node
corresponding to the GICv5 system component.

IRS nodes are added as GICv5 system component children.

An ITS is associated with an IRS so ITS nodes are described
as IRS children - use the hierarchy explicitly in the device
tree to define the association.

IWB nodes are described as a separate schema.

An IWB is connected to a single ITS, the connection is made explicit
through the msi-parent property and therefore is not required to be
explicit through a parent-child relationship in the device tree.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-1-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>
 2025-07-08 18:35:50 +01:00
J. Neuschäfer
98f79c729d dt-bindings: interrupt-controller: Convert fsl,mpic-msi to YAML 
As part of a larger effort to bring various PowerPC-related bindings
into the YAML world, this patch converts msi-pic.txt to YAML and moves
it into the bindings/interrupt-controller/ directory. The conversion may
necessarily be a bit hard to read because the binding is quite verbose.

Signed-off-by: J. Neuschäfer <j.ne@posteo.net>
Link: https://lore.kernel.org/r/20250611-msipic-yaml-v2-1-f2e174c48802@posteo.net
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-06-30 16:37:39 -05:00
Frank Li
de13141516 dt-bindings: interrupt-controller: Add arm,armv7m-nvic and fix #interrupt-cells 
According to existed dts arch/arm/boot/dts/armv7-m.dtsi and driver
drivers/irqchip/irq-nvic.c, compatible string should be arm,armv7m-nvic,

Fix below CHECK_DTB warning:

arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dtb: /interrupt-controller@e000e100:
    failed to match any schema with compatible: ['arm,armv7m-nvic']

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250624224630.2518776-1-Frank.Li@nxp.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-06-26 21:54:01 -05:00
Vladimir Kondratiev
ed651979bb dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi 
Add ACLINT-SSWI variant for the MIPS P8700 SoC. This CPU has a SSWI device
compliant with the RISC-V draft spec (see [1]).

CPU indexes on this platform are not continuous, instead it uses bit-fields
to encode hart,core,cluster numbers, thus the DT property
"riscv,hart-indexes" is mandatory for it.

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/all/20250612143911.3224046-4-vladimir.kondratiev@mobileye.com
Link: https://github.com/riscvarchive/riscv-aclint [1]
 2025-06-26 16:06:40 +02:00
Thomas Zimmermann
c598d5eb9f Merge drm/drm-next into drm-misc-next 
Backmerging to forward to v6.16-rc1

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
 2025-06-11 09:01:34 +02:00
Linus Torvalds
82dad69806 OpenRISC updates for 6.16 
Just a few documentation updates from the community.
 
  - Device tree documentation conversion from txt to yaml.
  - Documentation addition to help users getting started with initramfs
    on OpenRISC.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE2cRzVK74bBA6Je/xw7McLV5mJ+QFAmg8H/8ACgkQw7McLV5m
 J+R1mg//dG1Kpu/jEfJawfgzU0ck+rtrtVZ/ybYByHPTzlavvqX1UTf0+x1JXnT+
 VtoQqFrEVdefRXZqLWr34L6RpSt/6hfvOAGF7reGml5JqWRxWgrpNjnE20ej/UhY
 61vMotnM+wrpQ9ystGTnXy+ufkkMAyUzOAVKTjXkixrK+gW4Y8AQgfD/IJosS1vB
 DwUzgSeO/ZpcwLBKxTpkJi1JONdyVa4oxDNTlq9MdMcvWAyPSF4Bn9HQsjCjHRl3
 MVpm/10b59JH1RxoNqjjnaWN9YUGHUATI1umTY7BrpwTgl2g5qkGKTjC1iM2g2ys
 B0xuND89wZbcVGnbUclIslb7bcyaKD/1MD6h/bW1DZ/NUfwloWKDFRtDkHTlkxbp
 Kza+6B81sITnclZPH9WUA4zx/9+PkDLdGNr52lEzCRFqYA2KgxjEpaz7bAp9hsp9
 DT28CzyfW2rREDJu6PrLzwUr1r3yjcGdNKDXl2XoqdBGFkSbs4gnD866kpJa5Ik+
 jU+N7jjjma8BdxZQ6PD65AugEhAlzumfGf01ZJjJ2ugNvBTjGpqskGlepS7gOh4d
 B9l6YdS1ko9v87k0uqnz75w/2XVaGnOToi2vAOTxkNnBJV3YRQVRimn38w0EB8lz
 9yvr29B/GeRQuxxW1E0Qvaymjiix82v8JSzYwFDRtwF1jpmpK7Y=
 =XBzJ
 -----END PGP SIGNATURE-----

Merge tag 'for-linus' of https://github.com/openrisc/linux

Pull OpenRISC updates from Stafford Horne:
 "Just a few documentation updates from the community:

   - Device tree documentation conversion from txt to yaml

   - Documentation addition to help users getting started with initramfs
     on OpenRISC

* tag 'for-linus' of https://github.com/openrisc/linux:
  dt-bindings: interrupt-controller: Convert openrisc,ompic to DT schema
  dt-bindings: interrupt-controller: Convert opencores,or1k-pic to DT schema
  Documentation:openrisc: Add build instructions with initramfs
 2025-06-01 08:56:34 -07:00
Linus Torvalds
31848987f1 soc: sophgo devicetree updates for 6.16 
The Sophgo SG2044 SoC is their second generation server chip
 with 64 cores, following the SG2042.
 
 In addition, there are minor updates for the cv180x SoCs.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmg6KewACgkQmmx57+YA
 GNlx7Q/+JxiXqr339q5FNiLAdYhWRZSmbZ7/ya0UQi9a9EKhgv3skreSl/iHwIf3
 M2LEyw8dmJG2QhHjqBfm9eH0J/1Ctjp6G7JffFhOn1DqU9GVrQiiEw1omywhmoWC
 xFD1+rhKxxZalpm9O2m+p3xxgVjbZv3MQ13ILpwxJI91bcZuuM4HA6IDB881LtCK
 1OO2QAezMfiftEQG3PA8JzIAzkpPlyMSEZkUdNKpBSUIv92i54nQ3I/KRqbe8lp1
 duS21CJKxKjXLY91FIHb5klaYuPUr/wp/2X6cTYgyMfoxTZku7twlpYRtpRIUtwE
 XUnUcsL/xCz96QKcc/US2IkcOgG8gfAPQxWh0VZ7AQ87tttR7NR19nFt25ElTJAo
 WJoUTMOahBtE/56MMMUV+dyTAtcPTX4d9wo0lmUqt/xR/qH5LbM4oSpFsOUpDW9D
 1wdYfvWZ5JeYoEsBVfyYMzfZnMZV8IbufAkwsbfW7Gsgn8jlhyZT9gVKExZhGr0o
 GbnaKGJ5x9bChJPzuzb+LNKNBDfV+yCSWShNPZOp9TUG2c8iTFq7qkQN1iiZYE22
 REiFLTe7LyDfc7UUrt3HW2KSm6DeB9AdDnQVj9FW5GqLHBSUx1vzRnTiy9PrNn2c
 sHmlJmUdewPMroVrsaFTyO+Xn6lAooJbLH0x9xt20mKltSX6J1I=
 =rVJR
 -----END PGP SIGNATURE-----

Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull sophgo SoC devicetree updates from Arnd Bergmann:
 "The Sophgo SG2044 SoC is their second generation server chip with 64
  cores, following the SG2042.

  In addition, there are minor updates for the cv180x SoCs"

* tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
  riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
  dt-bindings: riscv: sophgo: Add SG2044 compatible string
  dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
  dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
  riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
  riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
  riscv: dts: sophgo: Move riscv cpu definition to a separate file
  riscv: dts: sophgo: Move all soc specific device into soc dtsi file
  riscv: sophgo: dts: Add spi controller for SG2042
  riscv: dts: sophgo: sg2042: add pinctrl support
 2025-05-31 08:14:37 -07:00
Linus Torvalds
ec71f661a5 soc: devicetree updates for 6.16 
There are 11 newly supported SoCs, but these are all either new
 variants of existing designs, or straig reuses of the existing
 chip in a new package:
 
  - RK3562 is a new chip based on the old Cortex-A53 core, apparently
    a low-cost version of the Cortex-A55 based RK3568/RK3566.
 
  - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
    set of on-chip peripherals.
 
  - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2 family
 
  - Amlogic S6/S7/S7D
 
  - Samsung Exynos7870 is an older chip similar to Exynos7885
 
  - WonderMedia wm8950 is a minor variation on the wm8850 chip
  - Amlogic s805y is almost idential to s805x
 
  - Allwinner A523 is similar to A527 and T527
 
  - Qualcomm MSM8926 is a variant of MSM8226
 
  - Qualcomm Snapdragon X1P42100 is related to R1E80100
 
 There are also 65 boards, including reference designs for the chips
 above, this includes
 
  - 12 new boards based on TI K3 series chips, most of them from
    Toradex
 
  - 10 devices using Rockchips RK35xx and PX30 chips
 
  - 2 phones and 2 laptops based on Qualcomm Snapdragon designs
 
  - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses
 
  - 3 Samsung Galaxy phones based on Exynos7870
 
  - 5 Allwinner based boards using a variety of ARMv8 chips
 
  - 9 32-bit machines, each based on a different SoC family
 
 Aside from the new hardware, there is the usual set of cleanups and
 newly added hardware support on existing machines, for a total of 965
 devicetree changesets.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmg5zYMACgkQmmx57+YA
 GNl1Ag/8CX35g42Gwxyr2X8wit+O2eU0axGoxM+SD1cmIcSnutZjMGu17lDGduOO
 8FC524yLE6Z9HxAUa2/cd+5fOiJcsd6Ggi5WXEFc+dHz0+P5End2DNsdIANbGcFU
 OAhCpuSB63/Mb5dcecoUULw+LIXIBffwt3FCJ0AaXFDi4RvWr0WatzQxHk/G63ci
 IoE5pAs/6W9mFvQ5R8Kt4jKISy1zF3JgqOmzy+JIsczPHlyMsbFosZRDxBWMRDza
 PenoULO/RSe3k37PGe8XCU1sja0lSCVEeJINUB11mSVGoIKRZ9Wxf57O9J81cEqF
 8HiqQ58vA/HpStPKfWZV3rXSlc3U3XGUj0lbG4iUSIOE4gMKnjWbPVuBTrr5mYsc
 cJ1pnzbZ0gbylufeS088GkCCKY/ej40aH0vLeoXEHwGh9LoWudI2xMrTJgwX5AlM
 H+X9kmP+JaC/woMmY7fr9XpMYuggraIMvDzI1j3qfohGnAUFCG7kh2IvfqkLNAEM
 o2dJkI/r/PY+fPeHBPw6EvsP6ZJhcorczwB7CxVEYJ8fqKOOunATs+aECa6HLPpv
 toh86d9rnKUrR9+hbuxacx5xxE/YT30muzh66lnV2p1rCS1RJcnzhAkFzeFNJEXf
 lpNLMauW1D3Elmk/qawKIxICazeuh4NJyQtNfdrCt/9hEpnmmeM=
 =ewvq
 -----END PGP SIGNATURE-----

Merge tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC devicetree updates from Arnd Bergmann:
 "There are 11 newly supported SoCs, but these are all either new
  variants of existing designs, or straight reuses of the existing chip
  in a new package:

   - RK3562 is a new chip based on the old Cortex-A53 core, apparently a
     low-cost version of the Cortex-A55 based RK3568/RK3566.

   - NXP i.MX94 is a minor variation of i.MX93/i.MX95 with a different
     set of on-chip peripherals.

   - Renesas RZ/V2N (R9A09G056) is a new member of the larger RZ/V2
     family

   - Amlogic S6/S7/S7D

   - Samsung Exynos7870 is an older chip similar to Exynos7885

   - WonderMedia wm8950 is a minor variation on the wm8850 chip

   - Amlogic s805y is almost idential to s805x

   - Allwinner A523 is similar to A527 and T527

   - Qualcomm MSM8926 is a variant of MSM8226

   - Qualcomm Snapdragon X1P42100 is related to R1E80100

  There are also 65 boards, including reference designs for the chips
  above, this includes

   - 12 new boards based on TI K3 series chips, most of them from
     Toradex

   - 10 devices using Rockchips RK35xx and PX30 chips

   - 2 phones and 2 laptops based on Qualcomm Snapdragon designs

   - 10 NXP i.MX8/i.MX9 boards, mostly for embedded/industrial uses

   - 3 Samsung Galaxy phones based on Exynos7870

   - 5 Allwinner based boards using a variety of ARMv8 chips

   - 9 32-bit machines, each based on a different SoC family

  Aside from the new hardware, there is the usual set of cleanups and
  newly added hardware support on existing machines, for a total of 965
  devicetree changesets"

* tag 'soc-dt-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (956 commits)
  MAINTAINERS, mailmap: update Sven Peter's email address
  arm64: dts: renesas: rzg3e-smarc-som: Reduce I2C2 clock frequency
  arm64: dts: nuvoton: Add pinctrl
  ARM: dts: samsung: sp5v210-aries: Align wifi node name with bindings
  arm64: dts: blaize-blzp1600: Enable GPIO support
  dt-bindings: clock: socfpga: convert to yaml
  arm64: dts: rockchip: move rk3562 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3562 pcie unit addresses
  arm64: dts: rockchip: move rk3528 pinctrl node outside the soc node
  arm64: dts: rockchip: remove a double-empty line from rk3576 core dtsi
  arm64: dts: rockchip: move rk3576 pinctrl node outside the soc node
  arm64: dts: rockchip: fix rk3576 pcie unit addresses
  arm64: dts: rockchip: Drop assigned-clock* from cpu nodes on rk3588
  arm64: dts: rockchip: Add missing SFC power-domains to rk3576
  Revert "arm64: dts: mediatek: mt8390-genio-common: Add firmware-name for scp0"
  arm64: dts: mediatek: mt8188: Address binding warnings for MDP3 nodes
  arm64: dts: mt6359: Rename RTC node to match binding expectations
  arm64: dts: mt8365-evk: Add goodix touchscreen support
  arm64: dts: mediatek: mt8188: Add missing #reset-cells property
  arm64: dts: airoha: en7581: Add PCIe nodes to EN7581 SoC evaluation board
  ...
 2025-05-31 08:08:56 -07:00
Linus Torvalds
bf373e4c78 Devicetree updates for v6.16: 
DT Bindings:
 - Convert all remaining interrupt-controller bindings to DT schema
 
 - Convert Rockchip CDN-DP and Freescale TCON, M4IF, TigerP, LDB, PPC
   PMC, imx-drm, and ftm-quaddec to DT schema
 
 - Add bindings for fsl,vf610-pit, fsl,ls1021a-wdt, sgx,vz89te,
   maxim,max30208, ti,lp8864, and fairphone,fp5-sndcard
 
 - Add top-level constraints for renesas,vsp1 and renesas,fcp
 
 - Add missing constraint in amlogic,pinctrl-a4 'group' nodes
 
 - Adjust the allowed properties for dwc3-xilinx, sony,imx219,
   pci-iommu, and renesas,dsi
 
 - Add EcoNet vendor prefix
 
 - Fix the reserved-memory.yaml in fsl,qman-fqd
 
 - Drop obsolete numa.txt and cpu-topology.txt which are schemas in
   dtschema now
 
 - Drop Renesas RZ/N1S bindings
 
 - Ensure Arm cpu nodes don't allow undocumented properties. Add all
   the properties which are in use and undocumented. Drop the Mediatek
   cpufreq binding which is not a binding, but just what DT properties
   the driver uses.
 
 - Add compatibles for Renesas RZ/G3E and RZ/V2N Mali Bifrost GPU
 
 - Update documentation on defining child nodes with separate schemas
 
 - Add bindings to PSCI MAINTAINERS entry
 
 DT core:
 - Add new functions to simplify driver handling of 'memory-region'
   properties. Users to be added next cycle.
 
 - Simplify of_dma_set_restricted_buffer() to use of_for_each_phandle()
 
 - Add missing unlock on error in unittest_data_add()
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEktVUI4SxYhzZyEuo+vtdtY28YcMFAmg3L7IACgkQ+vtdtY28
 YcPHew//dSH7WHwx+AwQag8svrBZbx+GrGqZlyGEGJYmF2o9TJ8d7tDCS5oPGNoV
 TObns4F1DQuX7YVrke5tYIiFMyWUmu+f8CSHg9a4Ifo+Gf5QqEhzxe1CfW6Y7VZv
 EIRrlCcW8VpTBuphsJMp6TLYof/mSBj4Ma1fRgp0H3CF0h1I5bM07jMCol+7fwT9
 0ZMEOiFOFx0HeOBVCmPvfETX1+gflnlTD+aULJwYky2Tzj6FLLWNTf94ca2iMjCd
 A4g9lJTaasRukL1RiHYoQYECgh57f3VMPRxI5wNPPVF7r3cHL7pjGzEt2vOkFDWC
 xNkIsNPrCu14He17vrh6XrNn1KMIOkLtE9yCcysE2OgdlOXfdfN6Ryz4gm1BPaFo
 ZDNZgs840r3gcQXjvCnSMq/Wxnwrka+x5vVT9VbDTV+1NWgFTpQZXqfiukxnuATa
 K0X8hW7pWatNhmT11rIfcp7WUIs0bpJ+J03ptzmYsvH4qyZpzpMZvbBoAZ9RA+E1
 dEFr7ISxhC4LlzjafqluUtBdaxKEAk8alzA9Z/OTKxDB+IiFTqztqIP3wSSApyhw
 GBdRy8iC1zU7/TbdmAVDtrT1+xvqH5On1DsjU8y96O/2dR9OKT/6Tv1ozPkcssDV
 EIeAZycS+6cFeusRxySMrOeGFQ0LiU2Qj/e9ugm07g+HMgY5jbI=
 =gMwN
 -----END PGP SIGNATURE-----

Merge tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT Bindings:

   - Convert all remaining interrupt-controller bindings to DT schema

   - Convert Rockchip CDN-DP and Freescale TCON, M4IF, TigerP, LDB, PPC
     PMC, imx-drm, and ftm-quaddec to DT schema

   - Add bindings for fsl,vf610-pit, fsl,ls1021a-wdt, sgx,vz89te,
     maxim,max30208, ti,lp8864, and fairphone,fp5-sndcard

   - Add top-level constraints for renesas,vsp1 and renesas,fcp

   - Add missing constraint in amlogic,pinctrl-a4 'group' nodes

   - Adjust the allowed properties for dwc3-xilinx, sony,imx219,
     pci-iommu, and renesas,dsi

   - Add EcoNet vendor prefix

   - Fix the reserved-memory.yaml in fsl,qman-fqd

   - Drop obsolete numa.txt and cpu-topology.txt which are schemas in
     dtschema now

   - Drop Renesas RZ/N1S bindings

   - Ensure Arm cpu nodes don't allow undocumented properties. Add all
     the properties which are in use and undocumented. Drop the Mediatek
     cpufreq binding which is not a binding, but just what DT properties
     the driver uses.

   - Add compatibles for Renesas RZ/G3E and RZ/V2N Mali Bifrost GPU

   - Update documentation on defining child nodes with separate schemas

   - Add bindings to PSCI MAINTAINERS entry

  DT core:

   - Add new functions to simplify driver handling of 'memory-region'
     properties. Users to be added next cycle.

   - Simplify of_dma_set_restricted_buffer() to use
     of_for_each_phandle()

   - Add missing unlock on error in unittest_data_add()"

* tag 'devicetree-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (87 commits)
  dt-bindings: timer: Add fsl,vf610-pit.yaml
  dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E SoC
  ASoC: dt-bindings: qcom,sm8250: Add Fairphone 5 sound card
  dt-bindings: arm/cpus: Allow 2 power-domains entries
  dt-bindings: usb: dwc3-xilinx: allow dma-coherent
  media: dt-bindings: sony,imx219: Allow props from video-interface-devices
  dt-bindings: soundwire: qcom: Document v2.1.0 version of IP block
  dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1021a-wdt
  dt-bindings: pinctrl: amlogic,pinctrl-a4: Add missing constraint on allowed 'group' node properties
  dt-bindings: display: rockchip: Convert cdn-dp-rockchip.txt to yaml
  dt-bindings: display: bridge: renesas,dsi: allow properties from dsi-controller
  dt-bindings: trivial-devices: Add VZ89TE to trivial
  media: dt-bindings: renesas,vsp1: add top-level constraints
  media: dt-bindings: renesas,fcp: add top-level constraints
  dt-bindings: trivial-devices: Add Maxim max30208
  dt-bindings: soc: fsl,qman-fqd: Fix reserved-memory.yaml reference
  dt-bindings: interrupt-controller: Convert ti,omap-intc-irq to DT schema
  dt-bindings: interrupt-controller: Convert ti,omap4-wugen-mpu to DT schema
  dt-bindings: interrupt-controller: Convert ti,keystone-irq to DT schema
  dt-bindings: interrupt-controller: Convert technologic,ts4800-irqc to DT schema
  ...
 2025-05-29 08:22:07 -07:00
Linus Torvalds
c0f182c979 Update for interrupt chip drivers: 
- Convert the generic interrupt chip to lock guards to remove copy &
     pasta boilerplate code and gotos.
 
   - A new driver fot the interrupt controller in the EcoNet EN751221 MIPS SoC.
 
   - Extend the SG2042-MSI driver to support the new SG2044 SoC
 
   - Updates and cleanups for the (ancient) VT8500 driver
 
   - Improve the scalability of the ARM GICV4.1 ITS driver by utilizing node
     local copies a VM's interrupt translation table when possible. This
     results in a 12% reduction of VM IPI latency in certain workloads.
 
   - The usual cleanups and improvements all over the place
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmgzfSwTHHRnbHhAbGlu
 dXRyb25peC5kZQAKCRCmGPVMDXSYoc4lD/0U24B8okpp2PxVVZOtNzWgl7kcAQSJ
 2U834ep1DhqJPNW0JjT+5Lb55NfAEN/uCuirjLZDsKYNNel4LXhAY951BCJMytYX
 ebH/J7wGjEphRogxn9QTGGC/mguThwFnOiqOLq4aU0Sq/oRH6Uj+P6hMod7ym9bn
 P+bZv9WWhLQQ3x/RimcauReCEDW6pW2soQV+zhN+xTxTW+R1zRcksz1x4+b/B7Vk
 ZH6KFBpZJyC34T0aXOJFhrEo01z2iZWifgmX1zz2ZgZjeUklFxtW9vGqBRS0mU2P
 9bW/qXDsSdOStyfuXbG7Q3s2z9s5Voj9okgBiA5DUD3DuplVHG/3x8do8ZHrvMoV
 k59ORecx29g0nBaVMjT13gH1XfaqI3W52qff6yksqqByh+5urhGXeYzvQ07M9ldm
 eUA8NxNad+6Gir6AcMN+COA+W8oOP17gvoSuFlUhdM/MZvPP0Gb8GkNk3o2Kfil/
 JjvcHJHCAZv6x1L7jhFhAmTUvR9ibmMJDmXJM2tIHvS1HrHNfKAIyxy00GAVg7TN
 f5Iv0+vqB7C6PHzMYIIQpZ3hrJL2GR6jdToPdAWIfr5BzugglDIRUlhEIsxhSXQn
 WMmoif5bKS8wxQRyP2F3FPv+eKYT2XVlVri3LHBkqKbkJW/sqJWHHFGIdaDrwVhX
 vZlmkT07PD3jbQ==
 =OS2H
 -----END PGP SIGNATURE-----

Merge tag 'irq-drivers-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq controller updates from Thomas Gleixner:
 "Update for interrupt chip drivers:

   - Convert the generic interrupt chip to lock guards to remove copy &
     pasta boilerplate code and gotos.

   - A new driver fot the interrupt controller in the EcoNet EN751221
     MIPS SoC.

   - Extend the SG2042-MSI driver to support the new SG2044 SoC

   - Updates and cleanups for the (ancient) VT8500 driver

   - Improve the scalability of the ARM GICV4.1 ITS driver by utilizing
     node local copies a VM's interrupt translation table when possible.
     This results in a 12% reduction of VM IPI latency in certain
     workloads.

   - The usual cleanups and improvements all over the place"

* tag 'irq-drivers-2025-05-25' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits)
  irqchip/irq-pruss-intc: Simplify chained interrupt handler setup
  irqchip/gic-v4.1: Use local 4_1 ITS to generate VSGI
  irqchip/econet-en751221: Switch to of_fwnode_handle()
  irqchip/irq-vt8500: Switch to irq_domain_create_*()
  irqchip/econet-en751221: Switch to irq_domain_create_linear()
  irqchip/irq-vt8500: Use fewer global variables and add error handling
  irqchip/irq-vt8500: Use a dedicated chained handler function
  irqchip/irq-vt8500: Don't require 8 interrupts from a chained controller
  irqchip/irq-vt8500: Drop redundant copy of the device node pointer
  irqchip/irq-vt8500: Split up ack/mask functions
  irqchip/sg2042-msi: Fix wrong type cast in sg2044_msi_irq_ack()
  irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller
  irqchip/sg2042-msi: Introduce configurable chipinfo for SG2042
  irqchip/sg2042-msi: Rename functions and data structures to be SG2042 agnostic
  dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller
  genirq/generic-chip: Fix incorrect lock guard conversions
  genirq/generic-chip: Remove unused lock wrappers
  irqchip: Convert generic irqchip locking to guards
  gpio: mvebu: Convert generic irqchip locking to guard()
  ARM: orion/gpio:: Convert generic irqchip locking to guard()
  ...
 2025-05-27 08:00:46 -07:00
Inochi Amaoto
beb2072860 dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC 
The SG2044 implement a standard T-HEAD C900 PLIC, which is
already supported by the kernel.

Add compatible string for Sophgo SG2044 plic.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250413223507.46480-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
 2025-05-19 06:23:26 +08:00
Inochi Amaoto
bced6beb16 dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi 
As SG2044 also implements an enhanced ACLINT as SG2042, add necessary
compatible string for SG2044 SoC.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250413223507.46480-4-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
 2025-05-19 06:23:26 +08:00
Liu Ying
57e464a30d dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller 
i.MX8qxp Display Controller has a built-in interrupt controller to support
Enable/Status/Preset/Clear interrupt bit.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414035028.1561475-8-victor.liu@nxp.com
 2025-05-14 15:08:32 +08:00
Rob Herring (Arm)
896633412d dt-bindings: interrupt-controller: Convert ti,omap-intc-irq to DT schema 
Convert the TI OMAP2/3 interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.

"ti,intc-size" property isn't actually used with "ti,omap2-intc", so the
2 bindings can be combined.

Link: https://lore.kernel.org/r/20250505144917.1294150-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:06 -05:00
Rob Herring (Arm)
6248d8ccc1 dt-bindings: interrupt-controller: Convert ti,omap4-wugen-mpu to DT schema 
Convert the TI Wakeup Generator interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.

Link: https://lore.kernel.org/r/20250505144913.1293967-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:06 -05:00
Rob Herring (Arm)
94555704be dt-bindings: interrupt-controller: Convert ti,keystone-irq to DT schema 
Convert the TI Keystone 2 interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144908.1293785-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:06 -05:00
Rob Herring (Arm)
dd0cea00d8 dt-bindings: interrupt-controller: Convert technologic,ts4800-irqc to DT schema 
Convert the TS-4800 FPGA interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144856.1293370-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:06 -05:00
Rob Herring (Arm)
c67d52fa7a dt-bindings: interrupt-controller: Convert st,spear3xx-shirq to DT schema 
Convert the SPEAr3xx Shared interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.

Link: https://lore.kernel.org/r/20250505144851.1293180-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:06 -05:00
Rob Herring (Arm)
9665ca7a7c dt-bindings: interrupt-controller: Convert snps,dw-apb-ictl to DT schema 
Convert the Synopsys DW-APB interrupt controller binding to schema
format. It's a straight-forward conversion of the typical interrupt
controller.

Link: https://lore.kernel.org/r/20250505144842.1292840-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:05 -05:00
Rob Herring (Arm)
f7c3cf504d dt-bindings: interrupt-controller: Convert snps,archs-intc to DT schema 
Convert the ARC-HS incore interrupt controller binding to schema format.
It's a straight-forward conversion of the typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144834.1292666-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:05 -05:00
Rob Herring (Arm)
76f75212f8 dt-bindings: interrupt-controller: Convert snps,archs-idu-intc to DT schema 
Convert the ARC-HS Interrupt Distribution Unit interrupt controller
binding to schema format. It's a straight-forward conversion of the
typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144830.1292495-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:05 -05:00
Rob Herring (Arm)
66276d212f dt-bindings: interrupt-controller: Convert snps,arc700-intc to DT schema 
Convert the Arc Core interrupt controller binding to schema format. It's
a straight-forward conversion of the typical interrupt controller.

Link: https://lore.kernel.org/r/20250505144826.1292329-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-05-13 16:20:05 -05:00