The commit 616effc0272b5 ("arm64: dts: imx8: Fix lpuart DMA channel
order") swap uart rx and tx channel at common imx8-ss-dma.dtsi. But miss
update imx8qm-ss-dma.dtsi.
The commit 5a8e9b022e569 ("arm64: dts: imx8qm-ss-dma: Pass lpuart
dma-names") just simple add dma-names as binding doc requirement.
Correct lpuart0 - lpuart3 dma rx and tx channels, and use defines for
the FSL_EDMA_RX flag.
Fixes: 5a8e9b022e56 ("arm64: dts: imx8qm-ss-dma: Pass lpuart dma-names")
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add edma error interrupt for i.MX8QM, i.MX8QXP and i.MX8DXL.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is no adma pwm on iMX8QM, so remove it from the DT. When enabled,
this cause warnings on resource partition ownership check by U-Boot
that receives messages from SCU firmware saying that these resources are
not owned:
Booting using the fdt blob at 0x9d400000
Loading Device Tree to 00000000fd622000, end 00000000fd66efff ... OK
Disable pwm@5a190000 rsrc 188 not owned
Disable clock-controller@5a590000 rsrc 188 not owned
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
can1_lpcg: clock-controller@5ace0000 {
... Col1 Col2
clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>,// 0 0
<&dma_ipg_clk>, // 1 4
<&dma_ipg_clk>; // 2 5
clock-indices = <IMX_LPCG_CLK_0>,
<IMX_LPCG_CLK_4>,
<IMX_LPCG_CLK_5>;
};
Col1: index, which existing dts try to get.
Col2: actual index in lpcg driver
&flexcan2 {
clocks = <&can1_lpcg 1>, <&can1_lpcg 0>;
^^ ^^
Should be:
clocks = <&can1_lpcg IMX_LPCG_CLK_4>, <&can1_lpcg IMX_LPCG_CLK_0>;
};
Arg0 is divided by 4 in lpcg driver. So flexcan get IMX_SC_PM_CLK_PER by
<&can1_lpcg 1> and <&can1_lpcg 0>. Although function work, code logic is
wrong. Fix it by using correct clock indices.
Cc: stable@vger.kernel.org
Fixes: be85831de020 ("arm64: dts: imx8qm: add can node in devicetree")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
It is eDMA1 at QM, which have the same register with eDMA3 at qxp.
The below commit fix panic problem.
commit b37e75bddc35 ("arm64: dts: imx8qm: Add imx8qm's own pm to avoid panic during startup")
This fixes the IRQ and DMA channel numbers. While QM eDMA1 technically has
32 channels, only 10 channels are likely used for I2C. The exact IRQ
numbers for the remaining channels were unclear in the reference manual.
Fixes: e4d7a330fb7a ("arm64: dts: imx8: add edma[0..3]")
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
<&pd IMX_SC_R_DMA_1_CH*> is now properly aligned with the previous line
for improved code readability.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both
the Rockchips rv1109 and Sopgho CV1812H are just minor variations of
already supported chips.
The other six new SoCs are all part of existing arm64 families, but
are somewhat more interesting:
- Samsung ExynosAutov920 is an automotive chip, and the first one
we support based on the Cortex-A78AE core with lockstep mode.
- Google gs101 (Tensor G1) is the chip used in a number of Pixel phones,
and is grouped with Samsung Exynos here since it is based on the same
SoC design, sharing most of its IP blocks with that series.
- MediaTek MT8188 is a new chip used for mid-range tablets and Chromebooks,
using two Cortex-A78 cores where the older MT8195 had four of them.
- Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range
phone SoC and the first supported chip based on Cortex-X4, Cortex-A720
and Cortex-A520.
- Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest
Laptop chip using the custom Oryon cores.
- Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on
Cortex-A76 and Cortex-A55
In terms of boards, we have
- Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto
G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs.
- Multiple Rockchips mobile gaming systems (Anbernic RG351V,
Powkiddy RK2023, Powkiddy X55) along with the Sonoff iHost Smart
Home Hub and a few Rockchips SBCs
- Some ComXpress boards based on Marvell CN913x, which is the
follow-up to Armada 7xxx/8xxx.
- Six new industrial/embedded boards based on NXP i.MX8 and i.MX9
- Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer.
- Toradex Verdin AM62 Mallow carrier for TI AM62
- Huashan Pi board based on the SophGo CV1812H RISC-V chip
- Two boards based on Allwinner H616/H618
- A number of reference boards for various added SoCs from Qualcomm,
Mediatek, Google, Samsung, NXP and Spreadtrum
As usual, there are cleanups and warning fixes across all platforms as
well as added features for several of them.
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Merge tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC DT updates from Arnd Bergmann:
"There is one new SoC for each 32-bit Arm and 64-bit RISC-V, but both
the Rockchips rv1109 and Sopgho CV1812H are just minor variations of
already supported chips.
The other six new SoCs are all part of existing arm64 families, but
are somewhat more interesting:
- Samsung ExynosAutov920 is an automotive chip, and the first one we
support based on the Cortex-A78AE core with lockstep mode.
- Google gs101 (Tensor G1) is the chip used in a number of Pixel
phones, and is grouped with Samsung Exynos here since it is based
on the same SoC design, sharing most of its IP blocks with that
series.
- MediaTek MT8188 is a new chip used for mid-range tablets and
Chromebooks, using two Cortex-A78 cores where the older MT8195 had
four of them.
- Qualcomm SM8650 (Snapdragon 8 Gen 3) is their current top range
phone SoC and the first supported chip based on Cortex-X4,
Cortex-A720 and Cortex-A520.
- Qualcomm X1E80100 (Snapdragon X Elite) in turn is the latest Laptop
chip using the custom Oryon cores.
- Unisoc UMS9620 (Tanggula 7 series) is a 5G phone SoC based on
Cortex-A76 and Cortex-A55
In terms of boards, we have
- Five old Microsoft Lumia phones, the HTC One Mini 2, Motorola Moto
G 4G, and Huawei Honor 5X/GR5, all based on Snapdragon SoCs.
- Multiple Rockchips mobile gaming systems (Anbernic RG351V, Powkiddy
RK2023, Powkiddy X55) along with the Sonoff iHost Smart Home Hub
and a few Rockchips SBCs
- Some ComXpress boards based on Marvell CN913x, which is the
follow-up to Armada 7xxx/8xxx.
- Six new industrial/embedded boards based on NXP i.MX8 and i.MX9
- Mediatek MT8183 based Chromebooks from Lenovo, Asus and Acer.
- Toradex Verdin AM62 Mallow carrier for TI AM62
- Huashan Pi board based on the SophGo CV1812H RISC-V chip
- Two boards based on Allwinner H616/H618
- A number of reference boards for various added SoCs from Qualcomm,
Mediatek, Google, Samsung, NXP and Spreadtrum
As usual, there are cleanups and warning fixes across all platforms as
well as added features for several of them"
* tag 'soc-dt-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (857 commits)
ARM: dts: usr8200: Fix phy registers
arm64: dts: intel: minor whitespace cleanup around '='
arm64: dts: socfpga: agilex: drop redundant status
arm64: dts: socfpga: agilex: add unit address to soc node
arm64: dts: socfpga: agilex: move firmware out of soc node
arm64: dts: socfpga: agilex: move FPGA region out of soc node
arm64: dts: socfpga: agilex: align pin-controller name with bindings
arm64: dts: socfpga: stratix10_swvp: drop unsupported DW MSHC properties
arm64: dts: socfpga: stratix10_socdk: align NAND chip name with bindings
arm64: dts: socfpga: stratix10: add unit address to soc node
arm64: dts: socfpga: stratix10: move firmware out of soc node
arm64: dts: socfpga: stratix10: move FPGA region out of soc node
arm64: dts: socfpga: stratix10: align pincfg nodes with bindings
arm64: dts: socfpga: stratix10: add clock-names to DWC2 USB
arm64: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
ARM: dts: socfpga: align NAND controller name with bindings
ARM: dts: socfpga: drop unsupported cdns,page-size and cdns,block-size
arm64: dts: rockchip: Fix led pinctrl of lubancat 1
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on nanopc-t6
arm64: dts: rockchip: correct gpio_pwrctrl1 typo on rock-5b
...
Per fsl-lpuart.yaml, when the 'dmas' property is used 'dma-names' should
also be present.
Pass the lpuart 'dma-names' property to fix the following schema
warnings:
imx8dxl-evk.dtb: serial@5a060000: dma-names:0: 'rx' was expected
from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
imx8dxl-evk.dtb: serial@5a060000: dma-names:1: 'tx' was expected
from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
imx8dxl-evk.dtb: serial@5a060000: Unevaluated properties are not allowed ('dma-names' was unexpected)
from schema $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add CAN node for imx8qm in devicetree.
Unlike on the i.MX 8QXP where the flexcan clocks are shared between
multiple CAN instances, the i.MX 8QM has separate flexcan clock slices.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS
while it has one more instance for each of LPUART, ADC and LPI2C. And unlike
MX8QXP that flexcan clocks are shared between multiple CAN instances,
MX8QM has separate flexcan clock slice.
So we reuse the most part of common imx8-ss-dma.dtsi and add new things
based on it.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
