torvalds-linux

mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-01-11 17:10:13 +00:00

Author	SHA1	Message	Date
Linus Torvalds	623fb9912f	Pin control fixes for the v6.19 series: - Fix the mt8189 register base name order back from being fixed broken. - Add REGMAP_MMIO to the pic64gx-gpio2 to avoid build breakages. - Mark the Qualcomm lpass-lpi pin controller GPIO chip instance as sleeping to fix lock splats. - Update .mailmap with my new kernel.org address for all old mails after maintainers ran into issues with this. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmlgIUUACgkQQRCzN7AZ XXNA1RAAmNzJ+nyrY9510gT0/tcNIzToUzxPz3AVL5VLtc9i+fDjr5egfUdk/+mM 9OAaLYeXB7q8ZocmJwKb4QKcc2/jgAyiv0GwUP+lmlizVFYMniYoTRKEIPW6d34a Edb/du+cncZlqaOqeBjQWN23dFW8x9Wr8gUvMEhCKCh0eCqAWFguq/zkewWvDjQN tTqGwn+L0I8pPLHytRocqVTNJLCRHDsq3xmfmSYS1k8RuccHtzoirKcKwYNHoB0a ceJV20SJ8xUoHiiFnr2r3eZZBCpR1dV9qPgZbug4j4jYjdNu49Cb17iLIaY6SUoU ZjEypL2bFck69py/alPbjtnrT2G+M0dRY9NrPbjy4aRPvDwlKaXuQ7WCzm9QOcBj 30w0wC2+N8d14bWsFVbMUThoPhCAxpJHQoqSTMXxRKXKQPDPs9vXvOtbBUwPxfS9 KveYveddu0ZrcncOEqBgvocbxNqqU/oi4Fo2qbnM2Jyq8+MkGTkziApWtORYqMhZ NTQRD2KDUnLQnGHFJSuoRpbNyxVei3Okv1EFjZboDYoTSl5NJ7MRcgge3yVFLuqo 7O2d5jF6lO+Xoqy4CWmuN5whsrSlmFS7nLAfLz/Xd/UgBu8UedD8JPL45OnKhO5u Y28p/d8hWnfuj8pIia4Fb8yifovB92y+XGHbFjwQvXKqNlSnSog= =k9fl -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - Fix the mt8189 register base name order back from being fixed broken - Add REGMAP_MMIO to the pic64gx-gpio2 to avoid build breakages - Mark the Qualcomm lpass-lpi pin controller GPIO chip instance as sleeping to fix lock splats - Update .mailmap with my new kernel.org address for all old mails after maintainers ran into issues with this * tag 'pinctrl-v6.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: qcom: lpass-lpi: mark the GPIO controller as sleeping pinctrl: pic64gx-gpio2: Add REGMAP_MMIO dependency Update .mailmap for Linus Walleij pinctrl: mediatek: mt8189: restore previous register base name array order	2026-01-08 16:38:19 -10:00
Bartosz Golaszewski	ebc18e9854	pinctrl: qcom: lpass-lpi: mark the GPIO controller as sleeping The gpio_chip settings in this driver say the controller can't sleep but it actually uses a mutex for synchronization. This triggers the following BUG(): [ 9.233659] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:281 [ 9.233665] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 554, name: (udev-worker) [ 9.233669] preempt_count: 1, expected: 0 [ 9.233673] RCU nest depth: 0, expected: 0 [ 9.233688] Tainted: [W]=WARN [ 9.233690] Hardware name: Dell Inc. Latitude 7455/0FK7MX, BIOS 2.10.1 05/20/2025 [ 9.233694] Call trace: [ 9.233696] show_stack+0x24/0x38 (C) [ 9.233709] dump_stack_lvl+0x40/0x88 [ 9.233716] dump_stack+0x18/0x24 [ 9.233722] __might_resched+0x148/0x160 [ 9.233731] __might_sleep+0x38/0x98 [ 9.233736] mutex_lock+0x30/0xd8 [ 9.233749] lpi_config_set+0x2e8/0x3c8 [pinctrl_lpass_lpi] [ 9.233757] lpi_gpio_direction_output+0x58/0x90 [pinctrl_lpass_lpi] [ 9.233761] gpiod_direction_output_raw_commit+0x110/0x428 [ 9.233772] gpiod_direction_output_nonotify+0x234/0x358 [ 9.233779] gpiod_direction_output+0x38/0xd0 [ 9.233786] gpio_shared_proxy_direction_output+0xb8/0x2a8 [gpio_shared_proxy] [ 9.233792] gpiod_direction_output_raw_commit+0x110/0x428 [ 9.233799] gpiod_direction_output_nonotify+0x234/0x358 [ 9.233806] gpiod_configure_flags+0x2c0/0x580 [ 9.233812] gpiod_find_and_request+0x358/0x4f8 [ 9.233819] gpiod_get_index+0x7c/0x98 [ 9.233826] devm_gpiod_get+0x34/0xb0 [ 9.233829] reset_gpio_probe+0x58/0x128 [reset_gpio] [ 9.233836] auxiliary_bus_probe+0xb0/0xf0 [ 9.233845] really_probe+0x14c/0x450 [ 9.233853] __driver_probe_device+0xb0/0x188 [ 9.233858] driver_probe_device+0x4c/0x250 [ 9.233863] __driver_attach+0xf8/0x2a0 [ 9.233868] bus_for_each_dev+0xf8/0x158 [ 9.233872] driver_attach+0x30/0x48 [ 9.233876] bus_add_driver+0x158/0x2b8 [ 9.233880] driver_register+0x74/0x118 [ 9.233886] __auxiliary_driver_register+0x94/0xe8 [ 9.233893] init_module+0x34/0xfd0 [reset_gpio] [ 9.233898] do_one_initcall+0xec/0x300 [ 9.233903] do_init_module+0x64/0x260 [ 9.233910] load_module+0x16c4/0x1900 [ 9.233915] __arm64_sys_finit_module+0x24c/0x378 [ 9.233919] invoke_syscall+0x4c/0xe8 [ 9.233925] el0_svc_common+0x8c/0xf0 [ 9.233929] do_el0_svc+0x28/0x40 [ 9.233934] el0_svc+0x38/0x100 [ 9.233938] el0t_64_sync_handler+0x84/0x130 [ 9.233943] el0t_64_sync+0x17c/0x180 Mark the controller as sleeping. Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver") Cc: stable@vger.kernel.org Reported-by: Val Packett <val@packett.cool> Closes: https://lore.kernel.org/all/98c0f185-b0e0-49ea-896c-f3972dd011ca@packett.cool/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>	2026-01-01 15:40:56 +01:00
Sander Vanheule	bc277212b4	pinctrl: pic64gx-gpio2: Add REGMAP_MMIO dependency In line with other drivers depending on REGMAP_*, select the required symbol to prevent a linker error when building with COMPILE_TEST=y: ld: drivers/pinctrl/pinctrl-pic64gx-gpio2.o: in function `pic64gx_gpio2_probe': pinctrl-pic64gx-gpio2.c:315:(.text+0x198): undefined reference to `__devm_regmap_init_mmio_clk' Fixes: 38cf9d641314 ("pinctrl: add pic64gx "gpio2" pinmux driver") Signed-off-by: Sander Vanheule <sander@svanheule.net> Signed-off-by: Linus Walleij <linusw@kernel.org>	2026-01-01 15:33:27 +01:00
Linus Walleij	882ddfc6b7	Update .mailmap for Linus Walleij Developers run into bouncing emails from my old address, so add it to .mailmap. Stuff in the rest of my old mail addresses as well while we're at it. Reported-by: Andy Shevchenko <andy@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>	2025-12-31 22:07:25 +01:00
Louis-Alexis Eyraud	fa917d3d57	pinctrl: mediatek: mt8189: restore previous register base name array order In mt8189-pinctrl driver, a previous commit changed the register base name array (mt8189_pinctrl_register_base_names) entry name and order to align it with the same name and order as the "mediatek,mt8189-pinctrl" devicetree bindings. The new order (by ascending register address) now causes an issue with MT8189 pinctrl configuration. MT8189 SoC has multiple base addresses for the pin configuration registers. Several constant data structures, declaring each pin configuration, are using PIN_FIELD_BASE() macro which i_base parameter indicates for a given pin the lookup index in the base register address array of the driver internal data for the configuration register read/write accesses. But in practice, this parameter is given a hardcoded numerical value that corresponds to the expected base register entry index in mt8189_pinctrl_register_base_names array. Since this array reordering, the i_base index matching is no more correct. So, in order to avoid modifying over a thousand of PIN_FIELD_BASE() calls, restore previous mt8189_pinctrl_register_base_names entry order. Fixes: 518919276c41 ("pinctrl: mediatek: mt8189: align register base names to dt-bindings ones") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: Linus Walleij <linusw@kernel.org>	2025-12-26 18:45:11 +01:00

4 changed files with 7 additions and 2 deletions

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.mailmap

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 Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
 Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@web.de>
 Linus Lüssing <linus.luessing@c0d3.blue> <ll@simonwunderlich.de>
+Linus Walleij <linusw@kernel.org> <linus.walleij@ericsson.com>
+Linus Walleij <linusw@kernel.org> <linus.walleij@stericsson.com>
+Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
+Linus Walleij <linusw@kernel.org> <triad@df.lth.se>
 <linux-hardening@vger.kernel.org> <kernel-hardening@lists.openwall.com>
 Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
 Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>

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drivers/pinctrl/Kconfig

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 	depends on ARCH_MICROCHIP || COMPILE_TEST
 	depends on OF
 	select GENERIC_PINCONF
+	select REGMAP_MMIO
 	default y
 	help
 	  This selects the pinctrl driver for gpio2 on pic64gx.

									
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drivers/pinctrl/mediatek/pinctrl-mt8189.c
									
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					@ -1642,7 +1642,7 @@ static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = {

					};

					};

					static const char * const mt8189_pinctrl_register_base_names[] = {

					static const char * const mt8189_pinctrl_register_base_names[] = {

						"base", "lm", "rb0", "rb1", "bm0", "bm1", "bm2", "lt0", "lt1", "rt",

						"base", "bm0", "bm1", "bm2", "lm",  "lt0", "lt1", "rb0", "rb1", "rt",

					};

					};

					static const struct mtk_eint_hw mt8189_eint_hw = {

					static const struct mtk_eint_hw mt8189_eint_hw = {

									
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drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
									
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					@ -498,7 +498,7 @@ int lpi_pinctrl_probe(struct platform_device *pdev)

						pctrl->chip.base = -1;

						pctrl->chip.base = -1;

						pctrl->chip.ngpio = data->npins;

						pctrl->chip.ngpio = data->npins;

						pctrl->chip.label = dev_name(dev);

						pctrl->chip.label = dev_name(dev);

						pctrl->chip.can_sleep = false;

						pctrl->chip.can_sleep = true;

						mutex_init(&pctrl->lock);

						mutex_init(&pctrl->lock);

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drivers/pinctrl/Kconfig

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drivers/pinctrl/mediatek/pinctrl-mt8189.c

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drivers/pinctrl/qcom/pinctrl-lpass-lpi.c

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2 drivers/pinctrl/mediatek/pinctrl-mt8189.c Unescape Escape View File

2 drivers/pinctrl/qcom/pinctrl-lpass-lpi.c Unescape Escape View File

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drivers/pinctrl/Kconfig

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drivers/pinctrl/mediatek/pinctrl-mt8189.c

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drivers/pinctrl/qcom/pinctrl-lpass-lpi.c

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