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7 Commits

Author SHA1 Message Date
Linus Torvalds
7254a2b522 firewire fixes for 6.18-rc6
This includes some fixes for bugs to generate topology map, newly
 introduced in v6.18 kernel.
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Merge tag 'firewire-fixes-6.18-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394

Pull firewire fixes from Takashi Sakamoto:
 "This includes some fixes for the topology map, newly introduced in
  v6.18 kernel"

* tag 'firewire-fixes-6.18-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394:
  firewire: core: fix to update generation field in topology map
  firewire: core: Initialize topology_map.lock
2025-11-16 07:08:28 -08:00
Linus Torvalds
87751e715e - In Versalnet, handle the reporting of non-standard hw errors whose
information can come in more than one remote processor message.
 
 - Explicitly reenable ECC checking after a warm reset in Altera OCRAM as those
   registers are reset to default otherwise
 
 - Fix single-bit error injection in Altera EDAC to not inject errors directly
   in ECC RAM and thus lead to false double-bit errors due to same ECC RAM
   being in concurrent use
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Merge tag 'edac_urgent_for_v6.18_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC fixes from Borislav Petkov:

 - In Versalnet, handle the reporting of non-standard hw errors whose
   information can come in more than one remote processor message.

 - Explicitly reenable ECC checking after a warm reset in Altera OCRAM
   as those registers are reset to default otherwise

 - Fix single-bit error injection in Altera EDAC to not inject errors
   directly in ECC RAM and thus lead to false double-bit errors due to
   same ECC RAM being in concurrent use

* tag 'edac_urgent_for_v6.18_rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection
  EDAC/altera: Handle OCRAM ECC enable after warm reset
  EDAC/versalnet: Handle split messages for non-standard errors
2025-11-16 07:05:24 -08:00
Takashi Sakamoto
1107aac1ad firewire: core: fix to update generation field in topology map
The generation field of topology map is updated after initialized by zero.
The updated value of generation field is always zero, and is against
specification.

This commit fixes the bug.

Fixes: 7d138cb269db ("firewire: core: use spin lock specific to topology map")
Link: https://lore.kernel.org/r/20251114144421.415278-1-o-takashi@sakamocchi.jp
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2025-11-16 21:30:26 +09:00
Ville Syrjälä
37339122a7 firewire: core: Initialize topology_map.lock
Lockdep barfs on the new uninitialized spinlock.
Initialize it.

protip: enable lockdep (CONFIG_PROVE_LOCKING=y) when
        doing locking changes

firewire_ohci 0000:02:01.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11
INFO: trying to register non-static key.
The code is fine but needs lockdep annotation, or maybe
you didn't initialize this object before use?
turning off the locking correctness validator.
CPU: 0 UID: 0 PID: 1042 Comm: irq/17-firewire Not tainted 6.17.0-rc2-cl-bisect2-00026-g7d138cb269db #136 PREEMPT
Hardware name: Dell Inc. Latitude E5400                  /0D695C, BIOS A19 06/13/2013
Call Trace:
 <TASK>
 dump_stack_lvl+0x6d/0xa0
 register_lock_class+0x783/0x790
 ? find_held_lock+0x2b/0x80
 ? __mod_timer+0x110/0x320
 ? __mod_timer+0x110/0x320
 __lock_acquire+0x405/0x2600
 lock_acquire+0xca/0x2e0
 ? fw_core_handle_bus_reset+0x888/0xca0 [firewire_core]
 ? fw_core_handle_bus_reset+0x878/0xca0 [firewire_core]
 ? fw_core_handle_bus_reset+0x878/0xca0 [firewire_core]
 _raw_spin_lock+0x2e/0x40
 ? fw_core_handle_bus_reset+0x888/0xca0 [firewire_core]
 fw_core_handle_bus_reset+0x888/0xca0 [firewire_core]
 handle_selfid_complete_event+0x35c/0x7a0 [firewire_ohci]
 ? irq_thread+0x8d/0x280
 irq_thread_fn+0x18/0x50
 irq_thread+0x15a/0x280
 ? irq_check_status_bit+0x100/0x100
 ? lockdep_hardirqs_on+0x78/0x100
 ? irq_finalize_oneshot.part.0+0xc0/0xc0
 ? irq_forced_thread_fn+0x60/0x60
 kthread+0x114/0x200
 ? kthreads_online_cpu+0x110/0x110
 ret_from_fork+0x158/0x1e0
 ? kthreads_online_cpu+0x110/0x110
 ret_from_fork_asm+0x11/0x20
 </TASK>

Reported-by: Erhard Furtner <erhard_f@mailbox.org>
Fixes: 7d138cb269db ("firewire: core: use spin lock specific to topology map")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
2025-11-14 23:18:50 +09:00
Niravkumar L Rabara
281326be67 EDAC/altera: Use INTTEST register for Ethernet and USB SBE injection
The current single-bit error injection mechanism flips bits directly in ECC RAM
by performing write and read operations. When the ECC RAM is actively used by
the Ethernet or USB controller, this approach sometimes trigger a false
double-bit error.

Switch both Ethernet and USB EDAC devices to use the INTTEST register
(altr_edac_a10_device_inject_fops) for single-bit error injection, similar to
the existing double-bit error injection method.

Fixes: 064acbd4f4ab ("EDAC, altera: Add Stratix10 peripheral support")
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111081333.1279635-1-niravkumarlaxmidas.rabara@altera.com
2025-11-11 14:59:04 +01:00
Niravkumar L Rabara
fd3ecda38f EDAC/altera: Handle OCRAM ECC enable after warm reset
The OCRAM ECC is always enabled either by the BootROM or by the Secure Device
Manager (SDM) during a power-on reset on SoCFPGA.

However, during a warm reset, the OCRAM content is retained to preserve data,
while the control and status registers are reset to their default values. As
a result, ECC must be explicitly re-enabled after a warm reset.

Fixes: 17e47dc6db4f ("EDAC/altera: Add Stratix10 OCRAM ECC support")
Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20251111080801.1279401-1-niravkumarlaxmidas.rabara@altera.com
2025-11-11 13:48:13 +01:00
Shubhrajyoti Datta
2cf95b9baa EDAC/versalnet: Handle split messages for non-standard errors
The current code assumes that only DDR errors have split messages.  Ensure
proper logging of non-standard event errors that may be split across multiple
messages too.

  [ bp: Massage, move comment too, fix it up. ]

Fixes: d5fe2fec6c40 ("EDAC: Add a driver for the AMD Versal NET DDR controller")
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://patch.msgid.link/20251023113108.3467132-1-shubhrajyoti.datta@amd.com
2025-11-07 20:15:14 +01:00
4 changed files with 34 additions and 17 deletions

View File

@ -1184,10 +1184,22 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
if (ret)
return ret;
/* Verify OCRAM has been initialized */
/*
* Verify that OCRAM has been initialized.
* During a warm reset, OCRAM contents are retained, but the control
* and status registers are reset to their default values. Therefore,
* ECC must be explicitly re-enabled in the control register.
* Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
*/
if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
(base + ALTR_A10_ECC_INITSTAT_OFST)))
return -ENODEV;
(base + ALTR_A10_ECC_INITSTAT_OFST))) {
if (!ecc_test_bits(ALTR_A10_ECC_EN,
(base + ALTR_A10_ECC_CTRL_OFST)))
ecc_set_bits(ALTR_A10_ECC_EN,
(base + ALTR_A10_ECC_CTRL_OFST));
else
return -ENODEV;
}
/* Enable IRQ on Single Bit Error */
writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
@ -1357,7 +1369,7 @@ static const struct edac_device_prv_data a10_enetecc_data = {
.ue_set_mask = ALTR_A10_ECC_TDERRA,
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject2_fops,
.inject_fops = &altr_edac_a10_device_inject_fops,
};
#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
@ -1447,7 +1459,7 @@ static const struct edac_device_prv_data a10_usbecc_data = {
.ue_set_mask = ALTR_A10_ECC_TDERRA,
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = &altr_edac_a10_device_inject2_fops,
.inject_fops = &altr_edac_a10_device_inject_fops,
};
#endif /* CONFIG_EDAC_ALTERA_USB */

View File

@ -605,21 +605,23 @@ static int rpmsg_cb(struct rpmsg_device *rpdev, void *data,
length = result[MSG_ERR_LENGTH];
offset = result[MSG_ERR_OFFSET];
/*
* The data can come in two stretches. Construct the regs from two
* messages. The offset indicates the offset from which the data is to
* be taken.
*/
for (i = 0 ; i < length; i++) {
k = offset + i;
j = ERROR_DATA + i;
mc_priv->regs[k] = result[j];
}
if (result[TOTAL_ERR_LENGTH] > length) {
if (!mc_priv->part_len)
mc_priv->part_len = length;
else
mc_priv->part_len += length;
/*
* The data can come in 2 stretches. Construct the regs from 2
* messages the offset indicates the offset from which the data is to
* be taken
*/
for (i = 0 ; i < length; i++) {
k = offset + i;
j = ERROR_DATA + i;
mc_priv->regs[k] = result[j];
}
if (mc_priv->part_len < result[TOTAL_ERR_LENGTH])
return 0;
mc_priv->part_len = 0;
@ -705,7 +707,7 @@ static int rpmsg_cb(struct rpmsg_device *rpdev, void *data,
/* Convert to bytes */
length = result[TOTAL_ERR_LENGTH] * 4;
log_non_standard_event(sec_type, &amd_versalnet_guid, mc_priv->message,
sec_sev, (void *)&result[ERROR_DATA], length);
sec_sev, (void *)&mc_priv->regs, length);
return 0;
}

View File

@ -577,6 +577,8 @@ void fw_card_initialize(struct fw_card *card,
INIT_LIST_HEAD(&card->transactions.list);
spin_lock_init(&card->transactions.lock);
spin_lock_init(&card->topology_map.lock);
card->split_timeout.hi = DEFAULT_SPLIT_TIMEOUT / 8000;
card->split_timeout.lo = (DEFAULT_SPLIT_TIMEOUT % 8000) << 19;
card->split_timeout.cycles = DEFAULT_SPLIT_TIMEOUT;

View File

@ -441,12 +441,13 @@ static void update_topology_map(__be32 *buffer, size_t buffer_size, int root_nod
const u32 *self_ids, int self_id_count)
{
__be32 *map = buffer;
u32 next_generation = be32_to_cpu(buffer[1]) + 1;
int node_count = (root_node_id & 0x3f) + 1;
memset(map, 0, buffer_size);
*map++ = cpu_to_be32((self_id_count + 2) << 16);
*map++ = cpu_to_be32(be32_to_cpu(buffer[1]) + 1);
*map++ = cpu_to_be32(next_generation);
*map++ = cpu_to_be32((node_count << 16) | self_id_count);
while (self_id_count--)