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7 Commits
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7254a2b522
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7254a2b522 | ||
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87751e715e | ||
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1107aac1ad | ||
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37339122a7 | ||
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281326be67 | ||
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fd3ecda38f | ||
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2cf95b9baa |
@ -1184,10 +1184,22 @@ altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
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if (ret)
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return ret;
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/* Verify OCRAM has been initialized */
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/*
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* Verify that OCRAM has been initialized.
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* During a warm reset, OCRAM contents are retained, but the control
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* and status registers are reset to their default values. Therefore,
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* ECC must be explicitly re-enabled in the control register.
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* Error condition: if INITCOMPLETEA is clear and ECC_EN is already set.
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*/
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if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
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(base + ALTR_A10_ECC_INITSTAT_OFST)))
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return -ENODEV;
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(base + ALTR_A10_ECC_INITSTAT_OFST))) {
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if (!ecc_test_bits(ALTR_A10_ECC_EN,
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(base + ALTR_A10_ECC_CTRL_OFST)))
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ecc_set_bits(ALTR_A10_ECC_EN,
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(base + ALTR_A10_ECC_CTRL_OFST));
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else
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return -ENODEV;
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}
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/* Enable IRQ on Single Bit Error */
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writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
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@ -1357,7 +1369,7 @@ static const struct edac_device_prv_data a10_enetecc_data = {
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.ue_set_mask = ALTR_A10_ECC_TDERRA,
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.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
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.ecc_irq_handler = altr_edac_a10_ecc_irq,
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.inject_fops = &altr_edac_a10_device_inject2_fops,
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.inject_fops = &altr_edac_a10_device_inject_fops,
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};
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#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
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@ -1447,7 +1459,7 @@ static const struct edac_device_prv_data a10_usbecc_data = {
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.ue_set_mask = ALTR_A10_ECC_TDERRA,
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.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
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.ecc_irq_handler = altr_edac_a10_ecc_irq,
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.inject_fops = &altr_edac_a10_device_inject2_fops,
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.inject_fops = &altr_edac_a10_device_inject_fops,
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};
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#endif /* CONFIG_EDAC_ALTERA_USB */
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@ -605,21 +605,23 @@ static int rpmsg_cb(struct rpmsg_device *rpdev, void *data,
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length = result[MSG_ERR_LENGTH];
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offset = result[MSG_ERR_OFFSET];
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/*
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* The data can come in two stretches. Construct the regs from two
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* messages. The offset indicates the offset from which the data is to
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* be taken.
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*/
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for (i = 0 ; i < length; i++) {
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k = offset + i;
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j = ERROR_DATA + i;
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mc_priv->regs[k] = result[j];
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}
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if (result[TOTAL_ERR_LENGTH] > length) {
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if (!mc_priv->part_len)
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mc_priv->part_len = length;
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else
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mc_priv->part_len += length;
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/*
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* The data can come in 2 stretches. Construct the regs from 2
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* messages the offset indicates the offset from which the data is to
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* be taken
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*/
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for (i = 0 ; i < length; i++) {
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k = offset + i;
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j = ERROR_DATA + i;
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mc_priv->regs[k] = result[j];
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}
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if (mc_priv->part_len < result[TOTAL_ERR_LENGTH])
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return 0;
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mc_priv->part_len = 0;
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@ -705,7 +707,7 @@ static int rpmsg_cb(struct rpmsg_device *rpdev, void *data,
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/* Convert to bytes */
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length = result[TOTAL_ERR_LENGTH] * 4;
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log_non_standard_event(sec_type, &amd_versalnet_guid, mc_priv->message,
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sec_sev, (void *)&result[ERROR_DATA], length);
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sec_sev, (void *)&mc_priv->regs, length);
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return 0;
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}
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@ -577,6 +577,8 @@ void fw_card_initialize(struct fw_card *card,
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INIT_LIST_HEAD(&card->transactions.list);
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spin_lock_init(&card->transactions.lock);
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spin_lock_init(&card->topology_map.lock);
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card->split_timeout.hi = DEFAULT_SPLIT_TIMEOUT / 8000;
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card->split_timeout.lo = (DEFAULT_SPLIT_TIMEOUT % 8000) << 19;
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card->split_timeout.cycles = DEFAULT_SPLIT_TIMEOUT;
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@ -441,12 +441,13 @@ static void update_topology_map(__be32 *buffer, size_t buffer_size, int root_nod
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const u32 *self_ids, int self_id_count)
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{
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__be32 *map = buffer;
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u32 next_generation = be32_to_cpu(buffer[1]) + 1;
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int node_count = (root_node_id & 0x3f) + 1;
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memset(map, 0, buffer_size);
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*map++ = cpu_to_be32((self_id_count + 2) << 16);
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*map++ = cpu_to_be32(be32_to_cpu(buffer[1]) + 1);
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*map++ = cpu_to_be32(next_generation);
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*map++ = cpu_to_be32((node_count << 16) | self_id_count);
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while (self_id_count--)
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