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9f393d8e75
According to [1], the C906 vector registers are 128 bits wide. The 'thead,vlenb' property specifies the vector register length in bytes, so its value must be set to 16. [1] https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Fixes: ce1daeeba600 ("riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree") Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com> Link: https://patch.msgid.link/20251119203508.1032716-1-geomatsi@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
119 lines
3.4 KiB
Plaintext
119 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
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#define SOC_PERIPHERAL_IRQ(nr) (nr + 16)
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#include "sunxi-d1s-t113.dtsi"
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/ {
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cpus {
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timebase-frequency = <24000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "thead,c906", "riscv";
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device_type = "cpu";
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reg = <0>;
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clocks = <&ccu CLK_RISCV>;
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d-cache-block-size = <64>;
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d-cache-sets = <256>;
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d-cache-size = <32768>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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operating-points-v2 = <&opp_table_cpu>;
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm", "xtheadvector";
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thead,vlenb = <16>;
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#cooling-cells = <2>;
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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opp_table_cpu: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <900000 900000 1100000>;
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};
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opp-1080000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <900000 900000 1100000>;
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};
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};
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soc {
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interrupt-parent = <&plic>;
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riscv_wdt: watchdog@6011000 {
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compatible = "allwinner,sun20i-d1-wdt";
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reg = <0x6011000 0x20>;
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interrupts = <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&dcxo>, <&rtc CLK_OSC32K>;
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clock-names = "hosc", "losc";
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};
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plic: interrupt-controller@10000000 {
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compatible = "allwinner,sun20i-d1-plic",
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"thead,c900-plic";
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reg = <0x10000000 0x4000000>;
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interrupts-extended = <&cpu0_intc 11>,
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<&cpu0_intc 9>;
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interrupt-controller;
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riscv,ndev = <175>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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};
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};
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pmu {
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compatible = "riscv,pmu";
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riscv,event-to-mhpmcounters =
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<0x00003 0x00003 0x00000008>,
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<0x00004 0x00004 0x00000010>,
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<0x00005 0x00005 0x00000200>,
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<0x00006 0x00006 0x00000100>,
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<0x10000 0x10000 0x00004000>,
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<0x10001 0x10001 0x00008000>,
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<0x10002 0x10002 0x00010000>,
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<0x10003 0x10003 0x00020000>,
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<0x10019 0x10019 0x00000040>,
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<0x10021 0x10021 0x00000020>;
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riscv,event-to-mhpmevent =
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<0x00003 0x00000000 0x00000001>,
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<0x00004 0x00000000 0x00000002>,
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<0x00005 0x00000000 0x00000007>,
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<0x00006 0x00000000 0x00000006>,
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<0x10000 0x00000000 0x0000000c>,
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<0x10001 0x00000000 0x0000000d>,
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<0x10002 0x00000000 0x0000000e>,
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<0x10003 0x00000000 0x0000000f>,
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<0x10019 0x00000000 0x00000004>,
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<0x10021 0x00000000 0x00000003>;
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riscv,raw-event-to-mhpmcounters =
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<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
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<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
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<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
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<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
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<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
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<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
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<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
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<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
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<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
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<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
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<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
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<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
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};
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};
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