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dc85a46928
Commit 2b938e3db335 ("vfio/pci: Enable iowrite64 and ioread64 for vfio
pci") enables qword access to the PCI bar resources. However certain
devices (e.g. Intel X710) are observed with problem upon qword accesses
to the rom bar, e.g. triggering PCI aer errors.
This is triggered by Qemu which caches the rom content by simply does a
pread() of the remaining size until it gets the full contents. The other
bars would only perform operations at the same access width as their
guest drivers.
Instead of trying to identify all broken devices, universally disable
qword access to the rom bar i.e. going back to the old way which worked
reliably for years.
Reported-by: Farrah Chen <farrah.chen@intel.com>
Closes: https://bugzilla.kernel.org/show_bug.cgi?id=220740
Fixes: 2b938e3db335 ("vfio/pci: Enable iowrite64 and ioread64 for vfio pci")
Cc: stable@vger.kernel.org
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Tested-by: Farrah Chen <farrah.chen@intel.com>
Link: https://lore.kernel.org/r/20251218081650.555015-2-kevin.tian@intel.com
Signed-off-by: Alex Williamson <alex@shazbot.org>
242 lines
8.0 KiB
C
242 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Red Hat, Inc. All rights reserved.
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* Author: Alex Williamson <alex.williamson@redhat.com>
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*
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* Derived from original vfio:
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* Copyright 2010 Cisco Systems, Inc. All rights reserved.
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* Author: Tom Lyon, pugs@cisco.com
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*/
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/vfio.h>
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#include <linux/irqbypass.h>
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#include <linux/rcupdate.h>
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#include <linux/types.h>
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#include <linux/uuid.h>
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#include <linux/notifier.h>
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#ifndef VFIO_PCI_CORE_H
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#define VFIO_PCI_CORE_H
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#define VFIO_PCI_OFFSET_SHIFT 40
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#define VFIO_PCI_OFFSET_TO_INDEX(off) (off >> VFIO_PCI_OFFSET_SHIFT)
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#define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
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#define VFIO_PCI_OFFSET_MASK (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
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struct vfio_pci_core_device;
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struct vfio_pci_region;
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struct p2pdma_provider;
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struct dma_buf_phys_vec;
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struct dma_buf_attachment;
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struct vfio_pci_eventfd {
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struct eventfd_ctx *ctx;
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struct rcu_head rcu;
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};
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struct vfio_pci_regops {
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ssize_t (*rw)(struct vfio_pci_core_device *vdev, char __user *buf,
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size_t count, loff_t *ppos, bool iswrite);
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void (*release)(struct vfio_pci_core_device *vdev,
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struct vfio_pci_region *region);
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int (*mmap)(struct vfio_pci_core_device *vdev,
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struct vfio_pci_region *region,
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struct vm_area_struct *vma);
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int (*add_capability)(struct vfio_pci_core_device *vdev,
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struct vfio_pci_region *region,
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struct vfio_info_cap *caps);
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};
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struct vfio_pci_region {
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u32 type;
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u32 subtype;
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const struct vfio_pci_regops *ops;
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void *data;
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size_t size;
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u32 flags;
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};
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struct vfio_pci_device_ops {
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int (*get_dmabuf_phys)(struct vfio_pci_core_device *vdev,
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struct p2pdma_provider **provider,
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unsigned int region_index,
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struct dma_buf_phys_vec *phys_vec,
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struct vfio_region_dma_range *dma_ranges,
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size_t nr_ranges);
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};
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#if IS_ENABLED(CONFIG_VFIO_PCI_DMABUF)
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int vfio_pci_core_fill_phys_vec(struct dma_buf_phys_vec *phys_vec,
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struct vfio_region_dma_range *dma_ranges,
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size_t nr_ranges, phys_addr_t start,
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phys_addr_t len);
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int vfio_pci_core_get_dmabuf_phys(struct vfio_pci_core_device *vdev,
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struct p2pdma_provider **provider,
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unsigned int region_index,
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struct dma_buf_phys_vec *phys_vec,
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struct vfio_region_dma_range *dma_ranges,
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size_t nr_ranges);
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#else
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static inline int
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vfio_pci_core_fill_phys_vec(struct dma_buf_phys_vec *phys_vec,
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struct vfio_region_dma_range *dma_ranges,
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size_t nr_ranges, phys_addr_t start,
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phys_addr_t len)
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{
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return -EINVAL;
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}
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static inline int vfio_pci_core_get_dmabuf_phys(
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struct vfio_pci_core_device *vdev, struct p2pdma_provider **provider,
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unsigned int region_index, struct dma_buf_phys_vec *phys_vec,
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struct vfio_region_dma_range *dma_ranges, size_t nr_ranges)
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{
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return -EOPNOTSUPP;
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}
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#endif
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struct vfio_pci_core_device {
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struct vfio_device vdev;
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struct pci_dev *pdev;
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const struct vfio_pci_device_ops *pci_ops;
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void __iomem *barmap[PCI_STD_NUM_BARS];
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bool bar_mmap_supported[PCI_STD_NUM_BARS];
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u8 *pci_config_map;
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u8 *vconfig;
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struct perm_bits *msi_perm;
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spinlock_t irqlock;
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struct mutex igate;
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struct xarray ctx;
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int irq_type;
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int num_regions;
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struct vfio_pci_region *region;
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u8 msi_qmax;
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u8 msix_bar;
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u16 msix_size;
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u32 msix_offset;
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u32 rbar[7];
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bool has_dyn_msix:1;
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bool pci_2_3:1;
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bool virq_disabled:1;
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bool reset_works:1;
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bool extended_caps:1;
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bool bardirty:1;
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bool has_vga:1;
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bool needs_reset:1;
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bool nointx:1;
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bool needs_pm_restore:1;
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bool pm_intx_masked:1;
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bool pm_runtime_engaged:1;
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struct pci_saved_state *pci_saved_state;
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struct pci_saved_state *pm_save;
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int ioeventfds_nr;
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struct vfio_pci_eventfd __rcu *err_trigger;
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struct vfio_pci_eventfd __rcu *req_trigger;
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struct eventfd_ctx *pm_wake_eventfd_ctx;
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struct list_head dummy_resources_list;
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struct mutex ioeventfds_lock;
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struct list_head ioeventfds_list;
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struct vfio_pci_vf_token *vf_token;
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struct list_head sriov_pfs_item;
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struct vfio_pci_core_device *sriov_pf_core_dev;
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struct notifier_block nb;
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struct rw_semaphore memory_lock;
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struct list_head dmabufs;
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};
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enum vfio_pci_io_width {
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VFIO_PCI_IO_WIDTH_1 = 1,
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VFIO_PCI_IO_WIDTH_2 = 2,
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VFIO_PCI_IO_WIDTH_4 = 4,
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VFIO_PCI_IO_WIDTH_8 = 8,
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};
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/* Will be exported for vfio pci drivers usage */
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int vfio_pci_core_register_dev_region(struct vfio_pci_core_device *vdev,
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unsigned int type, unsigned int subtype,
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const struct vfio_pci_regops *ops,
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size_t size, u32 flags, void *data);
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void vfio_pci_core_set_params(bool nointxmask, bool is_disable_vga,
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bool is_disable_idle_d3);
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void vfio_pci_core_close_device(struct vfio_device *core_vdev);
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int vfio_pci_core_init_dev(struct vfio_device *core_vdev);
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void vfio_pci_core_release_dev(struct vfio_device *core_vdev);
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int vfio_pci_core_register_device(struct vfio_pci_core_device *vdev);
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void vfio_pci_core_unregister_device(struct vfio_pci_core_device *vdev);
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extern const struct pci_error_handlers vfio_pci_core_err_handlers;
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int vfio_pci_core_sriov_configure(struct vfio_pci_core_device *vdev,
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int nr_virtfn);
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long vfio_pci_core_ioctl(struct vfio_device *core_vdev, unsigned int cmd,
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unsigned long arg);
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int vfio_pci_core_ioctl_feature(struct vfio_device *device, u32 flags,
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void __user *arg, size_t argsz);
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int vfio_pci_ioctl_get_region_info(struct vfio_device *core_vdev,
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struct vfio_region_info *info,
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struct vfio_info_cap *caps);
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ssize_t vfio_pci_core_read(struct vfio_device *core_vdev, char __user *buf,
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size_t count, loff_t *ppos);
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ssize_t vfio_pci_core_write(struct vfio_device *core_vdev, const char __user *buf,
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size_t count, loff_t *ppos);
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vm_fault_t vfio_pci_vmf_insert_pfn(struct vfio_pci_core_device *vdev,
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struct vm_fault *vmf, unsigned long pfn,
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unsigned int order);
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int vfio_pci_core_mmap(struct vfio_device *core_vdev, struct vm_area_struct *vma);
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void vfio_pci_core_request(struct vfio_device *core_vdev, unsigned int count);
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int vfio_pci_core_match(struct vfio_device *core_vdev, char *buf);
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int vfio_pci_core_match_token_uuid(struct vfio_device *core_vdev,
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const uuid_t *uuid);
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int vfio_pci_core_enable(struct vfio_pci_core_device *vdev);
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void vfio_pci_core_disable(struct vfio_pci_core_device *vdev);
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void vfio_pci_core_finish_enable(struct vfio_pci_core_device *vdev);
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int vfio_pci_core_setup_barmap(struct vfio_pci_core_device *vdev, int bar);
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pci_ers_result_t vfio_pci_core_aer_err_detected(struct pci_dev *pdev,
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pci_channel_state_t state);
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ssize_t vfio_pci_core_do_io_rw(struct vfio_pci_core_device *vdev, bool test_mem,
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void __iomem *io, char __user *buf,
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loff_t off, size_t count, size_t x_start,
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size_t x_end, bool iswrite,
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enum vfio_pci_io_width max_width);
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bool __vfio_pci_memory_enabled(struct vfio_pci_core_device *vdev);
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bool vfio_pci_core_range_intersect_range(loff_t buf_start, size_t buf_cnt,
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loff_t reg_start, size_t reg_cnt,
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loff_t *buf_offset,
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size_t *intersect_count,
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size_t *register_offset);
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#define VFIO_IOWRITE_DECLARATION(size) \
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int vfio_pci_core_iowrite##size(struct vfio_pci_core_device *vdev, \
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bool test_mem, u##size val, void __iomem *io);
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VFIO_IOWRITE_DECLARATION(8)
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VFIO_IOWRITE_DECLARATION(16)
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VFIO_IOWRITE_DECLARATION(32)
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#ifdef iowrite64
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VFIO_IOWRITE_DECLARATION(64)
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#endif
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#define VFIO_IOREAD_DECLARATION(size) \
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int vfio_pci_core_ioread##size(struct vfio_pci_core_device *vdev, \
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bool test_mem, u##size *val, void __iomem *io);
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VFIO_IOREAD_DECLARATION(8)
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VFIO_IOREAD_DECLARATION(16)
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VFIO_IOREAD_DECLARATION(32)
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#ifdef ioread64
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VFIO_IOREAD_DECLARATION(64)
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#endif
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static inline bool is_aligned_for_order(struct vm_area_struct *vma,
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unsigned long addr,
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unsigned long pfn,
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unsigned int order)
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{
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return !(order && (addr < vma->vm_start ||
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addr + (PAGE_SIZE << order) > vma->vm_end ||
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!IS_ALIGNED(pfn, 1 << order)));
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}
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int vfio_pci_dma_buf_iommufd_map(struct dma_buf_attachment *attachment,
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struct dma_buf_phys_vec *phys);
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#endif /* VFIO_PCI_CORE_H */
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