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a0c70244e5
The current EPP, ISP and MPE schemas are largely compatible with Tegra114+, requiring only minor adjustments. Additionally, the TSEC schema for the Security engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
76 lines
1.4 KiB
YAML
76 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-epp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra Encoder Pre-Processor
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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$nodename:
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pattern: "^epp@[0-9a-f]+$"
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compatible:
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oneOf:
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- enum:
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- nvidia,tegra20-epp
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- nvidia,tegra30-epp
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- nvidia,tegra114-epp
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- nvidia,tegra124-epp
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- items:
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- const: nvidia,tegra132-epp
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- const: nvidia,tegra124-epp
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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items:
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- description: module reset
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reset-names:
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items:
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- const: epp
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iommus:
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maxItems: 1
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interconnects:
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maxItems: 4
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interconnect-names:
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maxItems: 4
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operating-points-v2: true
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power-domains:
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items:
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- description: phandle to the core power domain
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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epp@540c0000 {
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compatible = "nvidia,tegra20-epp";
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reg = <0x540c0000 0x00040000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA20_CLK_EPP>;
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resets = <&tegra_car 19>;
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reset-names = "epp";
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};
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