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754c6f539e
Add devicetree document for UFS Host Controller on AMD Versal Gen 2 SoC. This includes clocks and clock-names as mandated by UFS common bindings. Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Co-developed-by: Ajay Neeli <ajay.neeli@amd.com> Signed-off-by: Ajay Neeli <ajay.neeli@amd.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Bart Van Assche <bvanassche@acm.org> Link: https://patch.msgid.link/20251021113003.13650-2-ajay.neeli@amd.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
62 lines
1.1 KiB
YAML
62 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/amd,versal2-ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AMD Versal Gen 2 UFS Host Controller
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maintainers:
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- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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allOf:
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- $ref: ufs-common.yaml
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properties:
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compatible:
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const: amd,versal2-ufs
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: core
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: host
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- const: phy
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required:
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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ufs@f10b0000 {
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compatible = "amd,versal2-ufs";
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reg = <0xf10b0000 0x1000>;
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clocks = <&ufs_core_clk>;
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clock-names = "core";
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resets = <&scmi_reset 4>, <&scmi_reset 35>;
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reset-names = "host", "phy";
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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freq-table-hz = <0 0>;
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};
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