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203dfbda03
Add support for the power controllers found in the MediaTek MT8196 Chromebook SoC. This chip has three power controllers, two of which located in the SCP subsystems (where one can be directly controlled and the other can be controlled only through the HW Voter IP), and one located in the Multimedia HFRP subsystem, controllable only through the HW Voter IP. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
269 lines
9.3 KiB
YAML
269 lines
9.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek Power Domains Controller
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maintainers:
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- MandyJH Liu <mandyjh.liu@mediatek.com>
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- Matthias Brugger <mbrugger@suse.com>
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description: |
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Mediatek processors include support for multiple power domains which can be
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powered up/down by software based on different application scenes to save power.
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IP cores belonging to a power domain should contain a 'power-domains'
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property that is a phandle for SCPSYS node representing the domain.
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properties:
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$nodename:
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pattern: '^power-controller(@[0-9a-f]+)?$'
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compatible:
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enum:
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- mediatek,mt6735-power-controller
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- mediatek,mt6795-power-controller
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- mediatek,mt6893-power-controller
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- mediatek,mt8167-power-controller
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- mediatek,mt8173-power-controller
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- mediatek,mt8183-power-controller
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- mediatek,mt8186-power-controller
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- mediatek,mt8188-power-controller
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- mediatek,mt8192-power-controller
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- mediatek,mt8195-power-controller
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- mediatek,mt8196-hwv-hfrp-power-controller
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- mediatek,mt8196-hwv-scp-power-controller
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- mediatek,mt8196-power-controller
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- mediatek,mt8365-power-controller
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'#power-domain-cells':
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const: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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access-controllers:
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description:
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A number of phandles to external blocks to set and clear the required
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bits to enable or disable bus protection, necessary to avoid any bus
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faults while enabling or disabling a power domain.
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For example, this may hold phandles to INFRACFG and SMI.
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minItems: 1
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maxItems: 3
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/power-domain-node"
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/power-domain-node"
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/power-domain-node"
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/power-domain-node"
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patternProperties:
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"^power-domain@[0-9a-f]+$":
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$ref: "#/$defs/power-domain-node"
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unevaluatedProperties: false
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unevaluatedProperties: false
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unevaluatedProperties: false
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unevaluatedProperties: false
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unevaluatedProperties: false
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$defs:
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power-domain-node:
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type: object
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description: |
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Represents the power domains within the power controller node as documented
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in Documentation/devicetree/bindings/power/power-domain.yaml.
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properties:
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'#power-domain-cells':
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description:
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Must be 0 for nodes representing a single PM domain and 1 for nodes
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providing multiple PM domains.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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reg:
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description: |
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Power domain index. Valid values are defined in:
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"include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
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"include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain.
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"include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
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"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
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"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
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"include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
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"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
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"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
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"include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
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maxItems: 1
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clocks:
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description: |
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A number of phandles to clocks that need to be enabled during domain
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power-up sequencing.
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clock-names:
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description: |
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List of names of clocks, in order to match the power-up sequencing
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for each power domain we need to group the clocks by name. BASIC
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clocks need to be enabled before enabling the corresponding power
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domain, and should not have a '-' in their name (i.e mm, mfg, venc).
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SUSBYS clocks need to be enabled before releasing the bus protection,
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and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
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In order to follow properly the power-up sequencing, the clocks must
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be specified by order, adding first the BASIC clocks followed by the
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SUSBSYS clocks.
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domain-supply:
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description: domain regulator supply.
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mediatek,infracfg:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the device containing the INFRACFG register range.
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deprecated: true
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mediatek,infracfg-nao:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the device containing the INFRACFG-NAO register range.
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deprecated: true
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mediatek,smi:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: phandle to the device containing the SMI register range.
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deprecated: true
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required:
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- reg
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required:
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- compatible
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8183-power-controller
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- mediatek,mt8196-power-controller
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then:
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properties:
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access-controllers:
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minItems: 2
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maxItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8365-power-controller
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then:
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properties:
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access-controllers:
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minItems: 3
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maxItems: 3
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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scpsys: syscon@10006000 {
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compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
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reg = <0 0x10006000 0 0x1000>;
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spm: power-controller {
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compatible = "mediatek,mt8173-power-controller";
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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/* power domains of the SoC */
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power-domain@MT8173_POWER_DOMAIN_VDEC {
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reg = <MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mm";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_VENC {
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reg = <MT8173_POWER_DOMAIN_VENC>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_VENC_SEL>;
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clock-names = "mm", "venc";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_ISP {
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reg = <MT8173_POWER_DOMAIN_ISP>;
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clocks = <&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mm";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_MM {
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reg = <MT8173_POWER_DOMAIN_MM>;
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clocks = <&topckgen CLK_TOP_MM_SEL>;
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clock-names = "mm";
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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power-domain@MT8173_POWER_DOMAIN_VENC_LT {
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reg = <MT8173_POWER_DOMAIN_VENC_LT>;
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clocks = <&topckgen CLK_TOP_MM_SEL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "mm", "venclt";
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_AUDIO {
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reg = <MT8173_POWER_DOMAIN_AUDIO>;
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_USB {
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reg = <MT8173_POWER_DOMAIN_USB>;
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#power-domain-cells = <0>;
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};
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power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
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reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
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clocks = <&clk26m>;
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clock-names = "mfg";
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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power-domain@MT8173_POWER_DOMAIN_MFG_2D {
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reg = <MT8173_POWER_DOMAIN_MFG_2D>;
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#address-cells = <1>;
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#size-cells = <0>;
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#power-domain-cells = <1>;
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power-domain@MT8173_POWER_DOMAIN_MFG {
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reg = <MT8173_POWER_DOMAIN_MFG>;
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#power-domain-cells = <0>;
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mediatek,infracfg = <&infracfg>;
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};
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};
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};
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};
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};
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};
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