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86eecc3a9c
The DW DP TX Controller is compliant with the DisplayPort Specification Version 1.4 with the following features: * DisplayPort 1.4a * Main Link: 1/2/4 lanes * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps * AUX channel 1Mbps * Single Stream Transport(SST) * Multistream Transport (MST) * Type-C support (alternate mode) * HDCP 2.2, HDCP 1.3 * Supports up to 8/10 bits per color component * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 * Pixel clock up to 594MHz * I2S, SPDIF audio interface Add library with common helpers to make it can be shared with other SoC. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20250822063959.692098-3-andyshrk@163.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
21 lines
400 B
C
21 lines
400 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __DW_DP__
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#define __DW_DP__
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#include <linux/device.h>
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struct drm_encoder;
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struct dw_dp;
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struct dw_dp_plat_data {
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u32 max_link_rate;
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};
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struct dw_dp *dw_dp_bind(struct device *dev, struct drm_encoder *encoder,
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const struct dw_dp_plat_data *plat_data);
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#endif /* __DW_DP__ */
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