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b1c26e0595
A new header fch.h was created to store registers used by different AMD
drivers. This header was included by i2c-piix4 in
commit 624b0d5696a8 ("i2c: piix4, x86/platform: Move the SB800 PIIX4 FCH
definitions to <asm/amd/fch.h>"). To prevent compile failures on non-x86
archs i2c-piix4 was set to only compile on x86 by commit 7e173eb82ae9717
("i2c: piix4: Make CONFIG_I2C_PIIX4 dependent on CONFIG_X86").
This was not a good decision because loongarch and mips both actually
support i2c-piix4 and set it enabled in the defconfig.
Move the header to a location accessible by all architectures.
Fixes: 624b0d5696a89 ("i2c: piix4, x86/platform: Move the SB800 PIIX4 FCH definitions to <asm/amd/fch.h>")
Suggested-by: Hans de Goede <hansg@kernel.org>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Hans de Goede <hansg@kernel.org>
Link: https://lore.kernel.org/r/20250610205817.3912944-1-superm1@kernel.org
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
14 lines
349 B
C
14 lines
349 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_AMD_FCH_H_
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#define _ASM_X86_AMD_FCH_H_
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#define FCH_PM_BASE 0xFED80300
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/* Register offsets from PM base: */
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#define FCH_PM_DECODEEN 0x00
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#define FCH_PM_DECODEEN_SMBUS0SEL GENMASK(20, 19)
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#define FCH_PM_SCRATCH 0x80
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#define FCH_PM_S5_RESET_STATUS 0xC0
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#endif /* _ASM_X86_AMD_FCH_H_ */
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