Anurag Kumar Vulisha cea0f76a48 dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY ...

Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

2020-06-29 18:48:00 +05:30

..

phy-am654-serdes.h

dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoC

2019-04-17 14:13:18 +05:30

phy-lantiq-vrx200-pcie.h

dt-bindings: phy: add binding for the Lantiq VRX200 and ARX300 PCIe PHYs

2019-08-23 09:40:46 +05:30

phy-ocelot-serdes.h

dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1

2018-10-22 19:27:14 -07:00

phy-pistachio-usb.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422

2019-06-05 17:37:15 +02:00

phy-qcom-qusb2.h

…

phy.h

dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY

2020-06-29 18:48:00 +05:30