mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-01-11 17:10:13 +00:00
81f5d15c48
32BIT platforms only have 32bit CSR/IOCSR registers, 64BIT platforms have both 32bit/64bit CSR/IOCSR registers. Now there are both 32bit and 64bit CSR accessors: csr_read32()/csr_write32()/csr_xchg32(); csr_read64()/csr_write64()/csr_xchg64(); Some CSR registers (address and timer registers) are 32bit length on 32BIT platform and 64bit length on 64BIT platform. To avoid #ifdefs here and there, they need adaptive accessors, so we define and use: csr_read()/csr_write()/csr_xchg(); IOCSR doesn't have a "natural length", which means a 64bit register can be treated as two 32bit registers, so we just use two 32bit accessors to emulate a 64bit accessors. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
#include <asm/fpu.h>
|
|
#include <asm/loongson.h>
|
|
#include <asm/sections.h>
|
|
#include <asm/time.h>
|
|
#include <asm/tlbflush.h>
|
|
#include <linux/suspend.h>
|
|
|
|
static u32 saved_crmd;
|
|
static u32 saved_prmd;
|
|
static u32 saved_euen;
|
|
static u32 saved_ecfg;
|
|
static unsigned long saved_pcpu_base;
|
|
struct pt_regs saved_regs;
|
|
|
|
void save_processor_state(void)
|
|
{
|
|
save_counter();
|
|
saved_crmd = csr_read32(LOONGARCH_CSR_CRMD);
|
|
saved_prmd = csr_read32(LOONGARCH_CSR_PRMD);
|
|
saved_euen = csr_read32(LOONGARCH_CSR_EUEN);
|
|
saved_ecfg = csr_read32(LOONGARCH_CSR_ECFG);
|
|
saved_pcpu_base = csr_read(PERCPU_BASE_KS);
|
|
|
|
if (is_fpu_owner())
|
|
save_fp(current);
|
|
}
|
|
|
|
void restore_processor_state(void)
|
|
{
|
|
sync_counter();
|
|
csr_write32(saved_crmd, LOONGARCH_CSR_CRMD);
|
|
csr_write32(saved_prmd, LOONGARCH_CSR_PRMD);
|
|
csr_write32(saved_euen, LOONGARCH_CSR_EUEN);
|
|
csr_write32(saved_ecfg, LOONGARCH_CSR_ECFG);
|
|
csr_write(saved_pcpu_base, PERCPU_BASE_KS);
|
|
|
|
if (is_fpu_owner())
|
|
restore_fp(current);
|
|
}
|
|
|
|
int pfn_is_nosave(unsigned long pfn)
|
|
{
|
|
unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin));
|
|
unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end));
|
|
|
|
return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
|
|
}
|
|
|
|
extern int swsusp_asm_suspend(void);
|
|
|
|
int swsusp_arch_suspend(void)
|
|
{
|
|
enable_pci_wakeup();
|
|
return swsusp_asm_suspend();
|
|
}
|
|
|
|
extern int swsusp_asm_resume(void);
|
|
|
|
int swsusp_arch_resume(void)
|
|
{
|
|
/* Avoid TLB mismatch during and after kernel resume */
|
|
local_flush_tlb_all();
|
|
return swsusp_asm_resume();
|
|
}
|