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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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5fb2f67341
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have four SPI peripherals, each with their own clock divider, which divides PLL4 by either 24, 25, 30 or 32, similar to the SCI peripheral. The dividers feed into the usual module clocks. Add them all. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20251105104151.1489281-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
321 lines
10 KiB
C
321 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* r9a09g077 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*
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*/
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#include <linux/bitfield.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
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#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#define RZT2H_REG_BLOCK_SHIFT 11
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#define RZT2H_REG_OFFSET_MASK GENMASK(10, 0)
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#define RZT2H_REG_CONF(block, offset) (((block) << RZT2H_REG_BLOCK_SHIFT) | \
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((offset) & RZT2H_REG_OFFSET_MASK))
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#define RZT2H_REG_BLOCK(x) ((x) >> RZT2H_REG_BLOCK_SHIFT)
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#define RZT2H_REG_OFFSET(x) ((x) & RZT2H_REG_OFFSET_MASK)
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#define SCKCR RZT2H_REG_CONF(0, 0x00)
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#define SCKCR2 RZT2H_REG_CONF(1, 0x04)
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#define SCKCR3 RZT2H_REG_CONF(0, 0x08)
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#define OFFSET_MASK GENMASK(31, 20)
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#define SHIFT_MASK GENMASK(19, 12)
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#define WIDTH_MASK GENMASK(11, 8)
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#define CONF_PACK(offset, shift, width) \
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(FIELD_PREP_CONST(OFFSET_MASK, (offset)) | \
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FIELD_PREP_CONST(SHIFT_MASK, (shift)) | \
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FIELD_PREP_CONST(WIDTH_MASK, (width)))
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#define GET_SHIFT(val) FIELD_GET(SHIFT_MASK, val)
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#define GET_WIDTH(val) FIELD_GET(WIDTH_MASK, val)
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#define GET_REG_OFFSET(val) FIELD_GET(OFFSET_MASK, val)
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#define DIVCA55C0 CONF_PACK(SCKCR2, 8, 1)
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#define DIVCA55C1 CONF_PACK(SCKCR2, 9, 1)
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#define DIVCA55C2 CONF_PACK(SCKCR2, 10, 1)
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#define DIVCA55C3 CONF_PACK(SCKCR2, 11, 1)
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#define DIVCA55S CONF_PACK(SCKCR2, 12, 1)
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#define DIVSPI3ASYNC CONF_PACK(SCKCR2, 16, 2)
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#define DIVSCI5ASYNC CONF_PACK(SCKCR2, 18, 2)
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#define DIVSPI0ASYNC CONF_PACK(SCKCR3, 0, 2)
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#define DIVSPI1ASYNC CONF_PACK(SCKCR3, 2, 2)
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#define DIVSPI2ASYNC CONF_PACK(SCKCR3, 4, 2)
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#define DIVSCI0ASYNC CONF_PACK(SCKCR3, 6, 2)
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#define DIVSCI1ASYNC CONF_PACK(SCKCR3, 8, 2)
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#define DIVSCI2ASYNC CONF_PACK(SCKCR3, 10, 2)
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#define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2)
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#define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2)
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#define SEL_PLL CONF_PACK(SCKCR, 22, 1)
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enum rzt2h_clk_types {
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CLK_TYPE_RZT2H_DIV = CLK_TYPE_CUSTOM, /* Clock with divider */
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CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */
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};
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#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
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DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
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.parent = _parent, .dtable = _dtable, .flag = 0)
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#define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
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DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
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.parent_names = _parent_names, .num_parents = _num_parents, \
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.flag = 0, .mux_flags = _mux_flags)
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G077_ETCLKE,
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/* External Input Clocks */
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CLK_EXTAL,
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/* Internal Core Clocks */
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CLK_LOCO,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL2,
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CLK_PLL4,
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CLK_SEL_CLK_PLL0,
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CLK_SEL_CLK_PLL1,
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CLK_SEL_CLK_PLL2,
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CLK_SEL_CLK_PLL4,
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CLK_PLL4D1,
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CLK_SCI0ASYNC,
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CLK_SCI1ASYNC,
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CLK_SCI2ASYNC,
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CLK_SCI3ASYNC,
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CLK_SCI4ASYNC,
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CLK_SCI5ASYNC,
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CLK_SPI0ASYNC,
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CLK_SPI1ASYNC,
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CLK_SPI2ASYNC,
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CLK_SPI3ASYNC,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_1_2[] = {
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{0, 2},
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{1, 1},
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{0, 0},
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};
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static const struct clk_div_table dtable_24_25_30_32[] = {
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{0, 32},
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{1, 30},
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{2, 25},
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{3, 24},
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{0, 0},
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};
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/* Mux clock tables */
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static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
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static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
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static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
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static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
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static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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/* Internal Core Clocks */
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DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
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DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
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DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
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DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
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DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
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sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
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DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
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sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
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DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
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sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
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DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
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sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
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DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
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DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".sci2async", CLK_SCI2ASYNC, CLK_PLL4D1, DIVSCI2ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".sci3async", CLK_SCI3ASYNC, CLK_PLL4D1, DIVSCI3ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".sci4async", CLK_SCI4ASYNC, CLK_PLL4D1, DIVSCI4ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".spi0async", CLK_SPI0ASYNC, CLK_PLL4D1, DIVSPI0ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".spi1async", CLK_SPI1ASYNC, CLK_PLL4D1, DIVSPI1ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".spi2async", CLK_SPI2ASYNC, CLK_PLL4D1, DIVSPI2ASYNC,
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dtable_24_25_30_32),
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DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
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dtable_24_25_30_32),
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/* Core output clk */
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DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
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dtable_1_2),
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DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1,
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dtable_1_2),
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DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2,
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dtable_1_2),
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DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3,
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dtable_1_2),
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DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
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dtable_1_2),
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DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
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DEF_FIXED("PCLKH", R9A09G077_CLK_PCLKH, CLK_SEL_CLK_PLL1, 4, 1),
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DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
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DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
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DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1),
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DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
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DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
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DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
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DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1),
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DEF_FIXED("ETCLKB", R9A09G077_ETCLKB, CLK_SEL_CLK_PLL1, 8, 1),
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DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
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DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
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DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
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};
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static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
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DEF_MOD("sci0fck", 8, CLK_SCI0ASYNC),
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DEF_MOD("sci1fck", 9, CLK_SCI1ASYNC),
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DEF_MOD("sci2fck", 10, CLK_SCI2ASYNC),
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DEF_MOD("sci3fck", 11, CLK_SCI3ASYNC),
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DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
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DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
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DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
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DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
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DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
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DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
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DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
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DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
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DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
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DEF_MOD("tsu", 307, R9A09G077_CLK_PCLKL),
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DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
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DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
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DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),
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DEF_MOD("usb", 408, R9A09G077_CLK_PCLKAM),
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DEF_MOD("gmac1", 416, R9A09G077_CLK_PCLKAM),
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DEF_MOD("gmac2", 417, R9A09G077_CLK_PCLKAM),
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DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC),
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DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
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DEF_MOD("spi3", 602, CLK_SPI3ASYNC),
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DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),
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DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM),
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};
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static struct clk * __init
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r9a09g077_cpg_div_clk_register(struct device *dev,
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const struct cpg_core_clk *core,
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void __iomem *addr, struct cpg_mssr_pub *pub)
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{
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const struct clk *parent;
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const char *parent_name;
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struct clk_hw *clk_hw;
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parent = pub->clks[core->parent];
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if (IS_ERR(parent))
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return ERR_CAST(parent);
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parent_name = __clk_get_name(parent);
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if (core->dtable)
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clk_hw = devm_clk_hw_register_divider_table(dev, core->name,
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parent_name,
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CLK_SET_RATE_PARENT,
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addr,
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GET_SHIFT(core->conf),
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GET_WIDTH(core->conf),
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core->flag,
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core->dtable,
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&pub->rmw_lock);
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else
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clk_hw = devm_clk_hw_register_divider(dev, core->name,
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parent_name,
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CLK_SET_RATE_PARENT,
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addr,
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GET_SHIFT(core->conf),
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GET_WIDTH(core->conf),
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core->flag, &pub->rmw_lock);
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if (IS_ERR(clk_hw))
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return ERR_CAST(clk_hw);
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return clk_hw->clk;
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}
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static struct clk * __init
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r9a09g077_cpg_mux_clk_register(struct device *dev,
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const struct cpg_core_clk *core,
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void __iomem *addr, struct cpg_mssr_pub *pub)
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{
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struct clk_hw *clk_hw;
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clk_hw = devm_clk_hw_register_mux(dev, core->name,
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core->parent_names, core->num_parents,
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core->flag,
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addr,
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GET_SHIFT(core->conf),
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GET_WIDTH(core->conf),
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core->mux_flags, &pub->rmw_lock);
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if (IS_ERR(clk_hw))
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return ERR_CAST(clk_hw);
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return clk_hw->clk;
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}
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static struct clk * __init
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r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *core,
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const struct cpg_mssr_info *info,
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struct cpg_mssr_pub *pub)
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{
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u32 offset = GET_REG_OFFSET(core->conf);
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void __iomem *base = RZT2H_REG_BLOCK(offset) ? pub->base1 : pub->base0;
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void __iomem *addr = base + RZT2H_REG_OFFSET(offset);
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switch (core->type) {
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case CLK_TYPE_RZT2H_DIV:
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return r9a09g077_cpg_div_clk_register(dev, core, addr, pub);
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case CLK_TYPE_RZT2H_MUX:
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return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub);
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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const struct cpg_mssr_info r9a09g077_cpg_mssr_info = {
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/* Core Clocks */
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.core_clks = r9a09g077_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g077_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r9a09g077_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g077_mod_clks),
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.num_hw_mod_clks = 14 * 32,
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.reg_layout = CLK_REG_LAYOUT_RZ_T2H,
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.cpg_clk_register = r9a09g077_cpg_clk_register,
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};
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