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157f9533f9
While the GCC and Clang compilers already define __ASSEMBLER__ automatically when compiling assembler code, __ASSEMBLY__ is a macro that only gets defined by the Makefiles in the kernel. Defining such a macro was necessary in the early days of the kernel, since GCC only started providing __ASSEMBLER__ since version 3.0 in 2000 (see https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=f8f769ea4e69 ). However, having two macros can be very confusing nowadays for the developers when switching between userspace and kernelspace coding, or when dealing with uapi headers that should use __ASSEMBLER__ instead. So let's now standardize on the __ASSEMBLER__ macro that is provided by the compilers. This is almost a completely mechanical patch (done with a simple "sed -i" statement), with just one comment tweaked manually in arch/mips/include/asm/cpu.h (that was missing some underscores). Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@vger.kernel.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 by Ralf Baechle
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*/
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#ifndef __ASM_PREFETCH_H
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#define __ASM_PREFETCH_H
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/*
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* R5000 and RM5200 implements pref and prefx instructions but they're nops, so
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* rather than wasting time we pretend these processors don't support
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* prefetching at all.
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*
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* R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
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* StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
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*
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* Hell (and the book on my shelf I can't open ...) know what the R8000 does.
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*
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* RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
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* Pref_PrepareForStore also.
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*
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* RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
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* Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
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* current versions due to erratum G105.
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*
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* VR5500 (including VR5701 and VR7701) only implement load prefetch.
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*
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* Finally MIPS32 and MIPS64 implement all of the following hints.
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*/
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#define Pref_Load 0
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#define Pref_Store 1
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/* 2 and 3 are reserved */
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#define Pref_LoadStreamed 4
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#define Pref_StoreStreamed 5
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#define Pref_LoadRetained 6
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#define Pref_StoreRetained 7
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/* 8 ... 24 are reserved */
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#define Pref_WriteBackInvalidate 25
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#define Pref_PrepareForStore 30
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#ifdef __ASSEMBLER__
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.macro __pref hint addr
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#ifdef CONFIG_CPU_HAS_PREFETCH
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pref \hint, \addr
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#endif
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.endm
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.macro pref_load addr
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__pref Pref_Load, \addr
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.endm
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.macro pref_store addr
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__pref Pref_Store, \addr
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.endm
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.macro pref_load_streamed addr
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__pref Pref_LoadStreamed, \addr
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.endm
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.macro pref_store_streamed addr
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__pref Pref_StoreStreamed, \addr
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.endm
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.macro pref_load_retained addr
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__pref Pref_LoadRetained, \addr
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.endm
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.macro pref_store_retained addr
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__pref Pref_StoreRetained, \addr
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.endm
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.macro pref_wback_inv addr
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__pref Pref_WriteBackInvalidate, \addr
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.endm
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.macro pref_prepare_for_store addr
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__pref Pref_PrepareForStore, \addr
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.endm
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#endif
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#endif /* __ASM_PREFETCH_H */
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