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28fc0972e3
While tracking down a problem where constant expressions used by BUILD_BUG_ON() suddenly stopped working[1], we found that an added static initializer was convincing the compiler that it couldn't track the state of the prior statically initialized value. Tracing this down found that ffs() was used in the initializer macro, but since it wasn't marked with __attribute__const__, the compiler had to assume the function might change variable states as a side-effect (which is not true for ffs(), which provides deterministic math results). Add missing __attribute_const__ annotations to PARISC's implementations of ffs(), __ffs(), and fls() functions. These are pure mathematical functions that always return the same result for the same input with no side effects, making them eligible for compiler optimization. Build tested ARCH=parisc defconfig with GCC hppa-linux-gnu 14.2.0. Link: https://github.com/KSPP/linux/issues/364 [1] Acked-by: Helge Deller <deller@gmx.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20250804164417.1612371-13-kees@kernel.org Signed-off-by: Kees Cook <kees@kernel.org>
210 lines
5.4 KiB
C
210 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _PARISC_BITOPS_H
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#define _PARISC_BITOPS_H
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#ifndef _LINUX_BITOPS_H
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#error only <linux/bitops.h> can be included directly
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#endif
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#include <linux/compiler.h>
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#include <asm/types.h>
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#include <asm/byteorder.h>
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#include <asm/barrier.h>
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#include <linux/atomic.h>
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/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
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* on use of volatile and __*_bit() (set/clear/change):
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* *_bit() want use of volatile.
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* __*_bit() are "relaxed" and don't use spinlock or volatile.
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*/
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static __inline__ void set_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long flags;
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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*addr |= mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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}
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static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long flags;
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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*addr &= ~mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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}
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static __inline__ void change_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long flags;
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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*addr ^= mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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}
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static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long old;
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unsigned long flags;
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int set;
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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old = *addr;
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set = (old & mask) ? 1 : 0;
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if (!set)
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*addr = old | mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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return set;
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}
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static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long old;
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unsigned long flags;
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int set;
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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old = *addr;
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set = (old & mask) ? 1 : 0;
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if (set)
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*addr = old & ~mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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return set;
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}
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static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long oldbit;
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unsigned long flags;
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addr += BIT_WORD(nr);
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_atomic_spin_lock_irqsave(addr, flags);
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oldbit = *addr;
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*addr = oldbit ^ mask;
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_atomic_spin_unlock_irqrestore(addr, flags);
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return (oldbit & mask) ? 1 : 0;
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}
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#include <asm-generic/bitops/non-atomic.h>
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/**
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* __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
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* @word: The word to search
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*
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* __ffs() return is undefined if no bit is set.
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*
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* 32-bit fast __ffs by LaMont Jones "lamont At hp com".
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* 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
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* (with help from willy/jejb to get the semantics right)
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*
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* This algorithm avoids branches by making use of nullification.
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* One side effect of "extr" instructions is it sets PSW[N] bit.
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* How PSW[N] (nullify next insn) gets set is determined by the
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* "condition" field (eg "<>" or "TR" below) in the extr* insn.
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* Only the 1st and one of either the 2cd or 3rd insn will get executed.
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* Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
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* cycles for each mispredicted branch.
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*/
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static __inline__ __attribute_const__ unsigned long __ffs(unsigned long x)
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{
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unsigned long ret;
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__asm__(
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#ifdef CONFIG_64BIT
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" ldi 63,%1\n"
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" extrd,u,*<> %0,63,32,%%r0\n"
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" extrd,u,*TR %0,31,32,%0\n" /* move top 32-bits down */
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" addi -32,%1,%1\n"
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#else
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" ldi 31,%1\n"
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#endif
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" extru,<> %0,31,16,%%r0\n"
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" extru,TR %0,15,16,%0\n" /* xxxx0000 -> 0000xxxx */
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" addi -16,%1,%1\n"
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" extru,<> %0,31,8,%%r0\n"
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" extru,TR %0,23,8,%0\n" /* 0000xx00 -> 000000xx */
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" addi -8,%1,%1\n"
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" extru,<> %0,31,4,%%r0\n"
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" extru,TR %0,27,4,%0\n" /* 000000x0 -> 0000000x */
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" addi -4,%1,%1\n"
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" extru,<> %0,31,2,%%r0\n"
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" extru,TR %0,29,2,%0\n" /* 0000000y, 1100b -> 0011b */
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" addi -2,%1,%1\n"
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" extru,= %0,31,1,%%r0\n" /* check last bit */
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" addi -1,%1,%1\n"
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: "+r" (x), "=r" (ret) );
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return ret;
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}
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#include <asm-generic/bitops/ffz.h>
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/*
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* ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
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* This is defined the same way as the libc and compiler builtin
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* ffs routines, therefore differs in spirit from the above ffz (man ffs).
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*/
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static __inline__ __attribute_const__ int ffs(int x)
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{
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return x ? (__ffs((unsigned long)x) + 1) : 0;
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}
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/*
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* fls: find last (most significant) bit set.
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* fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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*/
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static __inline__ __attribute_const__ int fls(unsigned int x)
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{
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int ret;
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if (!x)
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return 0;
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__asm__(
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" ldi 1,%1\n"
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" extru,<> %0,15,16,%%r0\n"
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" zdep,TR %0,15,16,%0\n" /* xxxx0000 */
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" addi 16,%1,%1\n"
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" extru,<> %0,7,8,%%r0\n"
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" zdep,TR %0,23,24,%0\n" /* xx000000 */
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" addi 8,%1,%1\n"
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" extru,<> %0,3,4,%%r0\n"
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" zdep,TR %0,27,28,%0\n" /* x0000000 */
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" addi 4,%1,%1\n"
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" extru,<> %0,1,2,%%r0\n"
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" zdep,TR %0,29,30,%0\n" /* y0000000 (y&3 = 0) */
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" addi 2,%1,%1\n"
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" extru,= %0,0,1,%%r0\n"
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" addi 1,%1,%1\n" /* if y & 8, add 1 */
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: "+r" (x), "=r" (ret) );
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return ret;
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}
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic-setbit.h>
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#endif /* _PARISC_BITOPS_H */
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