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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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37dbd78f98
Both the decompressor and the core kernel implement an early #VC handler, which only deals with CPUID instructions, and full featured one, which can handle any #VC exception. The former communicates with the hypervisor using the MSR based protocol, whereas the latter uses a shared GHCB page, which is configured a bit later during the boot, when the kernel runs from its ordinary virtual mapping, rather than the 1:1 mapping that the startup code uses. Accessing this shared GHCB page from the core kernel's startup code is problematic, because it involves converting the GHCB address provided by the caller to a physical address. In the startup code, virtual to physical address translations are problematic, given that the virtual address might be a 1:1 mapped address, and such translations should therefore be avoided. This means that exposing startup code dealing with the GHCB to callers that execute from the ordinary kernel virtual mapping should be avoided too. So move all GHCB page based communication out of the startup code, now that all communication occurring before the kernel virtual mapping is up relies on the MSR protocol only. As an exception, add a flag representing the need to apply the coherency fix in order to avoid exporting CPUID* helpers because of the code running too early for the *cpu_has* infrastructure. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/20250828102202.1849035-29-ardb+git@google.com
111 lines
2.4 KiB
C
111 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/types.h>
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#include "bitops.h"
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#include <asm/processor-flags.h>
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#include <asm/msr-index.h>
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#include "cpuflags.h"
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struct cpu_features cpu;
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u32 cpu_vendor[3];
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static bool loaded_flags;
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static int has_fpu(void)
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{
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u16 fcw = -1, fsw = -1;
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unsigned long cr0;
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asm volatile("mov %%cr0,%0" : "=r" (cr0));
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if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
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cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
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asm volatile("mov %0,%%cr0" : : "r" (cr0));
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}
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asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
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: "+m" (fsw), "+m" (fcw));
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return fsw == 0 && (fcw & 0x103f) == 0x003f;
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}
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#ifdef CONFIG_X86_32
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/*
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* For building the 16-bit code we want to explicitly specify 32-bit
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* push/pop operations, rather than just saying 'pushf' or 'popf' and
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* letting the compiler choose.
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*/
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bool has_eflag(unsigned long mask)
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{
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unsigned long f0, f1;
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asm volatile("pushfl \n\t"
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"pushfl \n\t"
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"pop %0 \n\t"
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"mov %0,%1 \n\t"
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"xor %2,%1 \n\t"
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"push %1 \n\t"
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"popfl \n\t"
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"pushfl \n\t"
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"pop %1 \n\t"
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"popfl"
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: "=&r" (f0), "=&r" (f1)
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: "ri" (mask));
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return !!((f0^f1) & mask);
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}
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#endif
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void cpuid_count(u32 id, u32 count, u32 *a, u32 *b, u32 *c, u32 *d)
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{
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asm volatile("cpuid"
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: "=a" (*a), "=b" (*b), "=c" (*c), "=d" (*d)
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: "0" (id), "2" (count)
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);
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}
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#define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
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void get_cpuflags(void)
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{
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u32 max_intel_level, max_amd_level;
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u32 tfms;
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u32 ignored;
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if (loaded_flags)
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return;
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loaded_flags = true;
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if (has_fpu())
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set_bit(X86_FEATURE_FPU, cpu.flags);
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if (has_eflag(X86_EFLAGS_ID)) {
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cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2],
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&cpu_vendor[1]);
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if (max_intel_level >= 0x00000001 &&
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max_intel_level <= 0x0000ffff) {
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cpuid(0x1, &tfms, &ignored, &cpu.flags[4],
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&cpu.flags[0]);
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cpu.level = (tfms >> 8) & 15;
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cpu.family = cpu.level;
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cpu.model = (tfms >> 4) & 15;
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if (cpu.level >= 6)
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cpu.model += ((tfms >> 16) & 0xf) << 4;
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}
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if (max_intel_level >= 0x00000007) {
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cpuid_count(0x00000007, 0, &ignored, &ignored,
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&cpu.flags[16], &ignored);
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}
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cpuid(0x80000000, &max_amd_level, &ignored, &ignored,
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&ignored);
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if (max_amd_level >= 0x80000001 &&
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max_amd_level <= 0x8000ffff) {
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cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6],
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&cpu.flags[1]);
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}
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}
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}
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