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85a2d4a890
A while ago [0] FineIBT started using the 0xEA instruction to raise #UD.
All existing parts will generate #UD in 64bit mode on that instruction.
However; Intel/AMD have not blessed using this instruction, it is on
their 'reserved' opcode list for future use.
Peter Anvin worked the committees and got use of 0xD6 blessed, it
shall be called UDB (per the next SDM or so), and it being a single
byte instruction is easy to slip into a single byte immediate -- as
is done by this very patch.
Reworking the FineIBT code to use UDB wasn't entirely trivial. Notably
the FineIBT-BHI1 case ran out of bytes. In order to condense the
encoding some it was required to move the hash register from R10D to
EAX (thanks hpa!).
Per the x86_64 ABI, RAX is used to pass the number of vector registers
for vararg function calls -- something that should not happen in the
kernel. More so, the kernel is built with -mskip-rax-setup, which
should leave RAX completely unused, allowing its re-use.
[ For BPF; while the bpf2bpf tail-call uses RAX in its calling
convention, that does not use CFI and is unaffected. Only the
'regular' C->BPF transition is covered by CFI. ]
The ENDBR poison value is changed from 'OSP NOP3' to 'NOPL -42(%RAX)',
this is basically NOP4 but with UDB as its immediate. As such it is
still a non-standard NOP value unique to prior ENDBR sites, but now
also provides UDB.
Per Agner Fog's optimization guide, Jcc is assumed not-taken. That is,
the expected path should be the fallthrough case for improved
throughput.
Since the preamble now relies on the ENDBR poison to provide UDB, the
code is changed to write the poison right along with the initial
preamble -- this is possible because the ITS mitigation already
disabled IBT over rewriting the CFI scheme.
The scheme in detail:
Preamble:
FineIBT FineIBT-BHI1 FineIBT-BHI
__cfi_\func: __cfi_\func: __cfi_\func:
endbr endbr endbr
subl $0x12345678, %eax subl $0x12345678, %eax subl $0x12345678, %eax
jne.d32,np \func+3 cmovne %rax, %rdi cs cs call __bhi_args_N
jne.d8,np \func+3
\func: \func: \func:
nopl -42(%rax) nopl -42(%rax) nopl -42(%rax)
Notably there are 7 bytes available after the SUBL; this enables the
BHI1 case to fit without the nasty overlapping case it had previously.
The !BHI case uses Jcc.d32,np to consume all 7 bytes without the need
for an additional NOP, while the BHI case uses CS padding to align the
CALL with the end of the preamble such that it returns to \func+0.
Caller:
FineIBT Paranoid-FineIBT
fineibt_caller: fineibt_caller:
mov $0x12345678, %eax mov $0x12345678, %eax
lea -10(%r11), %r11 cmp -0x11(%r11), %eax
nop5 cs lea -0x10(%r11), %r11
retpoline: retpoline:
cs call __x86_indirect_thunk_r11 jne fineibt_caller+0xd
call *%r11
nop
Notably this is before apply_retpolines() which will fix up the
retpoline call -- since all parts with IBT also have eIBRS (lets
ignore ITS). Typically the retpoline site is rewritten (when still
intact) into:
call *%r11
nop3
[0] 06926c6cdb95 ("x86/ibt: Optimize the FineIBT instruction sequence")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20250901191307.GI4067720@noisy.programming.kicks-ass.net
111 lines
2.8 KiB
C
111 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_BUG_H
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#define _ASM_X86_BUG_H
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#include <linux/stringify.h>
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#include <linux/instrumentation.h>
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#include <linux/objtool.h>
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#include <asm/asm.h>
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/*
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* Despite that some emulators terminate on UD2, we use it for WARN().
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*/
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#define ASM_UD2 _ASM_BYTES(0x0f, 0x0b)
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#define INSN_UD2 0x0b0f
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#define LEN_UD2 2
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#define ASM_UDB _ASM_BYTES(0xd6)
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#define INSN_UDB 0xd6
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#define LEN_UDB 1
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/*
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* In clang we have UD1s reporting UBSAN failures on X86, 64 and 32bit.
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*/
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#define INSN_ASOP 0x67
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#define INSN_LOCK 0xf0
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#define OPCODE_ESCAPE 0x0f
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#define SECOND_BYTE_OPCODE_UD1 0xb9
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#define SECOND_BYTE_OPCODE_UD2 0x0b
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#define BUG_NONE 0xffff
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#define BUG_UD2 0xfffe
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#define BUG_UD1 0xfffd
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#define BUG_UD1_UBSAN 0xfffc
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#define BUG_UDB 0xffd6
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#define BUG_LOCK 0xfff0
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#ifdef CONFIG_GENERIC_BUG
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#ifdef CONFIG_X86_32
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# define __BUG_REL(val) ".long " val
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#else
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# define __BUG_REL(val) ".long " val " - ."
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#endif
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#ifdef CONFIG_DEBUG_BUGVERBOSE
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#define __BUG_ENTRY(file, line, flags) \
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"2:\t" __BUG_REL("1b") "\t# bug_entry::bug_addr\n" \
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"\t" __BUG_REL(file) "\t# bug_entry::file\n" \
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"\t.word " line "\t# bug_entry::line\n" \
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"\t.word " flags "\t# bug_entry::flags\n"
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#else
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#define __BUG_ENTRY(file, line, flags) \
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"2:\t" __BUG_REL("1b") "\t# bug_entry::bug_addr\n" \
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"\t.word " flags "\t# bug_entry::flags\n"
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#endif
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#define _BUG_FLAGS_ASM(ins, file, line, flags, size, extra) \
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"1:\t" ins "\n" \
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".pushsection __bug_table,\"aw\"\n" \
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__BUG_ENTRY(file, line, flags) \
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"\t.org 2b + " size "\n" \
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".popsection\n" \
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extra
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#define _BUG_FLAGS(ins, flags, extra) \
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do { \
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asm_inline volatile(_BUG_FLAGS_ASM(ins, "%c0", \
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"%c1", "%c2", "%c3", extra) \
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: : "i" (__FILE__), "i" (__LINE__), \
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"i" (flags), \
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"i" (sizeof(struct bug_entry))); \
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} while (0)
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#define ARCH_WARN_ASM(file, line, flags, size) \
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_BUG_FLAGS_ASM(ASM_UD2, file, line, flags, size, "")
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#else
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#define _BUG_FLAGS(ins, flags, extra) asm volatile(ins)
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#endif /* CONFIG_GENERIC_BUG */
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#define HAVE_ARCH_BUG
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#define BUG() \
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do { \
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instrumentation_begin(); \
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_BUG_FLAGS(ASM_UD2, 0, ""); \
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__builtin_unreachable(); \
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} while (0)
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/*
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* This instrumentation_begin() is strictly speaking incorrect; but it
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* suppresses the complaints from WARN()s in noinstr code. If such a WARN()
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* were to trigger, we'd rather wreck the machine in an attempt to get the
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* message out than not know about it.
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*/
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#define ARCH_WARN_REACHABLE ANNOTATE_REACHABLE(1b)
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#define __WARN_FLAGS(flags) \
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do { \
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__auto_type __flags = BUGFLAG_WARNING|(flags); \
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instrumentation_begin(); \
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_BUG_FLAGS(ASM_UD2, __flags, ARCH_WARN_REACHABLE); \
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instrumentation_end(); \
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} while (0)
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#include <asm-generic/bug.h>
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#endif /* _ASM_X86_BUG_H */
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