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c6f2dddfa7
Convert the PolarFire SoC clock driver to use regmaps instead of iomem
addresses as a preparatory work for supporting the new binding for this
device that will only provide the second of the two register regions, and
will require the use of syscon regmap to access the "cfg" and "periph"
clocks currently supported by the driver.
This is effectively a revert of commit 4da2404bb003 ("clk: microchip:
mpfs: convert cfg_clk to clk_divider") and commit d815569783e6 ("clk:
microchip: mpfs: convert periph_clk to clk_gate") as it resurrects the
ops structures removed in those commits, with the readl()s and
writel()s replaced by regmap_read()s and regmap_writes()s.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20251029-surfboard-refocus-ca9b135ab123@spud
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 lines
362 B
Plaintext
15 lines
362 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config COMMON_CLK_PIC32
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def_bool COMMON_CLK && MACH_PIC32
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config MCHP_CLK_MPFS
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bool "Clk driver for PolarFire SoC"
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depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
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default ARCH_MICROCHIP_POLARFIRE
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depends on MFD_SYSCON
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select AUXILIARY_BUS
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select REGMAP_MMIO
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help
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Supports Clock Configuration for PolarFire SoC
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