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mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-01-11 17:10:13 +00:00
Linus Torvalds 0623fdf30b phy-for-6.19
- Core
   - Drop Kishon as maintainer, thanks to him for helping, move to credits and
     add Neil to help with reviews.
   - Add new phy_notify_stat to notify phy from controllers during the
     runtime transitions and usage in samsung phy
 
  - New Support
   - Renesas RZ/G3E USB3.0 driver
   - NXP Support TJA1048/TJA1051 CAN phy
   - Rockchip support for rk3506 dsi dphy
   - Qualcomm Glymur QMP PCIe PHY support
 
 - Updates
   - PM support for rcar-gen3-usb2 driver
   - Samsung HDMI/eDP Transmitter Combo PHY updates
   - Freescale imx8mq support for alternate reference clock
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Merge tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Pull phy updates from Vinod Koul:
 "Core:
   - Drop Kishon as maintainer, thanks to him for helping, move to
     credits and add Neil to help with reviews.
   - Add new phy_notify_stat to notify phy from controllers during the
     runtime transitions and usage in samsung phy

  New hardware support:
   - Renesas RZ/G3E USB3.0 driver
   - NXP Support TJA1048/TJA1051 CAN phy
   - Rockchip support for rk3506 dsi dphy
   - Qualcomm Glymur QMP PCIe PHY support

  Updates:
   - PM support for rcar-gen3-usb2 driver
   - Samsung HDMI/eDP Transmitter Combo PHY updates
   - Freescale imx8mq support for alternate reference clock"

* tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits)
  MAINTAINERS: phy: Add Neil Armstrong as reviewers for phy subsystem
  MAINTAINERS: phy: Move Kishon Vijay Abraham I to credits
  phy: fsl-imx8mq-usb: support alternate reference clock
  dt-bindings: phy: imx8mq-usb: add alternate reference clock
  phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits
  phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth
  phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode
  phy: ti: gmii-sel: Add a sanity check on the phy_id
  phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY
  phy: qcom-qmp: pcs: Add v8.50 register offsets
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Restrict resets per each device
  phy: freescale: Initialize priv->lock
  phy: renesas: Remove unneeded semicolons
  phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE
  phy: qcom: qmp-combo: get the USB3 & DisplayPort lanes mapping from DT
  dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex
  phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
  phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
  phy: renesas: rcar-gen3-usb2: Add suspend/resume support
  ...
2025-12-09 06:31:47 +09:00

166 lines
3.5 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8MQ USB3 PHY
maintainers:
- Li Jun <jun.li@nxp.com>
properties:
compatible:
oneOf:
- enum:
- fsl,imx8mq-usb-phy
- fsl,imx8mp-usb-phy
- items:
- const: fsl,imx95-usb-phy
- const: fsl,imx8mp-usb-phy
reg:
minItems: 1
maxItems: 2
"#phy-cells":
const: 0
clocks:
minItems: 1
items:
- description: PHY configuration clock
- description: Alternate PHY reference clock
clock-names:
minItems: 1
items:
- const: phy
- const: alt
power-domains:
maxItems: 1
vbus-supply:
description:
A phandle to the regulator for USB VBUS.
fsl,phy-tx-vref-tune-percent:
description:
Tunes the HS DC level relative to the nominal level
minimum: 90
maximum: 124
fsl,phy-tx-rise-tune-percent:
description:
Adjusts the rise/fall time duration of the HS waveform relative to
its nominal value
minimum: 90
maximum: 120
fsl,phy-tx-preemp-amp-tune-microamp:
description:
Adjust amount of current sourced to DPn and DMn after a J-to-K
or K-to-J transition. Default is 0 (disabled).
minimum: 0
maximum: 1800
fsl,phy-tx-vboost-level-microvolt:
description:
Adjust the boosted transmit launch pk-pk differential amplitude
enum: [844, 1008, 1156]
fsl,phy-comp-dis-tune-percent:
description:
Adjust the voltage level used to detect a disconnect event at the host
relative to the nominal value
minimum: 91
maximum: 115
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db:
description:
Adjust TX de-emphasis attenuation in dB at nominal
3.5dB point as per USB specification
minimum: 0
maximum: 36
fsl,phy-pcs-tx-swing-full-percent:
description:
Scaling of the voltage defined by fsl,phy-tx-vboost-level-microvolt
minimum: 0
maximum: 100
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx95-usb-phy
then:
properties:
reg:
items:
- description: USB PHY Control range
- description: USB PHY TCA Block range
else:
properties:
reg:
maxItems: 1
- if:
properties:
compatible:
enum:
- fsl,imx8mq-usb-phy
- fsl,imx8mp-usb-phy
then:
properties:
fsl,phy-tx-vref-tune-percent:
minimum: 94
fsl,phy-tx-rise-tune-percent:
minimum: 97
maximum: 103
- if:
properties:
compatible:
contains:
enum:
- fsl,imx95-usb-phy
then:
properties:
fsl,phy-tx-vref-tune-percent:
maximum: 108
fsl,phy-comp-dis-tune-percent:
minimum: 94
maximum: 104
- if:
required:
- orientation-switch
then:
allOf:
- $ref: /schemas/usb/usb-switch.yaml#
- $ref: /schemas/usb/usb-switch-ports.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
usb3_phy0: phy@381f0040 {
compatible = "fsl,imx8mq-usb-phy";
reg = <0x381f0040 0x40>;
clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
clock-names = "phy";
#phy-cells = <0>;
};