mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-01-11 17:10:13 +00:00
- Core
- Drop Kishon as maintainer, thanks to him for helping, move to credits and
add Neil to help with reviews.
- Add new phy_notify_stat to notify phy from controllers during the
runtime transitions and usage in samsung phy
- New Support
- Renesas RZ/G3E USB3.0 driver
- NXP Support TJA1048/TJA1051 CAN phy
- Rockchip support for rk3506 dsi dphy
- Qualcomm Glymur QMP PCIe PHY support
- Updates
- PM support for rcar-gen3-usb2 driver
- Samsung HDMI/eDP Transmitter Combo PHY updates
- Freescale imx8mq support for alternate reference clock
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Merge tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"Core:
- Drop Kishon as maintainer, thanks to him for helping, move to
credits and add Neil to help with reviews.
- Add new phy_notify_stat to notify phy from controllers during the
runtime transitions and usage in samsung phy
New hardware support:
- Renesas RZ/G3E USB3.0 driver
- NXP Support TJA1048/TJA1051 CAN phy
- Rockchip support for rk3506 dsi dphy
- Qualcomm Glymur QMP PCIe PHY support
Updates:
- PM support for rcar-gen3-usb2 driver
- Samsung HDMI/eDP Transmitter Combo PHY updates
- Freescale imx8mq support for alternate reference clock"
* tag 'phy-for-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits)
MAINTAINERS: phy: Add Neil Armstrong as reviewers for phy subsystem
MAINTAINERS: phy: Move Kishon Vijay Abraham I to credits
phy: fsl-imx8mq-usb: support alternate reference clock
dt-bindings: phy: imx8mq-usb: add alternate reference clock
phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits
phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth
phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode
phy: ti: gmii-sel: Add a sanity check on the phy_id
phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY
phy: qcom-qmp: pcs: Add v8.50 register offsets
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Restrict resets per each device
phy: freescale: Initialize priv->lock
phy: renesas: Remove unneeded semicolons
phy: qcom: m31-eusb2: Update init sequence to set PHY_ENABLE
phy: qcom: qmp-combo: get the USB3 & DisplayPort lanes mapping from DT
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Document lanes mapping when not using in USB-C complex
phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562
phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
phy: renesas: rcar-gen3-usb2: Add suspend/resume support
...
166 lines
3.5 KiB
YAML
166 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8MQ USB3 PHY
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maintainers:
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- Li Jun <jun.li@nxp.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,imx8mq-usb-phy
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- fsl,imx8mp-usb-phy
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- items:
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- const: fsl,imx95-usb-phy
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- const: fsl,imx8mp-usb-phy
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reg:
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minItems: 1
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maxItems: 2
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"#phy-cells":
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const: 0
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clocks:
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minItems: 1
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items:
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- description: PHY configuration clock
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- description: Alternate PHY reference clock
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clock-names:
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minItems: 1
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items:
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- const: phy
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- const: alt
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power-domains:
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maxItems: 1
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vbus-supply:
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description:
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A phandle to the regulator for USB VBUS.
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fsl,phy-tx-vref-tune-percent:
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description:
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Tunes the HS DC level relative to the nominal level
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minimum: 90
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maximum: 124
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fsl,phy-tx-rise-tune-percent:
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description:
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Adjusts the rise/fall time duration of the HS waveform relative to
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its nominal value
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minimum: 90
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maximum: 120
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fsl,phy-tx-preemp-amp-tune-microamp:
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description:
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Adjust amount of current sourced to DPn and DMn after a J-to-K
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or K-to-J transition. Default is 0 (disabled).
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minimum: 0
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maximum: 1800
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fsl,phy-tx-vboost-level-microvolt:
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description:
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Adjust the boosted transmit launch pk-pk differential amplitude
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enum: [844, 1008, 1156]
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fsl,phy-comp-dis-tune-percent:
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description:
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Adjust the voltage level used to detect a disconnect event at the host
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relative to the nominal value
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minimum: 91
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maximum: 115
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fsl,phy-pcs-tx-deemph-3p5db-attenuation-db:
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description:
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Adjust TX de-emphasis attenuation in dB at nominal
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3.5dB point as per USB specification
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minimum: 0
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maximum: 36
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fsl,phy-pcs-tx-swing-full-percent:
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description:
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Scaling of the voltage defined by fsl,phy-tx-vboost-level-microvolt
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minimum: 0
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maximum: 100
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required:
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- compatible
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- reg
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- "#phy-cells"
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- clocks
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- clock-names
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx95-usb-phy
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then:
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properties:
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reg:
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items:
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- description: USB PHY Control range
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- description: USB PHY TCA Block range
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else:
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properties:
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mq-usb-phy
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- fsl,imx8mp-usb-phy
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then:
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properties:
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fsl,phy-tx-vref-tune-percent:
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minimum: 94
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fsl,phy-tx-rise-tune-percent:
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minimum: 97
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maximum: 103
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx95-usb-phy
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then:
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properties:
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fsl,phy-tx-vref-tune-percent:
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maximum: 108
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fsl,phy-comp-dis-tune-percent:
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minimum: 94
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maximum: 104
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- if:
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required:
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- orientation-switch
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then:
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allOf:
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- $ref: /schemas/usb/usb-switch.yaml#
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- $ref: /schemas/usb/usb-switch-ports.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mq-clock.h>
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usb3_phy0: phy@381f0040 {
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compatible = "fsl,imx8mq-usb-phy";
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reg = <0x381f0040 0x40>;
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clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
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clock-names = "phy";
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#phy-cells = <0>;
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};
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