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5888533c60
The "bus-r-dma" clock in the A523's PRCM clock controller is also
referred to as "DMA_CLKEN_SW" or "DMA ADB400 gating". It is unclear how
this ties into the DMA controller MBUS clock gate; however if the clock
is not enabled, the DMA controller in the MCU block will fail to access
DRAM, even failing to retrieve the DMA descriptors.
Mark this clock as critical. This sort of mirrors what is done for the
main DMA controller's MBUS clock, which has a separate toggle that is
currently left out of the main clock controller driver.
Fixes: 8cea339cfb81 ("clk: sunxi-ng: add support for the A523/T527 PRCM CCU")
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://patch.msgid.link/20251020171059.2786070-6-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
250 lines
7.9 KiB
C
250 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Arm Ltd.
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* Based on the D1 CCU driver:
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* Copyright (c) 2020 huangzhenwei@allwinnertech.com
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* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu-sun55i-a523-r.h"
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static const struct clk_parent_data r_ahb_apb_parents[] = {
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{ .fw_name = "hosc" },
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{ .fw_name = "losc" },
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{ .fw_name = "iosc" },
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{ .fw_name = "pll-periph" },
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{ .fw_name = "pll-audio" },
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};
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static SUNXI_CCU_M_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
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r_ahb_apb_parents, 0x000,
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0, 5, /* M */
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24, 3, /* mux */
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0);
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static SUNXI_CCU_M_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
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r_ahb_apb_parents, 0x00c,
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0, 5, /* M */
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24, 3, /* mux */
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0);
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static SUNXI_CCU_M_DATA_WITH_MUX(r_apb1_clk, "r-apb1",
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r_ahb_apb_parents, 0x010,
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0, 5, /* M */
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24, 3, /* mux */
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0);
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0",
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r_ahb_apb_parents, 0x100,
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0, 0, /* no M */
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1, 3, /* P */
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4, 3, /* mux */
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BIT(0),
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0);
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1",
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r_ahb_apb_parents, 0x104,
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0, 0, /* no M */
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1, 3, /* P */
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4, 3, /* mux */
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BIT(0),
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0);
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static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2",
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r_ahb_apb_parents, 0x108,
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0, 0, /* no M */
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1, 3, /* P */
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4, 3, /* mux */
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BIT(0),
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0);
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static SUNXI_CCU_GATE_HW(bus_r_timer_clk, "bus-r-timer", &r_ahb_clk.common.hw,
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0x11c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_twd_clk, "bus-r-twd", &r_apb0_clk.common.hw,
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0x12c, BIT(0), 0);
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static const struct clk_parent_data r_pwmctrl_parents[] = {
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{ .fw_name = "hosc" },
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{ .fw_name = "losc" },
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{ .fw_name = "iosc" },
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};
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static SUNXI_CCU_MUX_DATA_WITH_GATE(r_pwmctrl_clk, "r-pwmctrl",
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r_pwmctrl_parents, 0x130,
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24, 2, /* mux */
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BIT(31),
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0);
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static SUNXI_CCU_GATE_HW(bus_r_pwmctrl_clk, "bus-r-pwmctrl",
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&r_apb0_clk.common.hw, 0x13c, BIT(0), 0);
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/* SPI clock is /M/N (same as new MMC?) */
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static SUNXI_CCU_GATE_HW(bus_r_spi_clk, "bus-r-spi",
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&r_ahb_clk.common.hw, 0x15c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_spinlock_clk, "bus-r-spinlock",
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&r_ahb_clk.common.hw, 0x16c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox",
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&r_ahb_clk.common.hw, 0x17c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_uart0_clk, "bus-r-uart0",
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&r_apb1_clk.common.hw, 0x18c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_uart1_clk, "bus-r-uart1",
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&r_apb1_clk.common.hw, 0x18c, BIT(1), 0);
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static SUNXI_CCU_GATE_HW(bus_r_i2c0_clk, "bus-r-i2c0",
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&r_apb1_clk.common.hw, 0x19c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_i2c1_clk, "bus-r-i2c1",
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&r_apb1_clk.common.hw, 0x19c, BIT(1), 0);
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static SUNXI_CCU_GATE_HW(bus_r_i2c2_clk, "bus-r-i2c2",
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&r_apb1_clk.common.hw, 0x19c, BIT(2), 0);
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static SUNXI_CCU_GATE_HW(bus_r_ppu0_clk, "bus-r-ppu0",
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&r_apb0_clk.common.hw, 0x1ac, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_ppu1_clk, "bus-r-ppu1",
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&r_apb0_clk.common.hw, 0x1ac, BIT(1), 0);
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static SUNXI_CCU_GATE_HW(bus_r_cpu_bist_clk, "bus-r-cpu-bist",
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&r_apb0_clk.common.hw, 0x1bc, BIT(0), 0);
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static const struct clk_parent_data r_ir_rx_parents[] = {
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{ .fw_name = "losc" },
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{ .fw_name = "hosc" },
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};
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static SUNXI_CCU_M_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
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r_ir_rx_parents, 0x1c0,
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0, 5, /* M */
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24, 2, /* mux */
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BIT(31), /* gate */
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0);
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static SUNXI_CCU_GATE_HW(bus_r_ir_rx_clk, "bus-r-ir-rx",
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&r_apb0_clk.common.hw, 0x1cc, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_dma_clk, "bus-r-dma",
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&r_apb0_clk.common.hw, 0x1dc, BIT(0), CLK_IS_CRITICAL);
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static SUNXI_CCU_GATE_HW(bus_r_rtc_clk, "bus-r-rtc",
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&r_apb0_clk.common.hw, 0x20c, BIT(0), 0);
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static SUNXI_CCU_GATE_HW(bus_r_cpucfg_clk, "bus-r-cpucfg",
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&r_apb0_clk.common.hw, 0x22c, BIT(0), CLK_IS_CRITICAL);
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static struct ccu_common *sun55i_a523_r_ccu_clks[] = {
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&r_ahb_clk.common,
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&r_apb0_clk.common,
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&r_apb1_clk.common,
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&r_cpu_timer0.common,
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&r_cpu_timer1.common,
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&r_cpu_timer2.common,
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&bus_r_timer_clk.common,
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&bus_r_twd_clk.common,
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&r_pwmctrl_clk.common,
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&bus_r_pwmctrl_clk.common,
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&bus_r_spi_clk.common,
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&bus_r_spinlock_clk.common,
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&bus_r_msgbox_clk.common,
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&bus_r_uart0_clk.common,
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&bus_r_uart1_clk.common,
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&bus_r_i2c0_clk.common,
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&bus_r_i2c1_clk.common,
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&bus_r_i2c2_clk.common,
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&bus_r_ppu0_clk.common,
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&bus_r_ppu1_clk.common,
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&bus_r_cpu_bist_clk.common,
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&r_ir_rx_clk.common,
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&bus_r_ir_rx_clk.common,
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&bus_r_dma_clk.common,
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&bus_r_rtc_clk.common,
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&bus_r_cpucfg_clk.common,
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};
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static struct clk_hw_onecell_data sun55i_a523_r_hw_clks = {
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.num = CLK_NUMBER,
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.hws = {
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[CLK_R_AHB] = &r_ahb_clk.common.hw,
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[CLK_R_APB0] = &r_apb0_clk.common.hw,
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[CLK_R_APB1] = &r_apb1_clk.common.hw,
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[CLK_R_TIMER0] = &r_cpu_timer0.common.hw,
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[CLK_R_TIMER1] = &r_cpu_timer1.common.hw,
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[CLK_R_TIMER2] = &r_cpu_timer2.common.hw,
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[CLK_BUS_R_TIMER] = &bus_r_timer_clk.common.hw,
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[CLK_BUS_R_TWD] = &bus_r_twd_clk.common.hw,
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[CLK_R_PWMCTRL] = &r_pwmctrl_clk.common.hw,
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[CLK_BUS_R_PWMCTRL] = &bus_r_pwmctrl_clk.common.hw,
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[CLK_BUS_R_SPI] = &bus_r_spi_clk.common.hw,
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[CLK_BUS_R_SPINLOCK] = &bus_r_spinlock_clk.common.hw,
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[CLK_BUS_R_MSGBOX] = &bus_r_msgbox_clk.common.hw,
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[CLK_BUS_R_UART0] = &bus_r_uart0_clk.common.hw,
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[CLK_BUS_R_UART1] = &bus_r_uart1_clk.common.hw,
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[CLK_BUS_R_I2C0] = &bus_r_i2c0_clk.common.hw,
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[CLK_BUS_R_I2C1] = &bus_r_i2c1_clk.common.hw,
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[CLK_BUS_R_I2C2] = &bus_r_i2c2_clk.common.hw,
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[CLK_BUS_R_PPU0] = &bus_r_ppu0_clk.common.hw,
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[CLK_BUS_R_PPU1] = &bus_r_ppu1_clk.common.hw,
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[CLK_BUS_R_CPU_BIST] = &bus_r_cpu_bist_clk.common.hw,
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[CLK_R_IR_RX] = &r_ir_rx_clk.common.hw,
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[CLK_BUS_R_IR_RX] = &bus_r_ir_rx_clk.common.hw,
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[CLK_BUS_R_DMA] = &bus_r_dma_clk.common.hw,
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[CLK_BUS_R_RTC] = &bus_r_rtc_clk.common.hw,
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[CLK_BUS_R_CPUCFG] = &bus_r_cpucfg_clk.common.hw,
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},
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};
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static struct ccu_reset_map sun55i_a523_r_ccu_resets[] = {
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[RST_BUS_R_TIMER] = { 0x11c, BIT(16) },
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[RST_BUS_R_TWD] = { 0x12c, BIT(16) },
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[RST_BUS_R_PWMCTRL] = { 0x13c, BIT(16) },
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[RST_BUS_R_SPI] = { 0x15c, BIT(16) },
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[RST_BUS_R_SPINLOCK] = { 0x16c, BIT(16) },
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[RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },
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[RST_BUS_R_UART0] = { 0x18c, BIT(16) },
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[RST_BUS_R_UART1] = { 0x18c, BIT(17) },
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[RST_BUS_R_I2C0] = { 0x19c, BIT(16) },
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[RST_BUS_R_I2C1] = { 0x19c, BIT(17) },
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[RST_BUS_R_I2C2] = { 0x19c, BIT(18) },
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[RST_BUS_R_PPU1] = { 0x1ac, BIT(17) },
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[RST_BUS_R_IR_RX] = { 0x1cc, BIT(16) },
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[RST_BUS_R_RTC] = { 0x20c, BIT(16) },
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[RST_BUS_R_CPUCFG] = { 0x22c, BIT(16) },
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[RST_BUS_R_PPU0] = { 0x1ac, BIT(16) },
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};
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static const struct sunxi_ccu_desc sun55i_a523_r_ccu_desc = {
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.ccu_clks = sun55i_a523_r_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun55i_a523_r_ccu_clks),
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.hw_clks = &sun55i_a523_r_hw_clks,
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.resets = sun55i_a523_r_ccu_resets,
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.num_resets = ARRAY_SIZE(sun55i_a523_r_ccu_resets),
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};
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static int sun55i_a523_r_ccu_probe(struct platform_device *pdev)
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{
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void __iomem *reg;
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reg = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(reg))
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return PTR_ERR(reg);
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return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_r_ccu_desc);
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}
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static const struct of_device_id sun55i_a523_r_ccu_ids[] = {
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{ .compatible = "allwinner,sun55i-a523-r-ccu" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun55i_a523_r_ccu_ids);
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static struct platform_driver sun55i_a523_r_ccu_driver = {
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.probe = sun55i_a523_r_ccu_probe,
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.driver = {
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.name = "sun55i-a523-r-ccu",
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.suppress_bind_attrs = true,
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.of_match_table = sun55i_a523_r_ccu_ids,
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},
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};
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module_platform_driver(sun55i_a523_r_ccu_driver);
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MODULE_IMPORT_NS("SUNXI_CCU");
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MODULE_DESCRIPTION("Support for the Allwinner A523 PRCM CCU");
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MODULE_LICENSE("GPL");
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