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torvalds-linux/arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
Linus Walleij ececfba255 ARM: dts: ixp4xx: Fix up Actiontec MI424WR DTS files
The KS8995 switch was unconditionally wired to EthC (eth1)
on both MI424WR variants, this is wrong: the D revision has
the switch connected to EthB (eth0) so pull this assingment
out of the generic MI424WR DTSI file and make it a property
of the respective variants instead.

Signed-off-by: Linus Walleij <linusw@kernel.org>
Link: https://patch.msgid.link/20251211-ixp4xx-actiontec-dts-fix-v1-1-97af8e79d474@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2025-12-15 21:15:36 +01:00

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// SPDX-License-Identifier: ISC
/*
* Device Tree file for the IXP425-based Actiontec MI424WR revision D
* Based on a board file from OpenWrt by Jose Vasconcellos.
*/
/dts-v1/;
#include "intel-ixp42x-actiontec-mi424wr.dtsi"
/ {
model = "Actiontec MI424WR rev D";
compatible = "actiontec,mi424wr-d", "intel,ixp42x";
/* Connect the switch to EthB */
spi {
ethernet-switch@0 {
ethernet-ports {
ethernet-port@4 {
ethernet = <&ethb>;
};
};
};
};
soc {
/* EthB used for LAN */
ethernet@c8009000 {
/* Fixed link to the CPU MII port on the KS8995 */
fixed-link {
speed = <100>;
full-duplex;
};
mdio {
/* PHY ID 0x00221450 */
phy5: ethernet-phy@5 {
/* WAN */
reg = <5>;
};
};
};
/* EthC used for WAN */
ethernet@c800a000 {
phy-handle = <&phy5>; // 5 on revision D
};
};
};