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dt-bindings: pinctrl: Convert marvell,armada-3710-(sb|nb)-pinctrl to DT schema
Convert the marvell,armada3710-(sb|nb)-pinctrl binding to DT schema format. The binding includes the "marvell,armada-3700-xtal-clock" subnode which is simple enough to include here. Mark interrupt-controller/#interrupt-cells as required as the users have them and the h/w is either capable of interrupts or not. As this syscon has 2 register ranges, syscon-common.yaml needs to be updated to drop the restriction of 1 register entry. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Rob Herring (Arm)
Linus Walleij
parent
d51093cf01
commit
c1c9641a04
@ -1,29 +0,0 @@
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* Xtal Clock bindings for Marvell Armada 37xx SoCs
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Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by
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reading the gpio latch register.
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This node must be a subnode of the node exposing the register address
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of the GPIO block where the gpio latch is located.
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See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-3700-xtal-clock"
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- #clock-cells : from common clock binding; shall be set to 0
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Optional properties:
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- clock-output-names : from common clock binding; allows overwrite default clock
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output names ("xtal")
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Example:
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pinctrl_nb: pinctrl-nb@13800 {
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compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
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reg = <0x13800 0x100>, <0x13C00 0x20>;
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xtalclk: xtal-clk {
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compatible = "marvell,armada-3700-xtal-clock";
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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};
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@ -35,9 +35,6 @@ properties:
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minItems: 2
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maxItems: 5 # Should be enough
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reg:
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maxItems: 1
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reg-io-width:
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description:
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The size (in bytes) of the IO accesses that should be performed
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@ -1,195 +0,0 @@
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* Marvell Armada 37xx SoC pin and gpio controller
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Each Armada 37xx SoC come with two pin and gpio controller one for the
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south bridge and the other for the north bridge.
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Inside this set of register the gpio latch allows exposing some
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configuration of the SoC and especially the clock frequency of the
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xtal. Hence, this node is a represent as syscon allowing sharing the
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register between multiple hardware block.
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GPIO and pin controller:
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------------------------
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Main node:
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Refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning
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of the phrase "pin configuration node".
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Required properties for pinctrl driver:
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- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
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for the south bridge
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"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
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for the north bridge
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- reg: The first set of register are for pinctrl/gpio and the second
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set for the interrupt controller
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- interrupts: list of the interrupt use by the gpio
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Available groups and functions for the North bridge:
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group: jtag
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- pins 20-24
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- functions jtag, gpio
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group sdio0
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- pins 8-10
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- functions sdio, gpio
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group emmc_nb
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- pins 27-35
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- functions emmc, gpio
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group pwm0
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- pin 11 (GPIO1-11)
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- functions pwm, led, gpio
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group pwm1
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- pin 12
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- functions pwm, led, gpio
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group pwm2
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- pin 13
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- functions pwm, led, gpio
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group pwm3
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- pin 14
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- functions pwm, led, gpio
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group pmic1
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- pin 7
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- functions pmic, gpio
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group pmic0
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- pin 6
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- functions pmic, gpio
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group i2c2
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- pins 2-3
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- functions i2c, gpio
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group i2c1
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- pins 0-1
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- functions i2c, gpio
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group spi_cs1
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- pin 17
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- functions spi, gpio
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group spi_cs2
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- pin 18
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- functions spi, gpio
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group spi_cs3
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- pin 19
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- functions spi, gpio
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group onewire
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- pin 4
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- functions onewire, gpio
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group uart1
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- pins 25-26
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- functions uart, gpio
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group spi_quad
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- pins 15-16
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- functions spi, gpio
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group uart2
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- pins 9-10 and 18-19
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- functions uart, gpio
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Available groups and functions for the South bridge:
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group usb32_drvvbus0
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- pin 36
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- functions drvbus, gpio
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group usb2_drvvbus1
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- pin 37
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- functions drvbus, gpio
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group sdio_sb
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- pins 60-65
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- functions sdio, gpio
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group rgmii
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- pins 42-53
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- functions mii, gpio
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group pcie1
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- pins 39
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- functions pcie, gpio
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group pcie1_clkreq
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- pins 40
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- functions pcie, gpio
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group pcie1_wakeup
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- pins 41
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- functions pcie, gpio
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group smi
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- pins 54-55
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- functions smi, gpio
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group ptp
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- pins 56
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- functions ptp, gpio
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group ptp_clk
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- pin 57
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- functions ptp, mii
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group ptp_trig
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- pin 58
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- functions ptp, mii
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group mii_col
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- pin 59
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- functions mii, mii_err
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GPIO subnode:
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Please refer to gpio.txt in this directory for details of gpio-ranges property
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and the common GPIO bindings used by client devices.
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Required properties for gpio driver under the gpio subnode:
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- interrupts: List of interrupt specifier for the controllers interrupt.
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- gpio-controller: Marks the device node as a gpio controller.
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- #gpio-cells: Should be 2. The first cell is the GPIO number and the
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second cell specifies GPIO flags, as defined in
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<dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
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GPIO_ACTIVE_LOW flags are supported.
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- gpio-ranges: Range of pins managed by the GPIO controller.
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Xtal Clock bindings for Marvell Armada 37xx SoCs
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------------------------------------------------
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see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
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Example:
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pinctrl_sb: pinctrl-sb@18800 {
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compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpio {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 29>;
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gpio-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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rgmii_pins: mii-pins {
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groups = "rgmii";
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function = "mii";
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};
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};
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@ -0,0 +1,124 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 37xx SoC pin and gpio controller
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maintainers:
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- Gregory CLEMENT <gregory.clement@bootlin.com>
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- Marek Behún <kabel@kernel.org>
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- Miquel Raynal <miquel.raynal@bootlin.com>
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description: >
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Each Armada 37xx SoC come with two pin and gpio controller one for the south
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bridge and the other for the north bridge.
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Inside this set of register the gpio latch allows exposing some configuration
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of the SoC and especially the clock frequency of the xtal. Hence, this node is
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a represent as syscon allowing sharing the register between multiple hardware
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block.
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properties:
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compatible:
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items:
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- enum:
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- marvell,armada3710-sb-pinctrl
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- marvell,armada3710-nb-pinctrl
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- const: syscon
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- const: simple-mfd
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reg:
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items:
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- description: pinctrl and GPIO controller registers
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- description: interrupt controller registers
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gpio:
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description: GPIO controller subnode
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type: object
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additionalProperties: false
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properties:
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'#gpio-cells':
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const: 2
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gpio-controller: true
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gpio-ranges:
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description: Range of pins managed by the GPIO controller
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'#interrupt-cells':
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const: 2
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interrupt-controller: true
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interrupts:
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description: List of interrupt specifiers for the GPIO controller
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required:
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- '#gpio-cells'
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- gpio-ranges
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- gpio-controller
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- '#interrupt-cells'
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- interrupt-controller
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- interrupts
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xtal-clk:
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type: object
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additionalProperties: false
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properties:
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compatible:
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const: marvell,armada-3700-xtal-clock
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'#clock-cells':
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const: 0
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clock-output-names: true
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patternProperties:
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'-pins$':
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$ref: pinmux-node.yaml#
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additionalProperties: false
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properties:
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groups:
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enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
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pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
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ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
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spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
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usb2_drvvbus1, usb32_drvvbus ]
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function:
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enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
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pcie, pmic, ptp, pwm, sdio, smi, spi, uart ]
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl_sb: pinctrl@18800 {
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compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpio {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 29>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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