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soc: fixes for 6.19

Browse Source 
The main code change is a revert of the Raspberry Pi RP1 overlay
 support that was decided to not be ready.
 
 The other fixes are all for devicetree sources:
 
  - ethernet configuration on ixp42x-actiontec-mi424wr is
    board revision specific
 
  - validation warning fixes for imx27/imx51/imx6, hikey960 and k3
 
  - Minor corrections across imx8 boards, addressing all types of
    issues with interrups, dma, ethernet and clock settings, all
    simple one-line changes.
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Merge tag 'soc-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC fixes from Arnd Bergmann:
 "The main code change is a revert of the Raspberry Pi RP1 overlay
  support that was decided to not be ready.

  The other fixes are all for devicetree sources:

   - ethernet configuration on ixp42x-actiontec-mi424wr is board
     revision specific

   - validation warning fixes for imx27/imx51/imx6, hikey960 and k3

   - Minor corrections across imx8 boards, addressing all types of
     issues with interrups, dma, ethernet and clock settings, all simple
     one-line changes"

* tag 'soc-fixes-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
  arm64: dts: hisilicon: hikey960: Drop "snps,gctl-reset-quirk" and "snps,tx_de_emphasis*" properties
  Documentation/process: maintainer-soc: Mark 'make' as commands
  Documentation/process: maintainer-soc: Be more explicit about defconfig
  arm64: dts: mba8mx: Fix Ethernet PHY IRQ support
  arm64: dts: imx8qm-ss-dma: correct the dma channels of lpuart
  arm64: dts: imx8mp: Fix LAN8740Ai PHY reference clock on DH electronics i.MX8M Plus DHCOM
  arm64: dts: freescale: tx8p-ml81: fix eqos nvmem-cells
  arm64: dts: freescale: moduline-display: fix compatible
  dt-bindings: arm: fsl: moduline-display: fix compatible
  ARM: dts: imx6q-ba16: fix RTC interrupt level
  arm64: dts: freescale: imx95-toradex-smarc: fix SMARC_SDIO_WP label position
  arm64: dts: freescale: imx95-toradex-smarc: use edge trigger for ethphy1 interrupt
  arm64: dts: add off-on-delay-us for usdhc2 regulator
  arm64: dts: imx8qm-mek: correct the light sensor interrupt type to low level
  ARM: dts: nxp: imx: Fix mc13xxx LED node names
  arm64: dts: imx95: correct I3C2 pclk to IMX95_CLK_BUSWAKEUP
  MAINTAINERS: Fix a linusw mail address
  arm64: dts: broadcom: rp1: drop RP1 overlay
  arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topology
  misc: rp1: drop overlay support
  ...
This commit is contained in:
Linus Torvalds 2026-01-09 15:11:45 -10:00
commit e55feea3a0
34 changed files with 111 additions and 150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@ -1105,7 +1105,6 @@ properties:
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
- gocontroll,moduline-display # GOcontroll Moduline Display controller
- prt,prt8ml # Protonic PRT8ML
- skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
@ -1164,6 +1163,14 @@ properties:
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
- const: fsl,imx8mp
- description: Ka-Ro TX8P-ML81 SoM based boards
items:
- enum:
- gocontroll,moduline-display
- gocontroll,moduline-display-106
- const: karo,tx8p-ml81
- const: fsl,imx8mp
- description: Kontron i.MX8MP OSM-S SoM based Boards
items:
- const: kontron,imx8mp-bl-osm-s # Kontron BL i.MX8MP OSM-S Board

8
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
View File

@ -25,6 +25,10 @@ properties:
items:
- const: pci1de4,1
reg:
maxItems: 1
description: The PCI Bus-Device-Function address.
'#interrupt-cells':
const: 2
description: |
@ -101,6 +105,7 @@ unevaluatedProperties: false
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- pci-ep-bus@1
@ -111,8 +116,9 @@ examples:
#address-cells = <3>;
#size-cells = <2>;
rp1@0,0 {
dev@0,0 {
compatible = "pci1de4,1";
reg = <0x10000 0x0 0x0 0x0 0x0>;
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
#address-cells = <3>;
#size-cells = <2>;

10
Documentation/process/maintainer-soc.rst
View File

@ -57,8 +57,10 @@ Submitting Patches for Given SoC
All typical platform related patches should be sent via SoC submaintainers
(platform-specific maintainers). This includes also changes to per-platform or
shared defconfigs (scripts/get_maintainer.pl might not provide correct
addresses in such case).
shared defconfigs. Note that scripts/get_maintainer.pl might not provide
correct addresses for the shared defconfig, so ignore its output and manually
create CC-list based on MAINTAINERS file or use something like
``scripts/get_maintainer.pl -f drivers/soc/FOO/``).
Submitting Patches to the Main SoC Maintainers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@ -114,9 +116,9 @@ coordinating how the changes get merged through different maintainer trees.
Usually the branch that includes a driver change will also include the
corresponding change to the devicetree binding description, to ensure they are
in fact compatible. This means that the devicetree branch can end up causing
warnings in the "make dtbs_check" step. If a devicetree change depends on
warnings in the ``make dtbs_check`` step. If a devicetree change depends on
missing additions to a header file in include/dt-bindings/, it will fail the
"make dtbs" step and not get merged.
``make dtbs`` step and not get merged.
There are multiple ways to deal with this:

2
MAINTAINERS
View File

@ -2012,7 +2012,7 @@ ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS)
M: Arnd Bergmann <arnd@arndb.de>
M: Krzysztof Kozlowski <krzk@kernel.org>
M: Alexandre Belloni <alexandre.belloni@bootlin.com>
M: Linus Walleij <linus.walleij@linaro.org>
M: Linus Walleij <linusw@kernel.org>
R: Drew Fustini <fustini@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: soc@lists.linux.dev

11
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-ac.dts
View File

@ -12,6 +12,17 @@
model = "Actiontec MI424WR rev A/C";
compatible = "actiontec,mi424wr-ac", "intel,ixp42x";
/* Connect the switch to EthC */
spi {
ethernet-switch@0 {
ethernet-ports {
ethernet-port@4 {
ethernet = <&ethc>;
};
};
};
};
soc {
/* EthB used for WAN */
ethernet@c8009000 {

11
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr-d.dts
View File

@ -12,6 +12,17 @@
model = "Actiontec MI424WR rev D";
compatible = "actiontec,mi424wr-d", "intel,ixp42x";
/* Connect the switch to EthB */
spi {
ethernet-switch@0 {
ethernet-ports {
ethernet-port@4 {
ethernet = <&ethb>;
};
};
};
};
soc {
/* EthB used for LAN */
ethernet@c8009000 {

1
arch/arm/boot/dts/intel/ixp/intel-ixp42x-actiontec-mi424wr.dtsi
View File

@ -152,7 +152,6 @@
};
ethernet-port@4 {
reg = <4>;
ethernet = <&ethc>;
phy-mode = "mii";
fixed-link {
speed = <100>;

8
arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts
View File

@ -248,14 +248,14 @@
linux,default-trigger = "nand-disk";
};
ledg3: led@10 {
reg = <10>;
ledg3: led@a {
reg = <0xa>;
label = "system:green3:live";
linux,default-trigger = "heartbeat";
};
ledb3: led@11 {
reg = <11>;
ledb3: led@b {
reg = <0xb>;
label = "system:blue3:cpu";
linux,default-trigger = "cpu0";
};

4
arch/arm/boot/dts/nxp/imx/imx51-zii-rdu1.dts
View File

@ -398,13 +398,13 @@
#size-cells = <0>;
led-control = <0x0 0x0 0x3f83f8 0x0>;
sysled0@3 {
led@3 {
reg = <3>;
label = "system:green:status";
linux,default-trigger = "default-on";
};
sysled1@4 {
led@4 {
reg = <4>;
label = "system:green:act";
linux,default-trigger = "heartbeat";

4
arch/arm/boot/dts/nxp/imx/imx51-zii-scu2-mezz.dts
View File

@ -225,13 +225,13 @@
#size-cells = <0>;
led-control = <0x0 0x0 0x3f83f8 0x0>;
sysled3: led3@3 {
sysled3: led@3 {
reg = <3>;
label = "system:red:power";
linux,default-trigger = "default-on";
};
sysled4: led4@4 {
sysled4: led@4 {
reg = <4>;
label = "system:green:act";
linux,default-trigger = "heartbeat";

4
arch/arm/boot/dts/nxp/imx/imx51-zii-scu3-esb.dts
View File

@ -153,13 +153,13 @@
#size-cells = <0>;
led-control = <0x0 0x0 0x3f83f8 0x0>;
sysled3: led3@3 {
sysled3: led@3 {
reg = <3>;
label = "system:red:power";
linux,default-trigger = "default-on";
};
sysled4: led4@4 {
sysled4: led@4 {
reg = <4>;
label = "system:green:act";
linux,default-trigger = "heartbeat";

2
arch/arm/boot/dts/nxp/imx/imx6q-ba16.dtsi
View File

@ -337,7 +337,7 @@
pinctrl-0 = <&pinctrl_rtc>;
reg = <0x32>;
interrupt-parent = <&gpio4>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
};
};

4
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -7,15 +7,13 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \
bcm2712-rpi-5-b.dtb \
bcm2712-rpi-5-b-ovl-rp1.dtb \
bcm2712-d-rpi-5-b.dtb \
bcm2837-rpi-2-b.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2837-rpi-zero-2-w.dtb \
rp1.dtbo
bcm2837-rpi-zero-2-w.dtb
subdir-y += bcmbca
subdir-y += northstar2

0
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts → arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
View File

39
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
View File

@ -1,22 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make
* the RP1 driver to load the RP1 dtb overlay at runtime, while
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
* already contains RP1 node, so no overlay is loaded nor needed).
* This file is intended to host the override nodes for the RP1 peripherals,
* e.g. to declare the phy of the ethernet interface or the custom pin setup
* for several RP1 peripherals.
* This in turn is due to the fact that there's no current generic
* infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that
* are not yet defined in the DT since they are loaded at runtime via overlay.
* As a loose attempt to separate RP1 customizations from SoC peripherals
* definitioni, this file is intended to host the override nodes for the RP1
* peripherals, e.g. to declare the phy of the ethernet interface or custom
* pin setup.
* All other nodes that do not have anything to do with RP1 should be added
* to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.
* to the included bcm2712-rpi-5-b-base.dtsi instead.
*/
/dts-v1/;
#include "bcm2712-rpi-5-b-ovl-rp1.dts"
#include "bcm2712-rpi-5-b-base.dtsi"
/ {
aliases {
@ -25,7 +19,26 @@
};
&pcie2 {
#include "rp1-nexus.dtsi"
pci@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
bus-range = <0 1>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
dev@0,0 {
compatible = "pci1de4,1";
reg = <0x10000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x0 0x82010000 0x0 0x0 0x0 0x400000>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <3>;
#size-cells = <2>;
#include "rp1-common.dtsi"
};
};
};
&rp1_eth {

14
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
View File

@ -1,14 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
rp1_nexus {
compatible = "pci1de4,1";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01 0x00 0x00000000
0x02000000 0x00 0x00000000
0x0 0x400000>;
interrupt-controller;
#interrupt-cells = <2>;
#include "rp1-common.dtsi"
};

11
arch/arm64/boot/dts/broadcom/rp1.dtso
View File

@ -1,11 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
/plugin/;
&pcie2 {
#address-cells = <3>;
#size-cells = <2>;
#include "rp1-nexus.dtsi"
};

1
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@ -113,6 +113,7 @@
ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */
compatible = "ethernet-phy-id0007.c110",
"ethernet-phy-ieee802.3-c22";
clocks = <&clk IMX8MP_CLK_ENET_QOS>;
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&pinctrl_ethphy0>;

2
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81-moduline-display-106.dts
View File

@ -9,7 +9,7 @@
#include "imx8mp-tx8p-ml81.dtsi"
/ {
compatible = "gocontroll,moduline-display", "fsl,imx8mp";
compatible = "gocontroll,moduline-display-106", "karo,tx8p-ml81", "fsl,imx8mp";
chassis-type = "embedded";
hardware = "Moduline Display V1.06";
model = "GOcontroll Moduline Display baseboard";

5
arch/arm64/boot/dts/freescale/imx8mp-tx8p-ml81.dtsi
View File

@ -47,6 +47,7 @@
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <266000000>, <100000000>, <50000000>;
nvmem-cells = <&eth_mac1>;
phy-handle = <&ethphy0>;
phy-mode = "rmii";
pinctrl-0 = <&pinctrl_eqos>;
@ -75,6 +76,10 @@
};
};
&fec {
nvmem-cells = <&eth_mac2>;
};
&gpio1 {
gpio-line-names = "SODIMM_152",
"SODIMM_42",

3
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@ -263,6 +263,7 @@
regulator-max-microvolt = <3000000>;
gpio = <&lsio_gpio4 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <4800>;
};
reg_audio: regulator-audio {
@ -576,7 +577,7 @@
compatible = "isil,isl29023";
reg = <0x44>;
interrupt-parent = <&lsio_gpio4>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
pressure-sensor@60 {

8
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View File

@ -172,25 +172,25 @@
&lpuart0 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 13 0 0>, <&edma2 12 0 1>;
dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 13 0 0>;
dma-names = "rx","tx";
};
&lpuart1 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 15 0 0>, <&edma2 14 0 1>;
dmas = <&edma2 14 0 FSL_EDMA_RX>, <&edma2 15 0 0>;
dma-names = "rx","tx";
};
&lpuart2 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 17 0 0>, <&edma2 16 0 1>;
dmas = <&edma2 16 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
dma-names = "rx","tx";
};
&lpuart3 {
compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
dmas = <&edma2 19 0 0>, <&edma2 18 0 1>;
dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
dma-names = "rx","tx";
};

4
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
View File

@ -406,8 +406,6 @@
"",
"",
"",
"",
"",
"SMARC_SDIO_WP";
};
@ -582,7 +580,7 @@
ethphy1: ethernet-phy@1 {
reg = <1>;
interrupt-parent = <&som_gpio_expander_1>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};

2
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@ -828,7 +828,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&scmi_clk IMX95_CLK_BUSAON>,
clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>,
<&scmi_clk IMX95_CLK_I3C2SLOW>;
clock-names = "pclk", "fast_clk";
status = "disabled";

2
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@ -192,7 +192,7 @@
reset-assert-us = <500000>;
reset-deassert-us = <500>;
interrupt-parent = <&expander2>;
interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
};
};
};

3
arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
View File

@ -675,10 +675,7 @@
snps,lfps_filter_quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,tx_de_emphasis_quirk;
snps,tx_de_emphasis = <1>;
snps,dis_enblslpm_quirk;
snps,gctl-reset-quirk;
usb-role-switch;
role-switch-default-mode = "host";
port {

2
arch/arm64/boot/dts/ti/k3-am62-lp-sk-nand.dtso
View File

@ -14,7 +14,7 @@
};
&main_pmx0 {
gpmc0_pins_default: gpmc0-pins-default {
gpmc0_pins_default: gpmc0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x003c, PIN_INPUT, 0) /* (K19) GPMC0_AD0 */
AM62X_IOPAD(0x0040, PIN_INPUT, 0) /* (L19) GPMC0_AD1 */

7
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-peb-c-010.dtso
View File

@ -30,13 +30,10 @@
<&main_pktdma 0xc206 15>, /* egress slice 1 */
<&main_pktdma 0xc207 15>, /* egress slice 1 */
<&main_pktdma 0x4200 15>, /* ingress slice 0 */
<&main_pktdma 0x4201 15>, /* ingress slice 1 */
<&main_pktdma 0x4202 0>, /* mgmnt rsp slice 0 */
<&main_pktdma 0x4203 0>; /* mgmnt rsp slice 1 */
<&main_pktdma 0x4201 15>; /* ingress slice 1 */
dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
"tx1-0", "tx1-1", "tx1-2", "tx1-3",
"rx0", "rx1",
"rxmgm0", "rxmgm1";
"rx0", "rx1";
firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
"ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",

8
arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso
View File

@ -20,13 +20,13 @@
};
&main_pmx0 {
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default {
main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */
>;
};
main_spi1_pins_default: main-spi1-pins-default {
main_spi1_pins_default: main-spi1-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
@ -35,7 +35,7 @@
>;
};
main_uart3_pins_default: main-uart3-pins-default {
main_uart3_pins_default: main-uart3-default-pins {
pinctrl-single,pins = <
AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */
AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */
@ -52,7 +52,7 @@
&main_spi1 {
pinctrl-names = "default";
pinctrl-0 = <&main_spi1_pins_default>;
ti,pindir-d0-out-d1-in = <1>;
ti,pindir-d0-out-d1-in;
status = "okay";
};

6
drivers/misc/rp1/Kconfig
View File

@ -5,8 +5,7 @@
config MISC_RP1
tristate "RaspberryPi RP1 misc device"
depends on OF_IRQ && OF_OVERLAY && PCI_MSI && PCI_QUIRKS
select PCI_DYNAMIC_OF_NODES
depends on OF_IRQ && PCI_MSI
help
Support the RP1 peripheral chip found on Raspberry Pi 5 board.
@ -15,6 +14,3 @@ config MISC_RP1
The driver is responsible for enabling the DT node once the PCIe
endpoint has been configured, and handling interrupts.
This driver uses an overlay to load other drivers to support for
RP1 internal sub-devices.

3
drivers/misc/rp1/Makefile
View File

@ -1,3 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MISC_RP1) += rp1-pci.o
rp1-pci-objs := rp1_pci.o rp1-pci.dtbo.o
obj-$(CONFIG_MISC_RP1) += rp1_pci.o

25
drivers/misc/rp1/rp1-pci.dtso
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* The dts overlay is included from the dts directory so
* it can be possible to check it with CHECK_DTBS while
* also compile it from the driver source directory.
*/
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path="";
__overlay__ {
compatible = "pci1de4,1";
#address-cells = <3>;
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#include "arm64/broadcom/rp1-common.dtsi"
};
};
};

37
drivers/misc/rp1/rp1_pci.c
View File

@ -34,16 +34,11 @@
/* Interrupts */
#define RP1_INT_END 61
/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */
extern char __dtbo_rp1_pci_begin[];
extern char __dtbo_rp1_pci_end[];
struct rp1_dev {
struct pci_dev *pdev;
struct irq_domain *domain;
struct irq_data *pcie_irqds[64];
void __iomem *bar1;
int ovcs_id; /* overlay changeset id */
bool level_triggered_irq[RP1_INT_END];
};
@ -184,24 +179,13 @@ static void rp1_unregister_interrupts(struct pci_dev *pdev)
static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
u32 dtbo_size = __dtbo_rp1_pci_end - __dtbo_rp1_pci_begin;
void *dtbo_start = __dtbo_rp1_pci_begin;
struct device *dev = &pdev->dev;
struct device_node *rp1_node;
bool skip_ovl = true;
struct rp1_dev *rp1;
int err = 0;
int i;
/*
* Either use rp1_nexus node if already present in DT, or
* set a flag to load it from overlay at runtime
*/
rp1_node = of_find_node_by_name(NULL, "rp1_nexus");
if (!rp1_node) {
rp1_node = dev_of_node(dev);
skip_ovl = false;
}
rp1_node = dev_of_node(dev);
if (!rp1_node) {
dev_err(dev, "Missing of_node for device\n");
@ -276,42 +260,29 @@ static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
rp1_chained_handle_irq, rp1);
}
if (!skip_ovl) {
err = of_overlay_fdt_apply(dtbo_start, dtbo_size, &rp1->ovcs_id,
rp1_node);
if (err)
goto err_unregister_interrupts;
}
err = of_platform_default_populate(rp1_node, NULL, dev);
if (err) {
dev_err_probe(&pdev->dev, err, "Error populating devicetree\n");
goto err_unload_overlay;
goto err_unregister_interrupts;
}
if (skip_ovl)
of_node_put(rp1_node);
of_node_put(rp1_node);
return 0;
err_unload_overlay:
of_overlay_remove(&rp1->ovcs_id);
err_unregister_interrupts:
rp1_unregister_interrupts(pdev);
err_put_node:
if (skip_ovl)
of_node_put(rp1_node);
of_node_put(rp1_node);
return err;
}
static void rp1_remove(struct pci_dev *pdev)
{
struct rp1_dev *rp1 = pci_get_drvdata(pdev);
struct device *dev = &pdev->dev;
of_platform_depopulate(dev);
of_overlay_remove(&rp1->ovcs_id);
rp1_unregister_interrupts(pdev);
}

1
drivers/pci/quirks.c
View File

@ -6308,7 +6308,6 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0, of_pci_make_dev_node);
/*
* Devices known to require a longer delay before first config space access